PI6C2504A [PERICOM]
Phase-Locked Loop Clock Driver with 4 Clock Outputs; 锁相环时钟驱动器有4个时钟输出型号: | PI6C2504A |
厂家: | PERICOM SEMICONDUCTOR CORPORATION |
描述: | Phase-Locked Loop Clock Driver with 4 Clock Outputs |
文件: | 总4页 (文件大小:295K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PI6C2504A
Phase-Locked Loop Clock Driver
with 4 Clock Outputs
ProductFeatures
ProductDescription
• High-PerformancePhase-Locked-LoopClock
ThePI6C2504Afeaturesalow-skew,low-jitter,phase-lockedloop
(PLL) clock driver, distributing high-frequency clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delayfromtheCLK_INinputtoanyclockoutputwillbenearlyzero.
DistributionforNetworking
• Registered DIMM Synchronous DRAM modules
for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
• Zero Input-to-Output delay
• Lowjitter:Cycle-to-Cyclejitter±75psmax.
• On-chip series damping resistor at clock output
drivers for low noise and EMI reduction
• Operatesat3.3VVCC
• Wide range of Clock Frequencies 80 to 134 MHz
• Package:Plastic16-pinQSOPPackage(Q)
LogicBlockDiagram
ProductPinConfiguration
G
CLK_IN
AGND
1
2
3
4
5
6
7
16
15
14
13
12
11
10
4
CLK_IN
Y[0:3]
V
CC
Y0
Y1
AV
CC
PLL
FB_IN
GND
GND
Y3
16-Pin
Q
FB_OUT
AV
CC
GND
V
Y2
CC
FunctionalTable
G
V
CC
Inputs
Outputs
FB_IN
FB_OUT
8
9
G
L
Y[0:3]
L
FB_OUT
CLK_IN
CLK_IN
H
CLK_IN
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PI6C2504A
Phase-LockedLoopClockDriver
with4ClockOutputs
PinFunctions
Pin Name Pin No.
Type
Description
CLK_IN
FB_IN
G
16
9
I
I
I
Reference Clock input. CLK_IN allows spread spectrum clock input.
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Output bank enable. When G is LOW, outputs Y[0:3] are disabled to a logic low state.
7
Feedback output. FB_OUT is dedicated for external feedback. FB_OUT has an embedded
series-damping resistor of the same value as the clock outputs Yx.
FB_OUT
Y[0:3]
8
O
O
Clock outputs. These outputs provide low-skew copies of CLK_IN
Each output has an embedded series-damping resistor.
3,4,11,12
Analog power supply. For test purposes, AVCC can be also used to bypass the PLL. When
AVCC
15
Power AVCC is strapped to ground, PLL is bypassed and CLK_IN is buffered directly to the device
outputs.
AGND
VCC
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
Power Power supply.
2, 6, 10
GND
5, 13, 14 Ground Ground
DC Specifications (Absolute maximum ratings over operating free-air temperature range)
Symbol
Parameter
Min.
Max.
+0.5
Units
V
I
Input voltage range
Output voltage range
DC input voltage
DC output current
V
CC
V
O
0.5
V
V
I_DC
3.8
I
100
1.0
mA
W
O_DC
o
Power
Maximum power dissipation at T = 55 C in still air
A
o
T
STG
Storage temperature
65
150
C
Note:
Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device.
Parameter
Test Conditions
V
CC
Min.
Typ.
Max.
Units
(1)
I
CC
V = V or GND; I = 0 Standby Current
3.6V
10
µA
I
CC
O
C
V = V or GND
4
6
I
I
CC
3.3V
pF
C
V =V or GND
O CC
O
Note:
1. Continuous Output Current
Recommended Operating Conditions
Symbol
Parameter
Min.
Max.
Units
VCC
VIH
VIL
VI
Supply voltage
3.0
2.0
3.6
High level input voltage
Low level input voltage
Input voltage
V
0.8
VCC
70
0
0
TA
Operating free-air temperature
ºC
PS8501
10/02/00
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PI6C2504A
Phase-LockedLoopClockDriver
with4ClockOutputs
ElectricalCharacteristics(OverRecommendedOperatingFree-AirTemperatureRange
PullUp/DownCurrentsofPI6C2504A,VCC =3.0V)
Symbol
Parameter
Condition
Vout = 2.4V
Min.
Max.
13.6
22
Units
Pull-up current
Pull-up current
I
OH
Vout = 2.0V
Vout = 0.8V
mA
Pull-down current
Pull-down current
19
13
I
OL
Vout = 0.55V
AC Specifications
(Timing requirements over recommended ranges of supply voltage and operating free-air temperature)
Symbol
Parameter
Clock frequency PI6C2504A
Input clock duty cycle
Min.
80
Max.
134
60
Units
F
MHz
%
CLK
D
CYI
40
Stabilization Time after power up
1
ms
SwitchingCharacteristics
(Over recommended ranges of supply voltage and operating free-air temperature, CL = 30pF)
V
= 3.3V ±0.3V, 0-70°C
CC
Parameter
From (Input)
To (Output)
Units
Min.
Typ.
Max.
tphase error without jitter
CLK_IN↑ at 100 & 66 MHz
FB_IN↑
150
+150
ps
Jitter, cycle-to-cycle
Duty cycle
At 100 & 66 MHz
75
45
+75
55
%
ns
CLK_OUT
tr, rise-time, 0.4V to 2.0V
tf, fall-time, 2.0V to 0.4V
1.0
1.1
Note:
These switching parameters are guaranteed by design.
PS8501
10/02/00
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PI6C2504A
Phase-LockedLoopClockDriver
with4ClockOutputs
Package Mechanical Information: 16-pin QSOP Package (Q).
°
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
PI6C2504AQ
Q16
16-pin QSOP
Commercial
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8501
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