PI6C3991JIE [PERICOM]
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| 型号： | PI6C3991JIE |
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PERICOM SEMICONDUCTOR CORPORATION |
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PI6C3991
3.3V High-Speed, Low-Voltage
Programmable Skew Clock Buffer
SuperClock
Features
Description
All output pair skew <100ps typical (250 Max.)
3.75 MHz to 80 MHz output operation
User-selectable output functions
Selectable skew to 18ns
PI6C3991 offers selectable control over system clock functions.
These multiple-output clock drivers provide the system integrator
with functions necessary to optimize the timing of high-perfor-
mancecomputersystems.Eightindividualdrivers,arrangedasfour
pairs of user-controllable outputs, can each drive terminated trans-
mission lines with impedances as low as 50 ohms while delivering
minimal and specified output skews and full-swing logic levels
(LVTTL).
Inverted and Non-Inverted
Operation at ½ and ¼ input frequency
Operation at 2X and 4X input frequency
(input as low as 3.75 MHz, x4 operation)
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal zero skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
up to ±12 time units.
Zero input-to-output delay
50% duty-cycle outputs
LVTTLoutputsdrive50-ohmterminatedlines
Operates from a single 3.3V supply
Low operating current
Divide-by-two and divide-by-four output functions are provided
foradditionalflexibilityindesigningcomplexclocksystems.When
combined with the internal PLL, these divide functions allow
distribution of a low-frequency clock that can be multiplied by
two or four at the clock destination. This feature allows flexibility
and simplifies system timing distribution design for complex
high-speed systems.
Availablein32-pinPLCC(J)package
Jitter < 200ps peak-to-peak (< 25ps RMS)
PinConfiguration
LogicBlockDiagram
Test
Phase
Freq.
DET
FB
VCO and
Time Unit
Generator
Filter
REF
4
3
2
1
32 31 30
5
29
28
27
26
25
24
23
22
21
3F1
4F0
4F1
2F0
GND
1F1
1F0
FS
6
4Q0
4Q1
7
4F0
4F1
8
V
CCQ
32-Pin
J
Select Inputs
(three level)
9
V
V
CCN
4Q1
CCN
Skew
3Q0
3Q1
10
11
12
13
1Q0
1Q1
GND
GND
3F0
3F1
4Q0
Select
GND
GND
2Q0
2Q1
2F0
2F1
Matrix
14 15 16 17 18 19 20
1Q0
1Q1
1F0
1F1
PS8450B
04/09/01
1
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
PinDescriptions
Signal Name
I/O
Description
REF
I
Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured.
PLL feedback input (typically connected to one of the eight outputs)
Three-level frequency range select. see Table 1.
FB
I
FS
I
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
I
Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
Three-level select. See test mode section under the block diagram descriptions
Output pair 1. See Table 2
I
I
I
I
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
VCCN
O
O
O
O
Output pair 2. See Table 2
Output pair 3. See Table 2
Output pair 4. See Table 2
PWR Power supply for output drivers
PWR Power supply for internal circuitry
PWR Ground
VCCQ
GND
Table2.ProgrammableSkewConfigurations(1)
Table1.FrequencyRangeSelectandt Calculation(1)
U
1
Function Selects
Output Functions
tU =
Approximate
Freq. (MHz) at
which tU= 1.0ns
FNOM(MHz)
f
NOM × N
FS(1,2)
1F1, 2F1,
1F0, 2F0,
3F0, 4F0
1Q0, 1Q1,
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
where N=
3F1, 4F1
LOW
LOW
LOW
MID
Min.
15
Max.
30
LOW
MID
4tU
3tU
2tU
1tU
0tU
Divide by 2 Divide by 2
LOW
MID
44
26
16
22.7
38.5
62.5
6tU
4tU
6tU
4tU
25
40
50
80
HIGH
LOW
MID
HIGH
2tU
2tU
MID
0tU
0tU
MID
HIGH
LOW
MID
+1tU
+2tU
+3tU
+4tU
+2tU
+2tU
+4tU
+6tU
Inverted
HIGH
HIGH
HIGH
+4tU
+6tU
HIGH
Divide by 4
Notes:
1. For all three-state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an
CC
open connection. Internal termination circuitry holds an unconnected input to V /2.
CC
2. The level to be set on FS is determined by the normal operating frequency (f ) and Time Unit Generator
NOM
(see Logic Block Diagram). Nominal frequency (f ) always appears at 1Q0 and the other outputs when they are operated in
NOM
their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f
when the output connected
NOM
to FB is undivided. The frequency of the REF and FB inputs will be f /2 or f /4 when the part is configured for a frequency
NOM NOM
multiplication by using a divided output as the FB input.
PS8450B
04/09/01
2
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
Test Mode
Block Diagram Description
TheTESTinputisathree-levelinput. Innormalsystemoperation,
this pin is connected to ground, allowing the PI6C3991 to operate
as explained briefly above (for testing purposes, any of the three
levelinputscanhavearemovablejumpertoground,orbetiedLOW
through a 100 Ohm resistor. This will allow an external tester to
change the state of these pins.)
IftheTESTinputisforcedtoitsMIDorHIGHstate,thedevicewill
operatewithitsinternalphaselockedloopdisconnected, andinput
levels supplied to REF will directly control all outputs. Relative
output to output functions are the same as in normal mode.
Phase Frequency Detector and Filter
These two blocks accept input signals from the reference frequency
(REF) input and the feedback (FB) input and generate correction
information to control the frequency of the Voltage-Controlled
Oscillator (VCO). These blocks, along with the VCO, form a Phase-
Locked Loop (PLL) that tracks the incoming REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency that is used by the time unit generator
to create discrete time units that are selected in the skew mix matrix.
The operational range of the VCO is determined by the FS control
pin. The time unit (tU) is determined by the operating frequency of
the device and the level of the FS pin as shown in Table 1.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
Skew Select Matrix
MaximumRatings
Storage Temperature ...................................... 65°Cto+150°C
AmbientTemperaturewith
PowerApplied.................................................55°Cto+125°C
Supply Voltage to Ground Potential.................. 0.5Vto+7.0V
DC Input Voltage ...............................................0.5Vto+7.0V
Output Current into Outputs (LOW) ............................... 64mA
Static Discharge Voltage ............................................... >2001V
(perMIL-STD-883,Method3015)
The skew select matrix is comprised of four independent sections.
Each section has two low-skew, high-fanout drivers (xQ0, xQ1),
and two corresponding three-level function select (xF0, xF1)
inputs. Table 2 shows the nine possible output functions for each
section as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0tU selected.
Latch-UpCurrent .........................................................>200mA
FB Input
REF Input
OperatingRange
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
1Fx
2Fx
3Fx
4Fx
3.3V ±10%
3.3V ±10%
(N/A)
LL
LM
LH
–6t
–4t
–3t
–2t
–1t
0t
U
U
U
40°C to +85°C
LM (N/A)
LH ML
ML (N/A)
MM MM
Note:
U
U
3. FB connected to an output selected for "zero" skew
(ie.,xF1=xF0=MID).
U
U
MH
HL
(N/A) +1t
MH +2t
(N/A) +3t
U
U
U
U
HM
HH
HL
+4t
+6t
(N/A)
HM
(N/A) LL/HH Divided
(N/A)
HH Invert
Figure1.TypicalOutputswithFBConnectedtoa
(3)
Zero-SkewOutput
PS8450B
04/09/01
3
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
Capacitance(6)
Parameter
Description
Test Conditions
Max.
Units
C
Input Capacitance
T = 25°C, f = 1MHz, V = 3.3V
10
pF
IN
A
CC
ElectricalCharacteristics(OvertheOperatingRange)
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
Min.
Max.
Units
VCC = Min., IOH = 12mA
2.4
VOL
Output LOW Voltage
VCC = Min., IOL = 35mA
0.45
VCC
Input HIGH Voltage (REF & FB
inputs only)
VIH
VIL
2.0
0.5
Input LOW Voltage (REF & FB inputs
only)
0.8
V
Three-Level Input HIGH Voltage
(Test, FS, xFn)(4)
VIHH
VIMM
VILL
IIH
Min. ≤ VCC ≤ Max.
0.87 VCC
VCC
Three-Level Input MID Voltage
(Test, FS, xFn)(4)
Min. ≤ VCC ≤ Max.
0.47 VCC 0.53 VCC
Three-Level Input LOW Voltage
(Test, FS, xFn)(4)
Min. ≤ VCC ≤ Max.
0.0
0.13 VCC
20
Input HIGH Leakage Current
(REF & FB inputs only)
VCC = Max., VIN = Max.
VCC = Max., VIN = 0.4V
Input LOW Leakage Current
(REF & FB inputs only)
IIL
20
µA
IIHH
IIMM
IILL
Input HIGH Current (Test, FS, xFn)
Input MID Current (Test, FS, xFn)
Input LOW Current (Test, FS, xFn)
Short Circuit Current(5)
VIN = VCC
200
50
VIN = VCC/2
50
VIN = GND
200
IOS
VCC = Max., VOUT = GND (25°C only)
200
95
mA
mA
ICCQ
Operating Current Used by Internal
Circuitry
VCCN = VCCQ = Max.,
All Input Selects Open
Com'l
Mil/Ind
100
ICCN
Output Buffer Current per Output Pair VCCN = VCCQ = Max.,
IOUT = 0mA
19
mA
All Input Selects Open, fMAX
PD
Power Dissipation per Output Pair
VCCN = VCCQ = Max.,
IOUT = 0mA
104
mW
All Input Selects Open, fMAX
Notes:
4. These inputs are normally wired to V , GND, or left unconnected (actual threshold voltages vary as a percentage of V ). Internal
CC
CC
termination resistors hold unconnected inputs at V /2. If these inputs are switched, the function and timing of the outputs may glitch
CC
and the PLL may require an additional t
time before all data sheet limits are achieved.
LOCK
5. PI6C3991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
Roomtemperatureonly.
6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
PS8450B
04/09/01
4
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
SwitchingCharacteristicsPI6C3991(OvertheOperatingRange)(2,7)
PI6C3991-2
PI6C3991-5
PI6C3991
Parameter
Description
Min.
15
Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
(1,2)
(1,2)
(1,2)
FS = LOW
30
50
80
15
25
30
50
80
15
25
30
50
80
Operating
Clock Frequency
in MHz
f
FS = MID
25
MHz
ns
NOM
FS = HIGH
40
40
40
t
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
5.0
5.0
5.0
5.0
5.0
5.0
RPWH
t
RPWL
t
U
See Table 1
0.05
0.1
See Table 1
0.1 0.25
See Table 1
(9,10)
t
Zero Output Matched-Pair Skew (XQ0, XQ1)
0.2
0.25
0.5
0.1
0.3
0.6
1.0
0.7
1.2
0.25
0.75
1.0
SKEWPR
(9,11)
t
Zero Output Skew (All Outputs)
0.25
0.6
0.5
0.5
0.5
0.5
0.7
1.0
0.7
1.0
1.25
SKEW0
(9,13)
t
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
0.1
SKEW1
(9,13)
(9,13)
t
0.5
1.0
1.5
SKEW2
t
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
0.25
0.5
0.5
1.2
SKEW3
(9,13)
t
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted
0.9
1.7
SKEW4
(8,14)
t
Device-to-Device Dkew
1.25
1.65
ns
DEV
t
Propagation Delay, REF Rise to FB Rise
0.25
0.65
0.0
0.0
+0.25 0.5
+0.65 1.0
2.0
0.0 +0.5 0.7
0.0
0.0
+0.7
+1.2
3
PD
(15)
t
Output Duty Cycle Variation
0.0 +1.0 1.2
ODCV
(16)
t
Output HIGH Time Deviation from 50%
2.5
3.0
PWH
(16)
t
Output LOW Time Deviation from 50%
1.5
3.5
2.5
2.5
0.5
25
PWL
(16,17)
t
Output Rise Time
0.15
0.15
1.0
1.0
1.2
1.2
0.5
25
0.15
0.15
1.0
1.0
1.5
1.5
0.5
25
0.15
0.15
1.5
1.5
ORISE
(16,17)
t
Output Fall Time
OFALL
(18)
t
PLL Lock Time
ms
ps
LOCK
(8)
RMS
Cycle-to-cycle
Output Jitter
t
JR
(8)
Peak-to-peak
200
200
200
Notes:
7. TestmeasurementlevelsforthePI6C3991areTTLlevels(1.5Vto1.5V). Testconditionsassumesignaltransitiontimesof2ns orless
and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t delay has
U
been selected when all are loaded with 30pF and terminated with 50 Ohm to V /2.
CC
10. t
11. t
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t .
U
SKEWPR
is defined as the skew between outputs when they are selected for 0t . Other outputs are divided or inverted but not shifted.
SKEW0
U
12. C = 0pF. For C = 30pF, t = 0.35ns.
SKEW0
L
L
13. There are three classes of outputs: Nominal (multiple of t delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided
U
(3Qxand4QxonlyinDivide-by-2orDivide-by-4mode).
14. t
is the output-to-output skew between any two devices operating under the same conditions (V ambient temperature, air flow,
CC
DEV
etc.)
15. t
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
and t
SKEW4
ODCV
SKEW2
specifications.
16. Specified with outputs loaded with 30pF for the PI6C3991 and PI6C3991-5 devices. Devices are terminated through 50 Ohm to V
/
CC
2. t
is measured at 2.0V. t
is measured at 0.8V.
PWL
PWH
17. t
18. t
and t
measured between 0.8V and 2.0V.
ORISE
LOCK
OFALL
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within
CC
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t is within
PD
specifiedlimits.
PS8450B
04/09/01
5
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
AC Test Loads and Waveforms
TTL AC Test Load
TTL Input Test Waveform
VCC
≤1ns
≤1ns
R1
3.0V
2.0V
Vth=1.5V
0.8V
0V
C
L
R2
R1=100
R2=100
C =30pF
L
(Includes fixture and probe capacitance)
ACTimingDiagrams
t
t
REF
RPWL
t
RPWH
REF
t
PD
t
t
ODCV
ODCV
FB
Q
t
JR
t
SKEWPR
t
SKEWPR
t
SKEW0, 1
t
SKEW0, 1
Other Q
t
t
SKEW2
SKEW2
Inverted Q
t
t
SKEW3,4
t
t
SKEW3,4
SKEW3,4
SKEW2,4
REF Divided by 2
t
SKEW1,3,4
REF Divided by 4
PS8450B
04/09/01
6
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
OperationalModeDescriptions
REF
FB
LOAD
System Clock
REF
FS
L1
Z
Z
0
0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
LOAD
L2
L3
L4
Z
Z
0
0
LENGTH: L1 = L2 = L3 = L4
Figure2.Zero-Skewand/orZero-DelayClockDriver
Figure 2 shows the SuperClock configured as a zero-skew clock
buffer.InthismodethePI6C3991canbeusedasthebasisforalow-
skew clock distribution tree. When all of the function select inputs
(xF0, xF1) are left open, the outputs are aligned and may each drive
aterminatedtransmissionlinetoanindependentload.TheFBinput
can be tied to any output in this configuration and the operating
frequency range is selected with the FS pin. The low-skew specifi-
cation,coupledwiththeabilitytodriveterminatedtransmissionlines
(withimpedancesaslowas50Ohm),allowsefficientprintedcircuit
board design.
REF
FB
LOAD
LOAD
System Clock
REF
FS
L1
L2
Z
Z
0
0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
L3
L4
LOAD
LOAD
Z
Z
0
0
LENGTH: L1 = L2, L3 < L2 by 6", L4 > L2 by 6"
Figure3.ProgrammableSkewClockDriver
PS8450B
04/09/01
7
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
Figure 3 shows a configuration to equalize skew between metal Figure4showsanexampleoftheinvertfunctionoftheSuperClock.
tracesofdifferentlengths. Inadditiontolowskewbetweenoutputs, In this example the 4Q0 output used as the FB input is programmed
the SuperClock can be programmed to stagger the timing of its forinvert(4F0=4F1=HIGH)whiletheotherthreepairsofoutputs
outputs. The four groups of output pairs can each be programmed areprogrammedforzeroskew.When4F0and4F1aretiedHIGH,4Q0
to different output timing. Skew timing can be adjusted over a wide and 4Q1 become inverted zero phase outputs. The PLL aligns the
range in small increments with the appropriate strapping of the rising edge of the FB input with the rising edge of the REF. This
functionselectpins. Inthisconfigurationthe4Q0outputisfedback causesthe1Q,2Q,and3Qoutputstobecometheinvertedoutputs
to FB and configured for zero skew.
with respect to the REF input. By selecting which output is connect
to FB, it is possible to have 2 inverted and 6 non-inverted outputs
or6invertedand2non-invertedoutputs.Thecorrectconfigura-tion
would be determined by the need for more (or fewer) inverted
outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate
for varying trace delays independent of inver-sion on 4Q.
The other three pairs of outputs are programmed to yield different
skewsrelativetothefeedback. Byadvancingtheclocksignalonthe
longertracesorretardingtheclocksignalonshortertraces,allloads
can receive the clock pulse at the same time.
In this illustration the FB input is connected to an output with 0ns
skew(xF1,xF0=MID)selected.TheinternalPLLsynchronizesthe
FB and REF inputs and aligns their rising edges to insure that all
outputs have precise phase alignment.
REF
Clock skews can be advanced by ±6 time units (t ) when using an
U
output selected for zero skew as the feedback. A wider range of
delaysispossibleiftheoutputconnectedtoFBisalsoskewed.Since
FB
20 MHz
REF
ZeroSkew,+t ,andt aredefinedrelativetooutputgroups,and
U
U
sincethePLLalignstherisingedgesofREFandFB, itispossibleto
createwideroutputskewsbyproperselectionofthexFninputs. For
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
40 MHz
20 MHz
examplea+10t betweenREFand3Qxcanbeachievedbyconnect-
U
ing 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 =
High.(SinceFBalignsat4t and3Qxskewsto+6t ,atotalof+10
U
U
t skew is realized). Many other configurations can be realized by
U
80 MHz
skewing both the output used as the FB input and skewing the other
outputs.
REF
Figure5.FrequencyMultiplierwithSkewConnections
FB
REF
FS
Figure5illustratestheSuperClockconfiguredasaclockmultiplier.
The 3Q0 output is programmed to divide by four and is fed back to
FB. This causes the PLL to increase its frequency until the 3Q0 and
3Q1outputsarelockedat20MHzwhilethe1Qxand2Qxoutputsrun
at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by
two,whichresultsina40MHzwaveformattheseoutputs.Notethat
the 20 and 40 MHz clocks fall simultaneously and are out of phase
on their rising edge. This will allow the designer to use the rising
edges of the ½ frequency and ¼ frequency outputs without concern
forrising-edgeskew.The2Q0,2Q1,1Q0,and1Q1outputsrunat80
MHz and are skewed by programming their select inputs accord-
ingly.NotethattheFSpiniswiredfor80MHzoperationbecausethat
is the frequency of the fastest output.
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Figure4.InvertedOutputConnections
PS8450B
04/09/01
8
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
Figure 7 shows some of the functions that are selectable on the 3Qx
and 4Qx outputs. These include inverted outputs and outputs that
offerdivide-by-2anddivide-by-4timing.Aninvertedoutputallows
the system designer to clock different sub-systems on opposite
edges, without suffering from the pulse asymmetry typical of non-
ideal loading. This function allows the two subsystems to each be
clocked 180 degrees out of phase, but still to be aligned within the
skew spec.
The divided outputs offer a zero-delay divider for portions of the
system that need the clock to be divided by either two or four, and
still remain within a narrow skew of the 1X clock. Without this
feature, an external divider would need to be add-ed, and the
propagation delay of the divider would add to the skew between the
different clock signals.
These divided outputs, coupled with the Phase Locked Loop, allow
the SuperClock to multiply the clock rate at the REF input by either
two or four. This mode will enable the designer to distribute a low-
frequency clock between various portions of the system, and then
locallymultiplytheclockratetoamoresuitablefrequency,whilestill
maintaining the low-skew characteristics of the clock driver. The
SuperClock can perform all of the functions described above at the
sametime.Itcanmultiplybytwoandfourordividebytwo(andfour)
at the same time that it is shifting its outputs over a wide range or
maintaining zero skew between selected outputs.
REF
FB
20 MHz
REF
FS
10 MHz
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
5 MHz
20 MHz
Figure6.FrequencyDividerConnections
Figure6demonstratestheSuperClock inaclockdividerapplication.
2Q0isfedbacktotheFBinputandprogrammedforzeroskew. 3Qx
isprogrammedtodividebyfour.4Qxisprogrammedtodividebytwo.
Note that the falling edges of the 4Qx and 3Qx outputs are aligned.
This allows use of the rising edges of the ½ frequency and ¼
frequencywithoutconcernforskewmismatch.The1Qxoutputsare
programmed to zero skew and are aligned with the 2Qx outputs. In
thisexample, theFSinputisgroundedtoconfigurethedeviceinthe
15 to 30 MHz range since the highest frequency output is running
at20MHz.
REF
FB
LOAD
27.5 MHz
REF
Distribution
Z0
Clock
FS
80 MHz
Inverted
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
Z0
27.5 MHz
LOAD
80 MHz
Zero Skew
Z0
80 MHz Skewed
LOAD
–3.125ns (–4t )
Z0
U
Figure7.Multi-FunctionClockDriver
PS8450B
04/09/01
9
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
REF
LOAD
FB
System
Clock
Z0
REF
FS
L1
L2
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
Z0
L3
LOAD
Z0
L4
FB
Z0
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
Figure8.Board-to-BoardClockDistribution
Figure8showsthePI6C3991connectedinseriestoconstructazero delay clock tree. Cascaded clock buffers will accumulate low-fre-
skew clock distribution tree between boards. Delays of the down quencyjitterbecauseofthenon-idealfilteringcharacteristicsofthe
streamclockbufferscanbeprogrammedtocompensateforthewire PLLfilter.Itisrecommendedthatnotmorethantwoclockbuffersbe
length (i.e., select negative skew equal to the wire delay) necessary connected in series.
to connect them to the master clock source, approximating a zero-
PS8450B
04/09/01
10
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
Package Diagram - 32-Pin PLCC (J)
OrderingInformation
Accuracy (ps)
Ordering Code
PI6C3991-2J
PI6C3991-5J
PI6C3991J
Package Name
Package Type
Operating Range
Commercial
250
500
750
500
750
J32
J32
J32
J32
J32
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
Commercial
Commercial
PI6C3991-5IJ
PI6C3991-IJ
Industrial
PericomSemiconductorCorporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8450B
04/09/01
11
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