PI6C3Q993-5QEX [PERICOM]
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, GREEN, QSOP-28;
| 型号： | PI6C3Q993-5QEX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, GREEN, QSOP-28 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver
SuperClock®
Features
Description
• PI6C3Q99x family provides following products:
PI6C3Q991:32-pinPLCCversion
PI6C3Q993:28-pinQSOPversion
• Inputs are 5V Tolerant
• 4 pairs of programmable skew outputs
• Low skew: 200ps same pair; 250ps all outputs
• Selectable positive or negative edge synchronization:
ExcellentforDSPapplications
ThePI6C3Q99xfamilyisa3.3VPLL-basedclockdriver intendedfor
high-performance computing and data-communication applica-
tions. A key feature of the programmable skew is the ability of
outputs to lead or lag the REF input signal. The PI6C3Q991 has 8
programmable skew outputs in 4 banks of 2, while the PI6C3Q993
has 6 programmable skew outputs and 2 zero skew outputs. Skew
is controlled by 3-level input signals that may be hard-wired to
appropriateHIGH-MID-LOWlevels.
• Synchronous output enable
WhentheGND/sOEpinisheldLOW,alloutputsaresynchronously
enabled.However,ifGND/sOEisheldHIGH,alloutputsexcept3Q0
• Input frequency: 3.75 MHz to 85 MHz
• Output frequency: 15 MHz to 85MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 3 skew grades:
PI6C3Q99x:tSKEW0<750ps
and3Q1aresynchronouslydisabled.Furthermore,whentheV
CCQ
/PE is held HIGH, all outputs are synchronized with the positive
edge of the REF clock input. When V /PE is held LOW, all
CCQ
outputs are synchronized with the negative edge of REF. Both
devices have LVTTL 12mA balanced drive outputs.
PI6C3Q99x-5:tSKEW0<500ps
PI6C3Q99x-2:tSKEW0<250ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• Externalfeedback,internalloopfilter
• 12mA balanced drive outputs
• LowJitter:<200pspeak-to-peak
• Industrial temperature range
• Packaging(Pb-freeandGreenavailable):
—32-pinPLCC
—28-pinQSOP
PinConfigurations
PI6C3Q991
PI6C3Q993
1
REF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
TEST
2F1
2
V
CCQ
FS
3
4
3
2
1 32 31 30
29
4
3F0
3F1
/PE
2F0
3F1
4F0
4F1
/PE
5
6
7
8
9
2F0
GND/sOE
1F1
5
GND/sOE
1F1
28
27
26
25
24
23
22
21
6
V
CCQ
V
7
1F0
V
CCN
1F0
CCQ
V
8
4Q1
4Q0
GND
3Q1
3Q0
V
CCN
V
CCN
4Q1
4Q0
GND
GND
CCN
9
1Q0
1Q1
GND
GND
2Q0
2Q1
10
11
12
13
1Q0
1Q1
GND
GND
10
11
12
13
14
V
14 15 16 17 18 19 20
CCN
FB
PS8449F
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock®
Logic Block Diagrams
PI6C3Q993
PI6C3Q991
GND/sOE
GND/sOE
Skew
1Q0
Skew
1Q0
1Q1
Select
Select
1Q1
3
3
3
3
1F1:0
2F1:0
3F1:0
1F1:0
2F1:0
3F1:0
4F1:0
V
/PE
V
/PE
CCQ
CCQ
Skew
Skew
2Q0
2Q1
2Q0
2Q1
Select
Select
3
3
3
3
REF
FB
REF
FB
PLL
PLL
Skew
Select
Skew
Select
3Q0
3Q1
3Q0
3Q1
3
3
3
3
3
3
FS
FS
Skew
Select
4Q0
4Q1
4Q0
4Q1
3
3
Table 1. Pin Descriptions
Pin Name
REF
Type
IN
Functional Description
Reference clock input
Feedback input
FB
IN
When TEST is held at MID level or HIGH level, the PLLi is disabled (except for conditions of Note 1). REF
goes to all outputs. Skew selections (see table 3) remain in effect. Set LOW for normal operation.
TEST(1)
IN
IN
IN
Synchronous output enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state -
3Q0 or 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level
and GND/sOE is HIGH, the nF [1:0] pins act as output disable controls for individual banks when nF [1:0] =
LL. Set GND/sOE LOW for normal operation.
GND/sOE(1)
Selectable positive or negative edge control. When LOW/HIGH outputs are synchronized with the
negative/positive edge of the reference clock.
VCCQ/PE
nF [1:0]
FS
IN
IN
3-level inputs for selecting 1 of 9 skew taps or frequency range.
Selects appropriate oscillator circuit based on anticipated frequency range. See Table 2
4 output banks of 2 outputs, with programmable skew. On the PI6C3Q993 4Q[1:0] are fixed zero skew
outputs.
nQ [1:0]
OUT
VCCN
VCCQ
GND
PWR Power supply for output buffers
PWR Power supply for phase locked loop and other internal circuitry
PWR Ground
Note:
1. When TEST = MID and GND/sOE = HIGH, the PLL remains active with nF[1:0] =LL functioning as an output disable control for the
individual output banks. See Table 3 for skew selections.
PS8449F
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock®
ExternalFeedback
ProgrammableSkew
Byprovidingexternalfeedback,thePI6C3Q99Xfamilygivesusers
flexibilitywithregardtoskewadjustment.TheFBsignaliscompared
with the input REF signal at the phase detector in order to drive the
Output skew with respect to the REF input is adjustable to compen-
sate for PCB trace delays, backplane propagation delays or to
accommodaterequirementsforspecialtimingrelationshipsbetween
clocked components. Skew is selectable as a multiple of time units
V . Phase differences causes the V of the PLL to adjust up or
CO CO
downaccordingly.Aninternalloopfiltermoderatestheresponseof
- t which is of the order of a nanosecond (see Table 2). There are
U
the V to the phase detector. The loop filter transfer function has
beenchosentoprovideminimaljitter(orfrequencyvariation)while
still providing accurate responses to input frequency.
9skewconfigurationsavailableforeachoutputpair.Theseconfigu-
rationsarechoosenbythenF[1:0]controlpins.Inordertominimize
the number of control pins, 3-level inputs (HIGH-MID-LOW) are
used,theyareintendedforbutnotrestrictedtohard-wiring.Undriven
3-level inputs default to the MID level. Where programmable skew
isnotarequirement,thecontrolpinscanbeleftopenforthezeroskew
default setting. The skew selection Table (Table 3) shows how to
select specific skew taps by using the nF[1:0] control pins.
CO
Table2. PLLProgrammableSkewRangeandResolutionTable
FS = LOW
FS = MID
FS = HIGH
1/(16xFNOM)
Timing unit calculation (tU)
1/(44xFNOM
)
1/(26xFNOM
)
(2,3)
VCO frequency range (FNOM
)
15 to 35 MHz
25 to 60 MHz
40 to 85 MHz
±9.09ns
±49°
±14%
±9.23ns
±83°
±23%
±9.38ns
±135°
±37%
Skew adjustment range(4)
Max. adjustment
Example 1, FNOM = 15 MHz
Example 2, FNOM = 25 MHz
Example 3, FNOM = 30 MHz
Example 4, FNOM = 40 MHz
Example 5, FNOM = 50 MHz
Example 6, FNOM = 80 MHz
tU = 1.52ns
tU = 0.91ns
tU = 0.76ns
tU = 1.54ns
tU = 1.28ns
tU = 0.96ns
tU = 0.77ns
tU = 1.56ns
tU = 1.25ns
tU = 0.78ns
Notes:
2. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is
lowest.
3. The level on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO
frequency appears at 1Q[1:0], 2Q[1:0], and the higher outputs when they are operated in undivided modes. The
frequency appearing at REF and FB inputs are the same as the VCO when the output is connected to FB undivided.
The frequency of the REF and FB inputs are 1/2 or 1/4 the VCO frequency when the part is configured for frequency
multiplication by using a divided output as the FB input.
4. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then
adjustment range greater. For example if a 4tU skewed output is used, all other outputs will be skewed by
–4tU in addition to whatever skew value is programmed for those outputs. Max adjustment range applies to output pairs
3 and 4 where ±6tU skew adjustment is possible and at the lowest FNOM value.
PS8449F
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock®
Table 3. Skew Selection Table for Output Pairs
nF1:0
LL(6)
LM
Skew (Pair #1, #2)
Skew (Pair #3)
Divide by 2
–6tU
Skew (Pair #4)(5)
Divide by 2
–6tU
–4tU
–3tU
LH
–2tU
–4tU
–4tU
ML
MM
MH
HL
–1tU
–2tU
–2tU
Zero skew
+1tU
Zero skew
+2tU
Zero skew
+2tU
+2tU
+4tU
+4tU
HM
HH
+3tU
+6tU
+6tU
Inverted(7)
+4tU
Divide by 4
Notes:
5. Programmable skew on pair #4 is not applicable for the PI6C3Q993.
6. LL disables outputs if TEST = MID level and GND/sOE = HIGH.
7. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VCCQ /PE = HIGH, GND/sOE disables pair #4 LOW when
VCCQ /PE = LOW
Table 4. Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the de-
vice at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Expo-
sure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
Supply Voltage to Ground ...................................... –0.5Vto7.0V
Input Voltage .......................................................... –0.5Vto7.0V
MaximumPowerDissipationatT =85°C,PLCC ....... 0.80watts
A
QSOP ....... 0.66watts
T
Storage Temperature .................................. –65°Cto150°C
STG
Table 5. Recommended Operating Range
PI6C3Q99X, PI6C3Q99X-2,
PI6C3Q99X-5
PI6C3Q99X/PI6C3Q99X-5
(Industrial)
Symbol
Description
Units
(Commercial)
Min.
Max.
Min.
Max.
VCC
TA
Power Supply Voltage
3.0
3.6
3.0
3.6
V
Ambient Operating
Temperature
–40
85
0
70
°C
PS8449F
11/30/05
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock®
Table 6. DC Characteristics Over Operating Range
Symbol
Parameter
Test Condition
Min.
Max.
Units
Guaranteed Logic HIGH
(REF, FB inputs only)
V
IH
Input HIGH Voltage
2.0
5.5
Guaranteed Logic LOW
(REF, FB inputs only)
V
Input LOW Voltage
Input HIGH Voltage
–0.5
0.8
IL
V
(8)
V
IHH
3-Level Inputs only
3-Level Inputs only
3-Level Inputs only
V
–0.6
CC
(8)
V
IMM
Input MID Voltage
V
/2–0.3
V
/2+0.3
CC
CC
(8)
V
ILL
Input LOW Voltage
0.6
5
V
V
= V or GND,
Input Leakage Current
(REF, FB inputs only)
IN
CC
I
IN
= Max.
CC
HIGH level
MID Level
LOW Level
200
50
V
V
= V or GND,
3-Level Input DC Current
(TEST, FS, nF1:0)
IN
CC
I
3
uA
= Max.
CC
200
I
I
Input Pull-Up Current (V
/PE)
V
CC
V
CC
V
CC
V
CC
= Max, V = GND
100
100
PU
CCQ
IN
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
= Max, V = V
IN CC
PD
V
= Min, I = -12mA
2.2
OH
OH
V
V
Output LOW Voltage
= Min, I = 12mA
0.55
OL
OL
Table7.PowerSupplyCharacteristics
Symbol
Parameter
Test Conditions
Typ.
Max. Units
Quiescent Power Supply
Current
V
Max, TEST = Mid., REF = LOW,
CC =
I
8.0
15
30
mA
CCQ
GND/sOE = LOW, All outputs unloaded
Power Supply Current per
µ
A
I
V
V
= Max V = 3.0V
1.0
55
Δ
CCN
CCD
CC
IN
(9)
Input HIGH
Dynamic Power Supply Current
µ
A/
I
= Max C = 0pF
125
CC
L
(9)
per Output
MHz
(9 )
(10)
I
I
I
Total Power Supply Current
V
CC
V
CC
V
CC
= 3.3V, F
= 3.3V, F
= 3.3V, F
= 20MHz, C =160pF
29
42
76
C
C
C
REF
RE F
REF
L
(9)
(10)
Total Power Supply Current
=33MHz, C =160pF
L
mA
(9)
(10)
Total Power Supply Current
=66MHz, C =160pF
L
Notes:
8. Inputs are wired to VCC , GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If inputs are switched, the
function and timing of the outputs may glitched, and the PLL may require additional time before datasheet specifications are achieved.
9. Guaranteed by characterization but not production tested.
10. For 8 outputs each loaded with CL = 20pF.
PS8449F
11/30/05
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock®
Table8. Capacitance (T = 25°C, f = 1 MHz, V = 0V)
A
IN
QSOP
PLCC
Units
Typ.
Max.
Typ.
Max.
CIN
4
6
5
7
pF
VCC
150Ω
150Ω
Output
20pF
tORISE
tOFALL
≤1ns
≤1ns
3.0V
2.0V
Vth=1.5V
0.8V
2.0V
0.8V
tPWL
tPWH
0V
LVTTL Input Test Waveform
LVTTL Output Waveform
Figure 1. AC Test Loads and Waveforms
PS8449F
11/30/05
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock®
Table9.SwitchingCharacteristicsOverOperatingRange
PI6C3Q991-2
PI6C3Q993-2
PI6C3Q991-5
PI6C3Q993-5
PI6C3Q991
PI6C3Q993
Description
Unit
Symbol
FNOM
tRPWH
tRPWL
tU
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
VCO frequency range
see Table 2
see Table 2
see Table 2
REF pulse width HIGH(21)
REF pulse width LOW(21)
Programmable skew time unit
3.0
3.0
3.0
3.0
3.0
3.0
ns
see Table 3
0.05
see Table 3
0.1
see Table 3
tSKEWPR Zero output matched-pair skew (xQ0, xQ1)(11,12,13)
tSKEW0 Zero output skew (all outputs) CL = 0pF(11,14)
0.20
0.25
0.50
1.2
0.25
0.5
0.7
1.2
0.7
1.0
1.25
0.5
1.2
2.5
3.0
1.5
1.5
0.5
40
0.1
0.3
0.6
1.0
0.7
1.2
0.25
0.75
1.0
1.5
1.2
1.7
1.65
0.7
1.2
3.0
3.5
2.5
2.5
0.5
40
0.1
0.25
0.6
tSKEW1 Output skew (rise-rise, fall-fall, same class outputs)(11,15)
tSKEW2 Output skew (rise-fall, nominal-inverted, divided-divided(11,15)
tSKEW3 Output skew (rise-rise, fall-fall, different class outputs)(11,15)
tSKEW4 Output skew (rise-fall, nominal-divided, divided inverted(11,15)
0.25
0.30
0.5
0.25
0.50
0.90
0.75
0.25
1.2
0.5
0.50
0.5
tDEV
Device-to-device skew(11,12,16)
ns
tPD
REF input to FB propagation delay(11,18)
–0.25
–1.2
0
0
–0.5
–1.2
0
0
–0.7
–1.2
0
0
tODCV Output duty cycle varation from 50%(11)
tPWH
Output HIGH time deviation from 50%(11,19)
Output LOW time deviation from 50%(11,20)
2.0
tPWL
1.5
tORISE Output rise time(11)
tOFALL Output fall time(11)
0.15
0.15
1.0
1.0
1.5
0.15
0.15
1.0
1.0
0.15
0.15
1.5
1.5
1.5
tLOCK
PLL lock time(11,17)
0.5
ms
ps
RMS
25
tJR
Cycle-to-cycle output jitter(11)
Peak-to-peak
200
200
200
Notes:
11. All timing tolerances apply for FNOM ≥ 25MHz. Guaranteed by design and characterization.
12. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay
has been selected when all are loaded with the specified load.
13.
tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
14. tSKEW0 is the skew between outputs when they are selected for 0tU.
15. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH),
and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
16. tDEV is output-to-output skew between any two devices operating under the same conditions (VCC , ambient temperature,
air flow, etc.)
17. tLOCK is time required before synchronization is achieved. This specification is valid only after VCC is stable & within
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is
within specified limits.
18. tPD is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
19. Measured at 2.0V.
20. Measured at 0.8V.
21. Refer to Table10 for more detail.
PS8449F
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock®
Table10.InputTimingRequirements(22)
Symbol
tR, tF
tPWC
DH
Description
Maximum input rise and fall times, 0.8V to 2.0V
Input clock pulse, HIGH or LOW
Input duty cycle
Min.
Max.
Units
ns/V
ns
10
3
10
90
%
Notes:
22. Input timing requirements are guaranteed by design. Where pulse width implied by D is less than t
limit,
H
PWC
t
limit applies.
PWC
t
t
REF
RPWL
t
RPWH
REF
t
PD
t
t
ODCV
ODCV
FB
Q
t
JR
t
SKEWPR
t
SKEWPR
t
SKEW0, 1
t
SKEW0, 1
Other Q
t
t
SKEW2
SKEW2
Inverted Q
t
t
SKEW3,4
t
t
SKEW3,4
SKEW3,4
SKEW2,4
REF Divided by 2
t
SKEW1,3,4
REF Divided by 4
Figure2. ACTimingDiagram
Notes:
VCCQ/PE: The AC timing diagram above applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge
of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals
align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when
all are loaded with 20pF and terminated with 75ohms to VCC/2.
tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0
tDEV
:
The skew between outputs when they are selected for 0t U.
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature,
:
air flow, etc.)
tODCV
:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tLOCK
:
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within
specified limits.
tPWH
tPWL
is measured at 2.0V.
is measured at 0.8V.
tORISE & tOFALL
are measured between 0.8V and 2.0V.
PS8449F
11/30/05
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock®
PackagingMechanical:32-PinPLCC
PackagingMechanical:28-PinQSOP
28
.008
0.20
MIN.
.008
.013
0.150
0.157
3.81
3.99
0.20
0.33
Guage Plane
0˚-6˚
.010
.016
.035
0.41
0.89
0.254
1
Detail A
.041
1.04
REF
.386 9.804
.394 10.009
.015 x 45˚
.033
REF
1.35 .053
1.75 .069
0.84
Detail A
SEATING
PLANE
0.178
0.254
.007
.010
0.41 .016
1.27 .050
0.101
0.254
.004
.010
.228
.244
5.79
6.19
.025
BSC
0.635
.008
.012
0.203
0.305
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
PS8449F
11/30/05
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock®
OrderingInformation
Ordering Code
PI6C3Q991J
Package Code
Package Type
32-Pin PLCC
Operating Range
J
J
PI6C3Q991-2J
PI6C3Q991-5J
PI6C3Q991-IJ
32-Pin PLCC
Commercial
J
32-Pin PLCC
J
32-Pin PLCC
PI6C3Q991-5IJ
PI6C3Q991-5IJE
PI6C3Q993-2Q
PI6C3Q993-5QE
PI6C3Q993-IQ
PI6C3Q993-5IQ
J
32-Pin PLCC
Industrial
J
Pb-free & Green 32-Pin PLCC
28-Pin QSOP
Q
Q
Q
Q
Commercial
Industrial
Pb-free & Green 28-Pin QSOP
28-Pin QSOP
28-Pin QSOP
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free & Green
• X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com
PS8449F
11/30/05
10
相关型号：
PI6C3Q993-5QI
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28
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PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28
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PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28
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