PI6C41201LE [PERICOM]
Low Skew Clock Driver, 6C Series, 1 True Output(s), 1 Inverted Output(s), PDSO8, 0.173 INCH, TSSOP-8;
| 型号： | PI6C41201LE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Low Skew Clock Driver, 6C Series, 1 True Output(s), 1 Inverted Output(s), PDSO8, 0.173 INCH, TSSOP-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C4120X
LVCMOS to LVPECL Driver
Description
Features
PI6C4120xisahighperformanceLVCMOSorLVTTLtoLVPECL
clockbuffer. ThePI6C41204isa4outputversionwith2selectable
inputs, pin compatible with ICS8535-01. PI6C41204A is the en-
hancedversionwithextrapowerandgroundpinstominimizenoise
andjitter.ThePI6C41202issimilartothePI6C41204exceptishastwo
outputs.ThePI6C41201isaconvenientLVTTL/LVCMOStoLVPECL
converter with 1 input and 1 output.
• Up to 4 LVPECL outputs
• SelectableCLK0orCLK1inputs
• LVCMOSorLVTTLinputlevel
• 30ps max output skew
• 150ps max part to part skew
• 1.9ns max propagation delay
• 266MHz output frequency
• TSSOPpackage
PinConfigurationPI6C41204/A
BlockDiagramPI6C41204/A
Vee
CLK_EN
CK_SEL
CLK0
1
2
3
4
5
6
7
8
9
10
20
Q0
D
CLK_EN
Q
19
nQ0
Vcc
Q1
LE
18
0
1
CLK0
CLK1
Q0
17
nQ0
nc/Vee
CLK1
20-Pin 16
nQ1
Q2
Q1
15
14
13
12
11
nQ1
Q2
nc/Vee
nc/Vee
nc/Vcc
Vcc
nQ2
Vcc
Q3
CLK_SEL
nQ2
Q1
nQ3
nQ3
BlockDiagramPI6C41202
PinConfigurationPI6C41202
Vee
CLK_EN
CK_SEL
CLK0
1
2
3
4
5
6
7
14
13
12
11
10
9
Vcc
Q0
D
CLK_EN
Q
LE
nQ0
nc
0
1
CLK0
Q0
14-Pin
nQ0
CLK1
Vee
Q1
Q1
CLK1
nQ1
Vcc
nQ1
Vcc
8
CLK_SEL
BlockDiagramPI6C41201
PinConfigurationPI6C41201
D
Vee
CLK_EN
CLK0
1
2
3
4
8
7
6
5
Vcc
Q0
CLK_EN
CLK0
Q
LE
8-Pin
nQ0
Vcc
Q0
Vee
nQ0
PS8626 08/16/02
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PI6C4120x
LVCMOS to LVPECLDriver
Table1a. PinDescriptionforPI6C41204
Number
Name
Type
Description
1
Vee
Power
Input
Ground.
Synchronizing clock enable. When HIGH, clock outputs follow
clock input. When LOW, Q are low, nQ are high. LVCMOS or
LVTTL input level.
2
3
CLK_EN
Pullup
Clock select input: LOW = CLK0, HIGH = CLK1 LVCMOS
or LVTTL input level.
CLK_SEL
Input
Pulldown
4
CLK0
CLK1
Input
Input
Pulldown LVCMOS or LVTTL clock input.
Pulldown LVCMOS or LVTTL input level.
No Connect
6
5, 7, 8, 9
10, 13, 18
11, 12
14, 15
16, 17
19, 20
NC
Unused
Power
Output
Output
Output
Output
Vcc
3.3V supply
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
LVPECL output pair.
LVPECL output pair.
LVPECL output pair.
LVPECL output pair.
Table1b. PinDescriptionforPI6C41204A
Number
Name
Type
Description
1, 5, 7, 8
Vee
Power
Input
Ground.
Synchronizing clock enable. When HIGH, clock outputs follow
clock input. When LOW, Q are low, nQ are high. LVCMOS or
LVTTL input level.
2
3
CLK_EN
Pullup
Clock select input: LOW = CLK0, HIGH = CLK1 LVCMOS
or LVTTL input level
CLK_SEL
Input
Pulldown
4
6
CLK0
CLK1
Input
Input
Pulldown LVCMOS or LVTTL clock input.
Pulldown LVCMOS or LVTTL input level.
9, 10, 13,
18
Vcc
Power
3.3V supply
11, 12
14, 15
16, 17
19, 20
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Output
Output
Output
Output
LVPECL output pair.
LVPECL output pair.
LVPECL output pair.
LVPECL output pair.
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PI6C4120x
LVCMOS to LVPECLDriver
Table 1c. Pin Description for PI6C41202
Number
Name
Type
Description
1, 5
Vee
Power
Input
Ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q are low, nQ are high. LVCMOS or LVTTL
input level.
2
3
CLK_EN
Pullup
Clock select input: LOW = CLK0, HIGH = CLK1 LVCMOS or
LVTTL input level.
CLK_SEL
Input
Pulldown
4
CLK0
CLK1
Input
Input
Pulldown
Pulldown
LVCMOS or LVTTL clock input.
LVCMOS or LVTTL input level.
3.3V supply
6
7, 8, 14
9, 10
12, 13
Vcc
Power
Output
Output
nQ1, Q1
nQ0, Q0
LVPECL output pair.
LVPECL output pair.
Table 1d. Pin Description for PI6C41201
Number
Name
Type
Description
1, 4
Vee
Power
Input
Ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q are low, nQ are high. LVCMOS or LVTTL
input level.
2
CLK_EN
Pullup
3
CLK0
Vcc
Input
Power
Output
Pulldown
LVCMOS or LVTTL clock input.
3.3V supply
5, 8
6, 7
nQ0, Q0
LVPECL output pair.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
CLK0,
CLK1
TBD
C
Input Capacitance
pF
IN
CLK_EN
CLK_SEL
TBD
80
R
Input Pullup Resistor
PULLUP
K ohm
Input Pulldown
Resistor
R
80
PULLDOWN
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PI6C4120x
LVCMOS to LVPECLDriver
3a.ControlInputFunctionTable
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK0
Q0 thru Q3
Disabled ; LOW
Disabled ; LOW
Enabled
nQ0 thru nQ3
0
0
1
1
0
1
0
Disabled ; HIGH
Disabled ; HIGH
Enabled
CLK1
CLK0
CLK1
Enabled
Enabled
1
After CLK_EN switches, the clock outputs are disabled or enabled following
a rising and falling input clock edge as shown in figure1. In the active mode, the state
of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3b.
Disabled
Enabled
CLK0, CLK1
CLK_EN
nQ0 - nQ3
Q0 - Q3
Figure1. CLK_ENTimingDiagram
Table3b.ClockInputFunctionTable
Inputs
Outputs
CLK0 or CLK1
Q0 thru Q3
LOW
nQ0 thru nQ3
HIGH
0
1
HIGH
LOW
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PI6C4120x
LVCMOS to LVPECLDriver
MaximumRatings
(Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
abovethoseindicatedintheoperationalsectionsofthis
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
Storage Temperature ...................................................................–65°Cto+150°C
Ambient Temperature with Power Applied .................................... –0°Cto+70°C
SupplyVoltage,V
.................................................................................................. +4.6V
CC
Input/Output Voltage ........................................................... –0.5VtoV +0.5V
CC
Table4a.OperatingConditions
Symbol
VCC
IEE
Parameter
Min.
Typ.
Max.
3.465
50
Units
V
Supply Voltage
3.135
3.3
Supply Current
mA
°C
TA
Ambient Temperature
0
70
Table 4b. LVCMOS/LVTTL DC Characteristics, (V = 3.3V ± 5%, T = 0°C to +70°C)
CC
A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
CLK0,CLK1
2
3.765
VIH
Input High Voltage
CLK_EN
2
3.765
1.3
CLK_SEL
V
CLK0, CLK1
— 0.3
— 0.3
VIL
IIH
IIL
Input Low Voltage
Input High Current
Input Low Current
CLK_EN
CLK_SEL
0.8
CLK0,CLK1
CLK_SEL
V
IN = VCC = 3.465V
150
5
CLK_EN
VIN = VCC = 3.465V
µA
CLK0, CLK1
CLK_SEL
VIN =0V, VCC = 3.465V
— 5
CLK_EN
VIN =0V, VCC = 3.465V
— 150
Table 4c. LVPECL DC Characteristics (V
= 3.3V ± 5%, T = 0°C to +70°C)
A
CC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
V
-
CC
1.4
V
Output High Voltage;
Output Low Voltage;
Note 1
Note 1
V
V
- 1.0
OH
CC
V
CC
-
V
- 1.7
V
OL
CC
2.0
Peak-to-Peak Output
Voltage Swing
V
SWING
0.6
0.85
Note:
1. Outputs terminated with 50ohm to V - 2V
CC
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PI6C4120x
LVCMOS to LVPECLDriver
Table 5. AC Characteristics, (V
= 3.3V ± 5%, T = 0°C to +70°C (Note 3)
A
CC
Symbol
Parameter
Test Conditions
Min.
Typ. Max.
Units
fMAX
Maximum Input Frequency
266
1.9
1.9
MHz
tPLH
tPHL
Propagation Delay Low to
High : Note 4
VCC to VOX
VCC to VOX
1.0
1.0
ns
ps
Propagation Delay High to
Low : Note 4
ts(o)
tsk(pp )
tDC
Output Skew : Note 5
11
50
30
Part to Part Skew : Note 6
150
Output Duty Cycle
48
52
%
Output Rise / Fall time
20% to 80%
tr/tf
100
400
ps
Notes:
3. All parameters measured at 266MHz unless noted otherwise. The part does not add jitter.
4. Measured from the V /2 point of the input to the differential output crossing point.
DD
5. Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output crossing points differential.
6. Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Measured at the output crossing points differential.
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PI6C4120x
LVCMOS to LVPECLDriver
V
CC
SCOPE
Z = 50Ohm
Z = 50Ohm
Qx
LVPECL
50Ohm
V
CC
= 2V
nQx
50Ohm
V
= -1.3V ± 0.165V
EE
Figure2.2-3.3VOutputLoadTestCircuit
Qx
Part 1
Qx
nQx
Qy
nQx
Qy
Part 2
nQy
nQy
tsk(0)
tsk(0)
Figure4. Part-to-PartSkew
Figure3. OutputSkew
80%
80%
CLK0, CLK1
VSWING
20%
Q0, Q3
20%
Clock Inputs
and Outputs
nQ0, nQ3
tF
tR
tPD
Figure 6. PropagationDelay
Figure 5. InputandOutputRiseandFallTime
nQ0, nQ3
Q0, Q3
Pulse Width
tPERIOD
odc =
tPW
tPERIOD
Figure 7. odc & tPERIOD
PS8626 08/16/02
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PI6C4120x
LVCMOS to LVPECLDriver
8-Pin TSSOP (L) Package Mechanical
14-Pin TSSOP (L) Package Mechanical
14
0.09
0.20
0.004
0.008
0.169
0.177
4.3
4.5
0.45 0.018
0.75 0.030
0.240
0.264
1
0.193
0.201
6.1
6.7
4.90
5.10
0.047
1.20
max.
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
SEATING
PLANE
0.002 0.05
0.006 0.15
0.007
0.0256
typical
0.012
0.19
0.30
0.65
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PI6C4120x
LVCMOS to LVPECLDriver
20-Pin TSSOP (L) Package Mechanical
20
.169
.177
4.3
4.5
1
.252
0.09
0.20
.004
.008
.260
6.4
6.6
.047
1.20
Max
0.45 .018
0.75 .030
SEATING
PLANE
.238
.269
6.1
6.7
.002
.006
0.05
0.15
.007
.012
0.19
0.30
.0256
BSC
0.65
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
Ordering Information
P/N
Description
PI6C41201L
PI6C41202L
PI6C41204L
PI6C41204AL
8-pin 173-mil TSSOP Package
14-pin 173-mil TSSOP Package
20-pin 173-mil TSSOP Package
20-pin 173-mil TSSOP Package
Commercial
Commercial
Commercial
Commercial
PericomSemiconductorCorporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8626 08/16/02
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