PI6CFGL202BLIE [PERICOM]
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs;
| 型号： | PI6CFGL202BLIE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs PC |
| 文件： | 总8页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Features
Description
ꢀÎPCIe® 3.0, 2.0 and 1.0 compliant
ꢀÎLVDS compatible outputs
ꢀÎSupply voltage of 3.3V 10%
e PI6CFGL202B is a spread spectrum clock generator compli-
ant to PCI Express® 3.0 and Ethernet requirements. e device is
used for PC or embedded systems to substantially reduce Electro-
magnetic Interference (EMI).
ꢀÎ25MHz crystal or clock input frequency
ꢀÎLow power consumption with independent output power
e PI6CFGL202B provides two differential (HCSL) or LVDS
spread spectrum outputs. e PI6CFGL202B is configured to se-
lect spread and clock selection. Using Pericom's patented Phase-
Locked Loop (PLL) techniques, the device takes a 25MHz crystal
input and produces two pairs of differential outputs (HCSL) at
25MHz, 100MHz, 125MHz and 200MHz clock frequencies. It
also provides spread selection of -0.5%, -0.75%, and no spread.
supply 1.05V to 3.3V
ꢀÎJitter 35ps cycle-to-cycle (typ)
ꢀÎSpread of -0.5%, -0.75%, and no spread
ꢀÎIndustrial temperature range
ꢀÎSpread Bypass option available
ꢀÎSpread and frequency selection via external pins
ꢀÎPackaging: (Pb-free and Green)
à
16-pin TSSOP (L16)
Block Diagram
Pin Configuration (16-Pin TSSOP)
VDD
2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
S0
S1
VDDA3.3
CLK0
SS1:SS0
2
CLK0
CLK0
Control
Logic
SS0
CLK0#
S1:S0
2
Phase
Lock
Loop
XTAL_IN
XTAL_OUT
OE
GNDA
VDDO
CLK1
CLK1
XTAL_IN or Ref CLK
CLK1
25 MHz
crystal or clock
Crystal
Driver
GNDX
SS1
CLK1#
XTAL_OUT
VDDDIG3.3
2
Pulling
Capacitors
GND
OE
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03/03/15
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1
PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Pin Description
Pin # Pin Name
Type
Description
1
S0
Input
Input
Input
Input
Select pin 0 (Internal pull-up resistor). See Table 1.
Select pin 1 (Internal pull-up resistor). See Table 1.
Spread Select pin 0 (Internal pull-up resistor). See Table 2.
Crystal or clock input. Connect to a 25MHz crystal or single ended clock.
Crystal connection. Leave unconnected for clock input.
Output enable. Internal pull-up resistor.
2
S1
3
SS0
4
XTAL_IN
5
XTAL_OUT Output
6
OE
Input
Power
Input
7
GNDX
SS1
Crystal ground pin.
8
Spread Select pin 1 (Internal pull-up resistor). See Table 2.
3.3V digital power.
9
VDDDIG3.3 Power
10
11
12
13
14
15
16
CLK1#
CLK1
Output
Output
Power
HCSL compliment clock output, LOW when output is disabled.
HCSL clock output, LOW when output is disabled.
Power supply, nominal 1.8V, range1.05V~3.3V.
Output and analog circuit ground.
VDDO
GNDA
CLK0#
CLK0
Power
Output
Output
Power
HCSL compliment clock output, LOW when output is disabled.
HCSL clock output, LOW when output is disabled.
3.3V power supply for PLL core.
VDDA3.3
Table 1: Frequency Select Table
Table 2: Spread Selection Table
S1
S0
CLK(MHz)
SS1
SS0
Spread
0
0
1
1
0
1
0
1
25
0
0
1
1
0
1
0
1
No Spread
Down -0.5
Down -0.75
No Spread
100
125
200
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03/03/15
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2
PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Test Loads
Low-Power HCSL Differenti
al Output Test Load
5 inches
Rs
Zo=100Ω
Rs
2pF
2pF
Device
Driving LVDS
3.3V
Driving LVDS
R7a
R7b
Cc
Cc
Rs
Rs
Zo
R8b
R8a
LVDS Clock
input
Device
Driving LVDS inputs with the PI6CFGL202B
Value
Component
Receiver has termination
Receiver does not have termination
R7a, R7b
R8a, R8b
Cc
10K Ω
5.6K Ω
0.1 uF
140 Ω
75 Ω
0.1 uF
1.2 volts
Vcm
1.2 volts
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PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Note: Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. is is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Supply Voltage to Ground Potential......................................................4.6V
All Inputs and Output.....................................................-0.5V toVDD+0.5V
Ambient Operating Temperature........................................... -40 to +85°C
Storage Temperature.......................................................... –65°C to +150°C
Junction Temperature .......................................................................... 125°C
Soldering Temperature.........................................................................260°C
ESD Protection (Input) ...........................................................2000V(HBM)
Electrical Characteristics–Current Consumption
(TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)
Symbol Parameters
Condition
Min. Typ. Max. Units
Total power consumption, All outputs active
@100MHz
IDDOP
Operating supply current1
52
mA
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions (TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)
Symbol
Parameters
Supply Voltage1
Supply Voltage1
Condition
Min. Typ.
Max. Units
VDDX
VDDO
Supply voltage for core, analog
Supply voltage outputs
3.0
3.3
1.8
3.6
2.0
V
V
1.65
0.65
VDD
VDD
0.3
+
VIH
VIL
IIN
Input High Voltage1
OE, S0, S1, SS0, SS1
OE, S0, S1, SS0, SS1
V
0.35
VDD
Input Low Voltage1
-0.3
-5
V
Single-ended inputs, VIN = GND, VIN = VDD (ex-
clude XTAL pin)
5
uA
Input Current1
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
XTAL or X1 input
-200
23
200
uA
Fin
Input Frequency1
Pin Inductance1
25
26
7
MHz
nH
pF
Lpin
CIN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
1.5
1.5
5
CINDIF_IN
COUT
Capacitance1,4
2.7
6
pF
pF
From VDD Power-Up and aꢀer input clock
stabilization
TSTAB
Clk Stabilization1,2
0.6
1
ms
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03/03/15
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4
PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Symbol
Parameters
Condition
Min. Typ.
Max. Units
Input SS Modulation
Frequency1
Output Enable Time1
Output Disable Time1
Allowable Frequency
(Triangular Modulation)
All output
fMODIN
30
31.500 33
kHz
TOE
tOT
10
10
μs
μs
All output
From Power-up to
VDD=3.3V1
tSTABLE
tSPREAD
From Power-up VDD=3.3V
3.0
3.0
ms
ms
Setting period aꢀer
spread change1
Setting period aꢀer spread change
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Control input must be monotonic from 20% to 80% of input swing. Input Frequency Capacitance
3. Time from deassertion until outputs are >200 mV
4. DIF_IN input
Electrical Characteristics–CLK 0.7V Low Power HCSL Outputs (TA = -40~85oC; VDD = 3.3V+/-
10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)
Symbol
Parameters
Slew rate1,2,3
Voltage High1
Condition
Min. Typ. Max. Units
Trf
1.1
2
4.5
V/ns
mV
VHIGH
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope averag-
ing on)
660
950
VLOW
Voltage Low1
-150
150
mV
Vmax
Vmin
Max Voltage1
Min Voltage1
Vswing1,2
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
1150
mV
mV
mV
mV
mV
%
-300
300
250
Vswing
Vcross_abs Crossing Voltage (abs)1,5
Scope averaging off
550
140
55
Δ-Vcross
tDC
Crossing Voltage (var)1,6
Duty Cycle1
Scope averaging off
Measured differentially, PLL Mode
45
tskew
Skew, Output to Output1 VT = 50%
Jitter, Cycle to cycle1,2
PLL mode @100MHz output, SSC off
50
ps
tjcyc-cyc
50
ps
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Measured from differential waveform
3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.
4. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point
where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calcula-
tions.
5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and
Clock# falling).
6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is
to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
All trademarks are property of their respective owners.
www.pericom.com
03/03/15
15-0025
5
PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Electrical Characteristics–Phase Jitter Parameters
(TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)
Symbol
Parameters Condition
Min. Typ. Industry Limit
Units
ps
tjphPCIeG1
PCIe Gen 11,2,3,5
25
86
3
(p-p)
ps
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz1,2,5
0.9
1.6
0.36
(rms)
ps
Phase Jitter,
PCI Express
tjphPCIeG2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)1,2,5
3.1
1
(rms)
ps
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)1,2,4,5
tjphPCIeG3
(rms)
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs.
3. Sample size of at least 100k cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4. Calculated from Intel-supplied Clock Jitter Tool.
5. Applies to all different outputs.
Thermal Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
ermal Resistance Junction to Ambient
ermal Resistance Junction to Case
Still air
90
24
°C/W
°C/W
θJA
θJC
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www.pericom.com
03/03/15
15-0025
6
PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Application Notes
Crystal circuit connection
e following diagram shows crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1=
27pF, C2= 27pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts.
Crystal Oscillator Circuit
XTAL_IN
C1
27pF
SaRonix-eCera
FL2500047
Crystal�(CL�=�18pF)
XTAL_OUT
C2
27pF
ASIC
CL= crystal spec. loading cap.
Cj = chip in/output cap. (3~5pF)
Cb = PCB trace/via cap. (2~4pF)
C1,2 = load cap. components
Rd = drive level res. (100Ω)
X1
X2
Cj
Cj
Cb
Rf Pseudo
sine
Rd
Cb
C1
C2
Final choose/trim C1=C2=2 *CL - (Cb +Cj) for the target +/-ppm
Example: C1=C2=2*(18pF) – (4pF+5pF)=27pF
Recommended Crystal Specification
a) FL2500047, SMD 3.2X2.5(4P), 25MHz, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf
b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
All trademarks are property of their respective owners.
www.pericom.com
03/03/15
15-0025
7
PI6CFGL202B
Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
Packaging Mechanical: 16-Pin TSSOP (L)
DATE: 05/03/12
REVISION: F
Notes:
1. Refer JEDEC MO-153F/AB
2. Controlling dimensions in millimeters
3. Package outline exclusive of mold flash and metal burr
DESCRIPTION: 16-Pin, 173mil Wide TSSOP
PACKAGE CODE: L
DOCUMENT CONTROL #: PD-1310
12-0372
Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
Package Code Description
PI6CFGL202BLIE
L
16-pin, 173mil Wide (TSSOP)
Notes:
• ermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging
Pericom Semiconductor Corporation • 1-800-435-2336
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03/03/15
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