PI6CU877 [PERICOM]
PLL Clock Driver for 1.8V DDR2 Memory; PLL时钟驱动器的1.8V DDR2内存
| 型号： | PI6CU877 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PLL Clock Driver for 1.8V DDR2 Memory |
| 文件： | 总11页 (文件大小：508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
Features
Description
• PLL clock distribution optimized for DDR2 SDRAM
applications.
PI6CU877 PLL clock driver is developed for Registered DDR2
DIMM applications with 1.8Voperation and differential data input
and output levels.
• Distributes one differential clock input pair to ten differential
clock output pairs.
The device is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to eleven differential pairs of clock
outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT,
FBOUT).
• Differential Inputs (CLK, CLK) and (FBIN, FBIN)
• Input OE/OS: LVCMOS
• Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT)
TheclockoutputsarecontrolledbyCLK/CLK,FBOUT,FBOUT,the
• External feedback pins (FBIN, FBIN) are used to
synchronize the outputs to the clock input.
LVCMOS (OE, OS) and the Analog Power input (AV ). When
OEisLOWtheoutputsexcept FBOUT,FBOUT,aredisabledwhile
the internal PLL continues to maintain its locked-in frequency.
DD
• Operates at AV = 1.8V for core circuit and internal PLL,
DD
OS is a program pin that must be tied to GND or V
When OS
DD.
and V
= 1.8V for differential output drivers
DDQ
is high, OE will function as described above. When OS is LOW,
• Packaging (Pb-free & Green available):
– 52-ball VFBGA (NF)
OE has no effect on Y7/Y7, they are free running. When AV is
DD
grounded, the PLL is turned off and bypassed for test purposes.
When CLK/CLK are logic low, the device will enter a low power
mode.Aninputlogicdetectioncircuitwilldetectthelogiclowlevel
and perform a low power state where all Y[0:9], Y[0:9]; FBOUT,
FBOUT, and PLL are OFF.
Pin Configuration
PI6CU877 is a high performance, low skew, and low jitter PLL
clock driver, and it is also able to track Spread Spectrum Clocking
(SSC) for reduced EMI.
1
2
3
4
5
6
Y1
Y0
Y0
Y5
Y5
Y6
A
B
C
D
E
F
Y1
Y2
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
Y4
GND
NB
GND
NB
GND
GND
OS
Y6
Y7
Y2
VDDQ
NB
VDDQ
NB
Y7
CK
VDDQ
OE
FBIN
FBIN
FBOUT
FBOUT
Y8
CK
NB
NB
AGND
AVDD
Y3
VDDQ
NB
VDDQ
NB
VDDQ
GND
GND
Y9
G
H
J
GND
Y4
GND
Y9
Y3
Y8
k
PS8689B
08/05/04
1
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
Block Diagram
Y0
Y0
Y
1
LD* or OE
OE
OS
Y
1
Powerdown
Control &
Test Logic
LD*
LD*, OS or OE
Y2
Y2
PLL bypass
AV
DD
Y
3
Y
3
Y4
Y4
Y5
Y5
Y
6
CK
CK
Y
Y
6
10K - 100kΩ
7
PLL
Y
7
FBIN
FBIN
Y8
Y8
Y
9
Y
9
* The Logic Detect (LD) powers down the device
when a logic low is applied to both CK and CK.
FB
FB
OUT
OUT
PS8689B
08/05/04
2
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
Pinout Table
Pin Name
AGND
Characteristics
Ground
Desctription
Analog ground
Analog power
AV
1.8V nominal
DD
CK
CK
Differential Input
Differential Input
Differential Input
Differential Input
Differenital Output
Differential Output
LVCMOS input
LVCMOS input
Ground
Clock input with a (10K - 100KΩ) pulldown resistor
Complementary clock input with a (10K - 100KΩ) pulldown resistor
Complementary feedback clock input
Feedback clock input
FB
FB
FB
FB
IN
IN
Complementary Feedback clock output
Feedback clock output
OUT
OUT
OE
Output enable (async.)
OS
Output select (tied to GND or V
)
DDQ
GND
Ground
V
1.8V nominal
Logic and output power
Clock outputs
DDQ
Y[0:9]
Y[0:9]
NB
Differential Outputs
Differential Outputs
Complementary clock outputs
No Ball (VFBGA only)
Function Table
Inputs
Outputs
FBOUT
PLL State
AV
OE
H
OS
X
CK
L
CK
H
Y
L
Y
H
FBOUT
DD
GND
GND
GND
L
H
L
H
L
Bypass/Off
Bypass/Off
Bypass/Off
H
X
H
L
H
L
(1)
(1)
L
H
L
H
L(Z)
L(Z)
H
(1)
(1)
L(Z)
,
L(Z) ,
GND
L
L
L
L
H
L
H
L
L
H
L
H
L
L
H
L
Bypass/Off
Y7 active Y7 active
(1)
(1)
1.8V (nom)
1.8V (nom)
L(Z)
L(Z)
On
On
(1)
(1)
L(Z)
,
L(Z) ,
H
H
Y7 active Y7 active
1.8V (nom)
1.8V (nom)
1.8V (nom)
1.8V (nom)
H
H
X
X
X
X
X
X
L
H
L
H
L
L
H
L
H
H
L
L
H
H
L
On
On
Off
(1)
(1)
(1)
(1)
L(Z)
L(Z)
L(Z)
L(Z)
H
Reserved
Notes:
1.
L(Z) means the outputs are disabled to a low state meeting the IODL limit on DC Specification
PS8689B
08/05/04
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PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
Parameter
Min.
Max.
Units
V
, A
DDQ VDD
I/O supply voltage range and analog /core supply voltage range
-0.5
2.5
V
+0.5
DDQ
V
Input voltage range
-0.5
V
I
V
Output voltage range
Input clamp current
-0.5
-50
O
I
50
50
IK
I
Output clamp current
Continuous output current
-50
OK
mA
ºC
I
-50
50
O
I
Continuous current through each V
or GND
DDQ
-100
-65
100
150
O(PWR)
T
Storage temperature
STG
Note:
1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DC Specifications Recommended Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
V
Output supply Voltage
1.7
1.8
1.9
DDQ
(4)
AV
Supply voltage
V
DDQ
DD
0.35 x
(5)
V
V
Low-level input voltage
OE, OS, CK, CK
OE, OS, CK, CK
IL
V
DDQ
0.65 x
(5)
V
High-level input voltage
IH
V
DDQ
I
High-level output current, see Fig 2
Low-level output current, see Fig. 2
-
-9
9
OH
I
-
OL
mA
(V
/2)
(V
/2)
DDQ
DDQ
V
V
Input differential-pair crossing voltage
Input voltage level
IX
IN
-0.15
-0.3
0.3
0.6
0
-0.15
V
V
V
+0.3
DDQ
DDQ
DDQ
DC
AC
+0.4
+0.4
V
(5)
V
Input differenital voltage, See Fig 9
ID
T
Operating free air temperature
70
ºC
A
Notes:
4. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended
operating conditions and no timing parameters are guaranteed.
5. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK,
VIH and VIL limits are used to define the DC low and high levels for the logic detect state.
PS8689B
08/05/04
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PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
Timing Requirements (Over recommended operating free-air temperature)
AV , V
= 1.8V ±0.1V
DD
DDQ
Symbol
Decription
Units
Min.
25
Max.
300
270
60
(7, 8)
Operation clock frequency
FCK
MHz
(7, 9)
Application clock frequency
Input clock duty cycle
160
40
t
%
µs
ns
DC
(10)
t
Stabalization time
15
L
(10)
t
Device power down
8
OFF
Notes:
7. The PLL is able to handle spread spectrum induced skew.
8. Operating clock frequency indicates a range over which the PLL is able to lock, but in which it is not required to meet the other
timing parameters. (Used for low-speed debug).
9. Application clock frequency indicates a range over which the PLL must meet all timing parameters.
10. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference
signal after power up . During normal operation, the stabilization time is also the time required for the integrated PLL circuit to
obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down
mode and later return to active operation. CK and CK maybe left floating after they have been driven low for one complete clock cycle.
DC Specifications
Param-
eter
AV
,
DD
Description
Test Condition
Min.
Typ.
Max.
Units
V
DDQ
V
All Inputs
I = -18mA
I
1.7V
1.2
IK
1.7 to
1.9V
V
DDQ
-0.2
V
HIGH output voltage
I
I
= -100µA
= -9mA
V
OH
OH
1.7
1.1
OH
I
Output disabled low current
OE = L, V
= 100mV
100
µA
V
ODL
ODL
Output differenital voltage, the magniture of the difference
between the true and complimentary outputs, see fig. 9 for
dimentions
1.7V
V
0.6
OD
CK, CK
OE, OS, FB , FB
V = V
or GND
or GND
±250
±10
500
I
DDQ
I
I
V = V
µA
IN
IN
I
DDQ
I
Static Supple current, I
+ I
CK and CK = L
DDLD
DDQ
ADD
1.9V
1.8V
Dynamic supply current, I
+
CK and CK = 270MHz,
all outputs are open (not
connected to a PCB)
DDQ
I
I
, see note 6 for CPD calcula-
300
mA
DD
CI
ADD
tion
CK, CK
V = V
or GND
or GND
or GND
or GND
2
2
3
I
DDQ
DDQ
DDQ
DDQ
FB , FB
V = V
I
3
IN
IN
IN
pF
CK, CK
V = V
I
0.25
0.25
CI(∆)
FB , FB
V = V
I
IN
Notes:
6. Total IDD = IDDQ + IADD = FCK *CPD *VDDQ, solving for CPD = (IDDQ + IADD)/(FCK*VDDQ) where FCK is the input frequency, VDDQ is the
power supply and CPD is the Power Dissipation Capacitance.
PS8689B
08/05/04
5
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
AC Specifications
(15)
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)
AV , V
= 1.8V ±0.1V
DD
DDQ
Parameter
Description
Diagram
Units
Min.
Nom.
Max.
8
ten
OE to and Y/Y
OE to and Y/Y
see Fig 11
see Fig 11
ns
tdis
8
tjit(cc+)
tjit(cc-)
t(Ø)
0
40
-40
50
50
40
40
75
4
Cycle-to-cycle jitter
see Fig 4
0
(11)
Static phase offset
Dynamic phase offset
Output clock skew
see Fig 5
see Fig 10
see Fig 6
see Fig 7
see Fig 8
see Fig 9
see Fig 9
see Fig 1, 9
-50
-50
t(Ø)dyn
tsk(o)
ps
(12)
tjit(per)
tjit(hper)
Period jitter
-40
-75
1
(12)
Halk period jitter
Input clock slew rate
Output enable (OE)
Output clock slew rate
2.5
2.5
slr(i)
0.5
1.5
V/ns
V
(14, 16)
slr(o)
3
(V
/2)
(V
/2)
DDQ
DDQ
-0.1
(13)
V
Outpu differenital-pair cross voltage
see Fig 2
OX
+0.1
The PLL on the PI6CU877 is capable of meeting all the above test parameters while supporting SSC synthesirers
with the following parameters:
SSC modulation frequency
30.00
0.00
33
kHz
%
SSC clock input frequency deviation
-0.50
PI6CU877 PLL design should target the values below to minimize the SCC induced skew:
PLL Loop Bandwidth 2.0
MHz
Notes:
11. Static Phase Offset does not include Jitter
12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
13. VOX specified at the DRAM clock input or the test load.
14. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these
Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered
DDR2 DIMM application.
15. There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differen-
tial-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables should be used.
16. The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended.
PS8689B
08/05/04
6
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
VDD
VCK
PI6CU877
R = 60Ω
R = 60Ω
VDD/2
VCK
GND
Figure 1. IBIS Model Output Load
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Figure 2. Output Load Test Circuit 1
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/2
DD
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–V /2
DD
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R = 10Ω
R = 10Ω
Z= 50Ω
Z= 50Ω
L= 2.97"
R = 50Ω
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V
TT
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V
TT
C = 10pF
–V /2
DD
PI6CU877
Note: VTT = GND
–V /2
DD
Figure 3. Output Load Test Circuit 2
PS8689B
08/05/04
7
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
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Figure 6. Output Skew
PS8689B
08/05/04
8
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
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Figure 8. Half-Period Jitter
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Figure 9. Input and Output Slew Rates
PS8689B
08/05/04
9
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
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Figure 10. Dynamic Phase Offset
50% V
DD
t
OE
en
Y
Y
50% V
DD
Y/Y
OE
50% V
DD
t
dis
Y
Y
50% V
DD
Figure 11. Time Delay Between Output Enable (OE) and Clock Output (Y, Y)
PS8689B
08/05/04
10
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
Packaging Mechanical: 52-Pin VFBGA (NF)
Ordering Information
Ordering Code
PI6CU877NF
PI6CU877NFE
Package Code
Package Description
NF
NF
52-ball VFBGA
Pb-free & Green, 52-ball VFBGA
Notes:
1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com
PS8689B
08/05/04
11
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