PI6CV855LEX [PERICOM]
PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 MM, PLASTIC, TSSOP-28;型号: | PI6CV855LEX |
厂家: | PERICOM SEMICONDUCTOR CORPORATION |
描述: | PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 MM, PLASTIC, TSSOP-28 驱动 光电二极管 逻辑集成电路 |
文件: | 总9页 (文件大小:180K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
ProductFeatures
ProductDescription
PLLclockdistributionoptimizedforSSTL_2DDRSDRAM
applications.
PI6CV855PLLclockdeviceisdevelopedforSSTL_DDRSDRAM
applications. This PLL Clock Buffer is designed for 2.5 V and
DDQ
Distributes one differential clock input pair to five differential
clock output pairs.
2.5V AV operation and differential data input and output levels.
DD
The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to five differential pairs of clock outputs
(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the
Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2
Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2
Externalfeedbackpins(FBIN,FBIN)areusedto
synchronize the outputs to the input clocks.
Analog Power input (AV ). When the AV is strapped low, the
DD
DD
Operates at AV = 2.5V for core circuit and internal PLL,
DD
PLL is turned off and bypassed for test purposes.
and V
= 2.5V for differential output drivers
DDQ
ThePI6CV855isabletotrackSpreadSpectrumClockingtoreduce
EMI.
AvailablePackage:
Plastic28-pinTSSOP
PinConfiguration
BlockDiagram
28
1
GND
Y0
Y4
Y4
V
Y0
27
2
Y0
Y1
26
25
3
Y0
DDQ
CLK
CLK
V
4
GND
DDQ
CLK
CLK
Y1
Y2
24
5
FBOUT
FBOUT
PLL
FBIN
FBIN
28-Pin 23
6
Y2
Y3
V
AV
L
22
21
20
19
18
17
16
15
7
DDQ
DD
FBIN
FBIN
GND
8
AGND
GND
Y1
Y3
Y4
9
10
11
12
13
14
Y4
V
Y1
DDQ
Logic
and
FBOUT
FBOUT
V
Y3
DDQ
Y2
Y2
Test Ciruit
AV
DD
Y3
GND
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PI6CV855
PLLClockDriverfor2.5V
SSTL 2 DDR SDRAM Memory
PinoutTable
Pin
Name
I/O
Type
Pin No.
Description
CLK
CLK
5
6
I
Reference Clock input
Y[0:4]
Y[0:4]
3,11,13,17,27
2,10,14,16,28
Clock outputs.
Complement Clock outputs.
O
FBOUT
FBOUT
23
24
Feedback output, and Complement Feedback Output
FBIN
FBIN
21
20
I
Feedback input, and Complement Feedback input
Power Supply for I/O pins.
V
DDQ
4,12,18,22,26
7
Power
Analog/core power supply. AV can be used to bypass the PLL for testing purposes. When
DD
AV
DD
AV is strapped to ground, PLL is bypassed & CLK is buffered directly to the device outputs.
DD
AGND
GND
8
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground for I/O pins.
Ground
1,9,15,19,25
FunctionTable
Inputs
Outputs
FBOUT
PLL State
AVDD
GND
CLK
L
CLK
H
Y[0:4]
Y[0:4]
FBOUT
L
H
L
H
L
H
L
L
H
L
H
L
H
L
Bypassed/Off
GND
H
L
Bypassed/Off
2.5V(nom)
2.5V(nom)
L
H
on
on
H
L
H
H
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PI6CV855
PLLClockDriverfor2.5V
SSTL 2 DDR SDRAM Memory
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
, AV
Parameter
I/O supply voltage range and analog/core supply voltage range
Input voltage range
Min.
0.5
0.5
Max.
Units
V
3.6
DDQ
DD
V
I
V
V
+0.5
DDQ
V
Output voltage range
Storage temperature
0.5
65
O
o
C
Tstg
150
Note: Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
TimingRequirements(Overrecommendedoperatingfree-airtemperature)
AV , V
= 2.5V ±0.2V
DD DDQ
Symbol
Description
Units
Min.
60
Max.
170
170
60
(1,2)
(3)
Operating clock frequency
f
MHz
CK
Application clock frequency
Input clock duty cycle
95
t
DC
40
%
µs
t
PLL stabilization time after powerup
100
STAB
Notes:
1.The PLL is able to handle spread spectrum induced skew.
2.Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is
not required to meet the other timing parameters. (Used for low-speed debug).
3.Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
PS8545B 04/03/02
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PI6CV855
PLLClockDriverfor2.5V
SSTL 2 DDR SDRAM Memory
DCSpecifications
Recommended Operating Conditions
Symbol
Parameter
Min.
Nom.
2.5
Max.
2.7
Units
AVDD Analog/core supply voltage
VDDQ Output supply voltage
2.3
2.3
2.5
2.7
VOH
VOL
VIX
High-level output voltage
1.8
0
VDDQ
Low-level output voltage
0.5
Input differential-pair crossing voltage
(VDDQ/2) 0.2
(VDDQ/2) 0.2
0.3
(VDDQ/2) +0.2
(VDDQ/2) +0.2
VDDQ +0.3
VDDQ +0.6
V
VOX Output differential-pair crossing voltage at the SDRAM clock input
VIN
VID
Input voltage level
Input differential voltage between CLK and CLK
0.36
Output differential voltage between Y[n] and Y[n] and FBOUT
and FBOUT
VOD
TA
0.7
0
VDDQ +0.6
70
Operating free air temperature
°C
ElectricalCharacteristics
Parameter
Test Conditions
II = 18mA
AVDD, VDDQ Min.
Typ. Max. Units
VIK
II
All inputs
2.3V
2.7V
1.2
±10
V
CLK, FBIN
VI = VDDQ or GND
VDD = 2.7V (1)
µA
IDDQ
Dynamic supply current of VDDQ
300
12
mA
mA
IADD
CI
Dynamic supply current of AVDD
CLK and CLK
VDD = 2.7V (1)
VI = VDD or GND
2.5V
2.0
3.0
pF
FBIN and FBIN
Notes:
1.Driving 9 or 18 DDR SDRAM memory chips with 120-ohm termination resistor for each clock output pair at 134 MHz.
PS8545B 04/03/02
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PI6CV855
PLLClockDriverfor2.5V
SSTL 2 DDR SDRAM Memory
ACSpecifications
Switching characteristics over recommended operating free-air temperature range, fCLK > 100 MHz (unless otherwise noted).
(See Figure 1 and 2)
AVCC, VDDQ = 2.5V ±0.2V
Parameter
Description
Static phase offset(1)
Diagram
Units
Min.
50
75
75
100
1.0
Nom.
Max
50
t( )
tjit(cc)
tjit(per)
tjit(hper)
tsl(i)
Figure 4
Figure 3
Figure 6
Figure 7
Figure 8
Figure 8
Figure 5
0
Cycle-to-cycle jitter
Period jitter
75
ps
75
Half-period jitter
100
2.0
2.0
100
Input clock slew rate(2)
Output clock slew rate(2)
Output clock skew
V/ns
ps
tsl(o)
1.0
tsk(o)
The PLL on the PI6CV855 meets all the above parameters while supporting SSC synthesizers with the following parameters(3).
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth
30.0
0.00
50.0
kHz
%
0.50
2
MHz
degrees
Phase angle
0.031
Notes:
1. Static Phase offset does not include jitter.
2. The slew rate is determined from the IBIS model with test load shown in Figure 1.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
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PI6CV855
PLLClockDriverfor2.5V
SSTL 2 DDR SDRAM Memory
V
DD
Z = 60Ω
Z = 60Ω
DDR
SDRAM
R =120Ω
DDR
SDRAM
Figure1.IBISModelOutputLoad
V
/2
DDQ
Z = 60Ω
Z = 60Ω
Z = 50Ω
Z = 50Ω
R =10Ω
C=14pF
R = 50Ω
–V
–V
/2
DDQ
R =10Ω
C=14pF
/2
R = 50Ω
DDQ
SCOPE
–V
/2
DDQ
Figure2.OutputLoadTestCircuit
PS8545B 04/03/02
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PI6CV855
PLLClockDriverfor2.5V
SSTL 2 DDR SDRAM Memory
Yx,FBOUT
Yx,FBOUT
tcycle n
tjit(cc) tcycle n
tcycle n+1
=
-
tcycle n+1
Figure3.Cycle-to-CycleJitter
CLK
CLK
FBIN
FBIN
t(
t(
)
n
)
n+1
n=N
1
t(
∑
) n
t
=
(N is a large number of samples)
N
Figure 4. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure5.OutputSkew
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PI6CV855
PLLClockDriverfor2.5V
SSTL 2 DDR SDRAM Memory
Yx, FBOUT
Yx, FBOUT
tcycle n
Yx, FBOUT
Yx, FBOUT
1
fO
1
fO
t jit(per)
=
tcycle n
Figure 6. Period Jitter
Yx, FBOUT
Yx, FBOUT
t n+1
thalf period n
half period
1
fO
1
2*fO
tjit(hper)
=
thalf period n
Figure7.Half-PeriodJitter
VDDQ
80%
80%
20%
0V
20%
Clock Inputs
and Outputs
tsl(i), sl(o)
t
tsl(i), tsl(o)
Figure8.InputandOutputSlewRates
PS8545B 04/03/02
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PI6CV855
PLLClockDriverfor2.5V
SSTL 2 DDR SDRAM Memory
PackagingMechanical:28-PinTSSOP(L)
28
.169
.177
4.3
4.5
0.09
0.20
.004
.008
1
.378
.386
0.45 .018
0.75 .030
9.6
9.8
.252
BSC
6.4
.047
1.20
Max
SEATING
PLANE
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
.002
.006
0.05
0.15
.007
.012
.0256
BSC
0.19
0.30
0.65
OrderingInformation
Ordering Code
Package Name
Package Type
28-pin, 4.4mm wide TSSOP
PI6CV855L
L28
Pericom Semiconductor Corporation
2380BeringDrive SanJose,CA951311-800-435-2336 Fax(408)435-1100 http://www.pericom.com
PS8545B 04/03/02
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