PI6CVF857 [PERICOM]
1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory; 1:10 PLL时钟驱动器的2.5V DDR -SDRAM内存
| 型号： | PI6CVF857 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory |
| 文件： | 总14页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
ProductFeatures
ProductDescription
• Operating Frequency up to 220 MHz for PC3200 Registered
PI6CVF857PLLclockdeviceisdevelopedforregisteredDDRDIMM
applications. The device is a zero-delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten differential pairs of
clockoutputs(Y[0:9],Y[0:9]),andonedifferentialpairfeedbackclock
outputs(FBOUT,FBOUT). Theclockoutputsarecontrolledbythe
inputclocks(CLK,CLK),thefeedbackclocks(FBIN,FBIN),the2.5V
DIMM applications
• Distributes one differential clock input pair to ten differential
clock output pairs
• Inputs(CLK,CLK)and(FBIN,FBIN)
• Input PWRDWN: LVCMOS
• Outputs (Yx,Yx),(FBOUT,FBOUT)
• Externalfeedbackpins(FBIN,FBIN)areusedto
synchronize the outputs to the clock input
• Operatesat2.5VforPC1600,PC2100,PC2700,
and2.6VforPC3200
LVCMOSinput(PWRDWN),andtheAnalogPowerinput(AV ).
DD
When input PWRDWN is low while power is applied, the input
receiversaredisabled,thePLListurnedoff,andthedifferentialclock
outputs are 3-stated. When the AV is strapped low, the PLL is
DD
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
willenteralowpowermode.Aninputfrequencydetectioncircuitwill
detectthelowfrequencyconditionandperformthesamelowpower
features as when the PWRDWN input is low.
ThePLLinthePI6CVF857clockdriverusestheinputclocks(CLK,
CLK)andthefeedbackclocks(FBIN,FBIN)toprovidehigh-perfor-
mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]).
The PI6CVF857 is also able to track Spread Spectrum Clocking for
reducedEMI.
• Packaging (Pb-free & Green available, select packages):
–48-pinTSSOP
–40-pinTQFN
–56-ballVFBGA
BlockDiagram
Y0
Y0
Y1
CLK
Y1
CLK
Y2
PLL
FBIN
FBIN
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Powerdown
and Test
Logic
PWRDWN
Y6
Y7
AV
DD
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
PS8683B
10/17/03
1
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
PinConfigurationTSSOP(A)
PinConfigurationQFN(ZD)
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y0
GND
Y5
Y5
V
3
4
Y0
V
D D Q
Y1
D D Q
5
6
Y6
Y1
Y6
GND
40 39 38 37 36 35 34 33 32 31
7
GND
Y2
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
24
23
22
21
Y7
Y7
GND
GND
Y2
8
9
GND
Y7
Y7
V
Y2
V
DDQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Y2
48-Pin
A
V
PWRDWN
FBIN
DDQ
V
V
D D Q
D D Q
CLK
GND
D D Q
CLK
CLK
D D Q
P W R DW N
FBIN
CLK
FBIN
V
V
V
DDQ
DDQ
DDQ
FBIN
AV
DD
V
V
D D Q
AGND
FBOUT
FBOUT
AV
FBOUT
FBOUT
D D
GND
10
11 12 13 14 15 16 17 18 19 20
AGND
GND
Y3
GND
Y8
Y8
Y3
V
V
D D Q
D D Q
Y4
Y4
Y9
Y9
GND
GND
BallConfiguration
BallConfiguration VFBGA(NF)
1
Y0
2
Y0
3
4
5
Y5
6
A
B
C
D
E
F
GND
GND
Y5
Y6
1
2
3
4
5
6
Y1
Y1
VDDQ VDDQ
Y6
A
B
C
D
E
F
GND
Y2
GND
Y2
NC
NC
NB
NB
NC
NC
NC
NC
NB
NB
NC
NC
GND
Y7
GND
Y7
VDDQ VDDQ
CLK CLK
VDDQ AVDD
VDDQ PWRDWN
FBIN
FBOUT
GND
Y8
FBIN
VDDQ
FBOUT
Y8
G
H
J
G
H
J
AGND
Y3
GND
Y3
K
VDDQ VDDQ
GND GND
NO CONNECT on C3, C4, D3, D4,
G3, G4, H3 and H4
K
Y4
Y4
Y9
Y9
Notes:
NC = No Contact
NB=NoBall
PS8683B
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PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
PinoutTable
Pin Name
Description
CLK
CLK
Reference Clock input
Yx
Yx
Clock outputs.
Complement Clock outputs.
FBOUT
FBOUT
Feedback output, and Complement Feedback Output
Feedback Input, and Complement Feedback Input
FBIN
FBIN
Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and
the differential clock outputs are disabled to a - state. When PWRDWN = 1, all differential clock outputs are
enabled and run at the same frequency as CLK.
PWRDWN
VDDQ
AVDD
Power Supply for I/O.
Analog /core power supply. AVDD can be used to bypass the PLL for testing purposes. When AVDD is strapped to
ground, PLL is bypassed and CLK is buffered directly to the device outputs.
AGND
GND
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
FunctionTable
Inputs
Outputs
FBOUT
PLL
AV
PWRDWN
CLK
L
CLK
H
Y
L
H
Z
Z
L
H
Z
Y
H
L
Z
Z
H
L
Z
FBOUT
DD
GND
GND
X
H
H
L
L
H
Z
Z
L
H
Z
H
L
Z
Z
H
L
Z
Bypassed/off
H
L
Bypassed/off
L
H
off
off
on
on
off
X
L
H
L
(2)
Nominal
H
H
X
L
H
(2)
Nominal
H
L
(1)
(2)
Nominal
< 20 MHz
Notes:
1. For testing and power saving purposes, PI6CVF857 will power down if the frequency of the reference inputs CLK, CLK is well below the
operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CVF857 will be powered down when
the CLK,CLK stop running.
2. AVDD Nominal is 2.5V for PC1600, PC2100, and PC2700. AVDD Nominal is 2.6V for PC3200.
Z = High impedance
X = Don’t care
PS8683B
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PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
AbsoluteMaximumRatings(Overoperatingfree-airtemperaturerange)
Symbol
Parameter
I/O supply voltage range and analog/core supply voltage range
Input voltage range
Min.
– 0.5
– 0.5
– 0.5
– 50
– 50
– 50
– 100
– 65
Max.
Units
VDDQ, AVDD
3.6
VI
VO
V
VDDQ +0.5
Output voltage range
IIK
Input Clamp Current
50
50
IOK
Output Clamp Current
mA
IO
Continuous output Current
50
IO(PWR)
Tstg
Continuous current through each AVDD, VDDQ, or GND
Storage temperature
100
150
104
38
oC
oC/w
oC/w
Junction to ambient thermal (package A)
Junction to case thermal (package A)
JA
JC
Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DCSpecifications
Recommended Operating Conditions
Symbol
Parameter
Min.
– 0.12
Nom.
Max.
2.7
Units
AV
Analog/core supply voltage
Output supply voltage
V
DDQ
V
DDQ
DD
PC1600 - PC2700
PC3200
2.3
2.5
–0.3
1.7
–
2.5
2.6
2.7
V
DDQ
2.7
V
V
IL
Low-level input voltage for PWRDWN pin
High-level input voltage for PWRDWN pin
High-level output current
0.7
V
IH
V
+0.3
DDQ
I
OH
12
mA
I
OL
Low-level output current
–
–12
(V
/2)
DDQ
V
Input differential-pair crossing voltage
Input voltage level
(V
/2) +0.2
IX
DDQ
–0.2
V
IN
–0.3
V
V
V
+0.3
+0.6
+0.6
DDQ
DDQ
DDQ
V
DC
AC
0.36
0.7
Input differential voltage between CLK and
CLK
V
ID
T
A
Operating free air temperature
–40
85
°C
PS8683B
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PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
TimingRequirementsforPC1600~PC2700(Overrecommendedoperatingfree-airtemperature)
AV , V
= 2.5V ±0.2V
DD
DDQ
Symbol
Description
Units
Min.
60
Max.
170
170
60
(1,2)
Operating clock frequency
f
CK
MHz
(3)
Application clock frequency
95
t
DC
Input clock duty cycle
40
%
µs
t
PLL stabilization time after powerup
100
STAB
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing
parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
ElectricalCharacteristicsforPC1600~PC2700(Overrecommendedoperatingfree-airtemperature)
Parameter
Test Conditions
A
VDD
, V
Min.
Typ. Max. Units
DDQ
V
IK
All inputs
I = –18mA
I
2.3V
–1.2
I
= –100µA
= –12mA
= 100µA
= 12mA
2.3 to 2.7V
2.3V
V
– 0.1
OH
DDQ
V
High output voltage
Low output voltage
OH
I
OH
1.7
V
I
OL
2.3 to 2.7V
2.3V
0.1
0.6
V
OL
I
OL
CLK, FBIN
PWRDWN
V = V
or GND
or GND
2.7V
I
DDQ
I
I
±10
µA
V = V
2.7V
I
DDQ
CLK & CLK = 0 MHz,
PWRDWN = Low
I
Static supply current I
+ I
ADD
200
DDPD
DDQ
CLK & CLK = 170 MHz
All outputs are open
I
Dynamic supply current of V
2.7V
2.7V
300
12
mA
mA
DDQ
DDQ
I
Dynamic supply current of AV
CLK and CLK
CLK & CLK = 170 MHz
ADD
DD
C
V = V
or GND
or GND
2.5V
2.5V
2.0
3.5
I
I
DDQ
FBIN and FBIN
pF
(5)
CLK and CLK
C
V = V
–0.25
0.25
I(∆)
I
DDQ
(5)
FBIN and FBIN
Note:
4. The maximum power-down clock frequency is below 20 MHz.
5. Guaranteed by design, but not production tested.
PS8683B
10/17/03
5
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
TimingRequirementsforPC3200(Overrecommendedoperatingfree-airtemperature)
AV , V
= 2.6V ±0.1V
Units
DD
DDQ
Symbol
Description
Min.
60
Max.
(1,2)
Operating clock frequency
220
f
CK
MHz
220
(3)
Application clock frequency
95
t
Input clock duty cycle
40
60
%
µs
DC
t
PLL stabilization time after powerup
100
STAB
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing
parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
ElectricalCharacteristicsforPC3200(Overrecommendedoperatingfree-airtemperature)
Parameter
All inputs
Test Conditions
I = –18mA
A
, V
Min.
Typ. Max. Units
VDD
DDQ
V
IK
2.5V
–1.2
I
I
= –100µA
= –12mA
= 100µA
= 12mA
2.5 to 2.7V
2.5V
V
– 0.1
OH
DDQ
V
High output voltage
Low output voltage
OH
I
OH
1.7
V
I
OL
2.5 to 2.7V
2.5V
0.1
0.6
V
OL
I
OL
CLK, FBIN
PWRDWN
V = V
or GND
or GND
2.7V
I
DDQ
I
I
±10
µA
V = V
2.7V
I
DDQ
CLK & CLK = 0 MHz,
PWRDWN = Low
I
Static supply current I
+ I
ADD
200
DDPD
DDQ
CLK & CLK = 200 MHz
All outputs are open
I
Dynamic supply current of V
2.7V
2.7V
300
12
mA
mA
DDQ
DDQ
I
Dynamic supply current of AV
CLK and CLK
CLK & CLK = 200 MHz
ADD
DD
C
V = V
or GND
or GND
2.6V
2.6V
2.0
3.5
I
I
DDQ
FBIN and FBIN
pF
(5)
CLK and CLK
C
V = V
–0.25
0.25
I(∆)
I
DDQ
(5)
FBIN and FBIN
Note:
4. Themaximumpower-downclockfrequencyisbelow20MHz.
5. Guaranteed by design, but not production tested.
PS8683B
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6
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
AC Specifications for PC1600 ~ PC2700
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )
AVDD, VDDQ = 2.5V ±0.2V
Parameter
Description
Cycle-to-cycle jitter
Static phase offset(1)
Diagram
Units
Min.
–50
Nom.
Max
tjit(cc)
t(θ)
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 9
50
–50
0
50
tsk(o)
tjit(per)
tjit(hper)
tsl(i)
Output clock skew
75
ps
Period jitter
–75
–100
75
Half-period jitter
100
4.0
Input clock slew rate
Output clock slew rate(2)
Output differential-pair cross-voltage
1.0
V/ns
V
tsl(o)
1.0
2.0
VOX
(VDDQ/2) –0.1
(VDDQ/2) +0.1
The PLL is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth(4)
Phase angle
30.00
0.00
2
50.00
–0.50
kHz
%
MHz
degrees
–0.031
Notes:
1. Static Phase offset does not include Jitter.
2. The Output Skew Rate is calculated by using the load shown in Figure 3.
3. V specified at the DRAM clock input or the test load in Figure 2.
OX
4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
PS8683B
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PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
ACSpecificationsforPC3200
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )
AVDD, VDDQ = 2.6V ±0.1V
Parameter
Description
Cycle-to-cycle jitter
Static phase offset(1)
Diagram
Units
Min.
–50
Nom.
Max
tjit(cc)
t(θ)
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 9
50
–50
0
50
tsk(o)
tjit(per)
tjit(hper)
tsl(i)
Output clock skew
75
ps
Period jitter
–50
50
Half-period jitter
–75
1.0
75
4.0
Input clock slew rate
Output clock slew rate(2)
Output differential-pair cross-voltage
V/ns
V
tsl(o)
1.0
2.0
VOX
(VDDQ/2) –0.1
(VDDQ/2) +0.1
The PLL is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth(4)
Phase angle
30.00
0.00
2
50.00
–0.50
kHz
%
MHz
degrees
–0.031
Notes:
1. Static Phase offset does not include Jitter.
2. The Output Skew Rate is calculated by using the load shown in Figure 3.
3. V specified at the DRAM clock input or the test load in Figure 2.
OX
4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
PS8683B
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8
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
V
DD
V
CLK
R=60Ω
R=60Ω
V
/2
DD
V
CLK
Figure1.IBISModelOutputLoad
V
DDQ
C=14pF
Z=60Ω
R=1MΩ
C=1pF
R=120Ω
Z=60Ω
GND
C=14pF
R=1MΩ
C=1pF
GND
PROBE
GND
Figure2.OutputLoadTestCircuit1
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PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
V
/2
DD
–V /2
DD
C=14pF
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=50Ω
Z=60Ω
V
V
TT
R=10Ω
R=50Ω
C=14pF
TT
–V /2
DD
Scope
V
= GND
TT
–V /2
DD
Figure3.OutputLoadTestCircuit2
PS8683B
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10
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Yx,FBOUT
Yx,FBOUT
tcycle n
tjit(cc) tcycle n
tcycle n+1
=
-
tcycle n+1
Figure4.Cycle-to-CycleJitter
CLK
CLK
FBIN
FBIN
t(
t(
)
n
)
n+1
n=N
t(
∑
) n
1
t
=
(N > 1000 samples)
N
Figure 5. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure6.OutputSkew
PS8683B
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PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Yx, FBOUT
Yx, FBOUT
tcycle n
Yx, FBOUT
Yx, FBOUT
1
fO
1
fO
t jit(per)
=
tcycle n
(f = input frequency measured at CLK, CLK)
O
Figure 7. Period Jitter
Yx, FBOUT
Yx, FBOUT
t n+1
thalf period n
half period
1
fO
1
2*fO
tjit(hper)
=
thalf period n
Figure8.Half-PeriodJitter
80%
80%
Clock Inputs
and Outputs
V
, V
OD
ID
20%
20%
t
t
f(i), f(o)
t
t
r(i), r(o)
t
=
t
=
slr(i/o)
slf(i/o)
t
t
f(i/o)
r(i/o)
Figure9.InputandOutputSlewRates
PS8683B
10/17/03
12
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
PackagingMechanical:48-PinTSSOP(A)
48
.236
.244
6.0
6.2
1
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
0.09
0.20
.004
.008
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.007
.010
.0197
BSC
.319
BSC
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.50
0.17
0.27
8.1
PackagingMechanical:40-ContactTQFN(ZD)
6.00 BSC
0.50 BSC
0 - 0.05
0.20 REF.
Pin #1
Corner
2.90 NOM.
1.00 MAX.
Pin #1
Corner
PS8683B
10/17/03
13
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
PackagingMechanical:56-BallVFBGA(NF)
OrderingInformation
Ordering Code
Package Code
Pin Count - Package Type
48-pin TSSOP
PI6CVF857A
A
PI6CVF857AE
PI6CVF857ZDE
PI6CVF857NF
AE
Pb-free & Green, 48-pin TSSOP
Pb-free & Green, 40-contact TQFN
56-ball, VFBGA
ZDE
NF
Notes:
1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/
PericomSemiconductorCorporation • 1-800-435-2336 • http://www.pericom.com
PS8683B
10/17/03
14
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