PI6ULS5V9515AUE [PERICOM]
SMBus Repeater;
| 型号： | PI6ULS5V9515AUE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | SMBus Repeater |
| 文件： | 总10页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6ULS5V9515A
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I2C Bus/SMBus Repeater
drivers on and off. This can be used to isolate a badly
Features
behaved slave on power-up until after the system power-
up reset. It should never change state during an I2C-bus
2 channel, bidirectional buffer
I2C-bus and SMBus compatible
operation because disabling during a bus operation will
hang the bus and enabling part way through a bus cycle
Operating supply voltage range of 2.3 V to 3.6 V
could confuse the I2C-bus parts being enabled. The
Active HIGH repeater enable input
Open-drain input/outputs
enable pin should only change state when the global bus
and the repeater port are in an idle state to prevent
system failures.
Lock-up free operation
The output low levels for sides are approximately 0.5
V, but the input voltage of each internal buffer must be
70 mV lower (0.43V) or even more lower. When the
output internally is driven low the low is not recognized
as a low by the input.. This prevents a lockup condition
from occurring when the input low condition is released.
Two or more PI6ULS5V9515A devices can’t be
used in series. The PI6ULS5V9515A design does not
allow this configuration. Since there is no direction pin,
slightly different valid low-voltage levels are used to
avoid lockup conditions between the input and the
output of each repeater. A valid low applied at the input
of a PI6ULS5V9515A will be propagated as a buffered
low with a slightly higher value on the output. When this
buffered low is applied to another PI6ULS5V9515A-
type device in series, the second device does not
recognize it as a valid low and will not propagate it as a
buffered low again.
Supports arbitration and clock stretching across the
repeater
Accommodates Standard-mode and Fast-mode I2C-
bus devices and multiple masters
Powered-off high-impedance I2C-bus pins
5.5 V tolerant I2C-bus and enable pins
0 Hz to 400 kHz clock frequency (the maximum
system operating frequency may be less than 400
kHz because of the delays added by the repeater)
ESD protection exceeds 4KV HBM per JESD22-
A114
Package: MSOP-8, SOIC-8 and DFN2x3-8L
The device contains a power-up control circuit that
sets an internal latch to prevent the output circuits
from becoming active until Vcc is at a valid level (Vcc =
2.3 V).
Description
The PI6ULS5V9515A is a CMOS integrated circuit
intended for I2C bus and SMBus systems applications.
The device contains two identical bidirectional open-
drain buffer circuits that enable I2C and similar bus
systems to be extended without degradation of system
performance.
The PI6ULS5V9515A enables the system designer
to isolate two halves of a bus for both voltage and
capacitance, accommodating more I2C devices or longer
trace length. It also permits extension of the I2C-bus by
providing bidirectional buffering for both the data (SDA)
and the clock (SCL) lines, thus allowing two buses of
400 pF to be connected in an I2C application.
As with the standard I2C system, pull-up resistors are
required to provide the logic-high levels on the buffered
bus. The PI6ULS5V9515A has standard open-collector
configuration of the I2C bus. The size of these pull-up
resistors depends on the system, but each side of the
repeater must have a pull-up resistor. The device is
designed to work with Standard mode and Fast mode I2C
devices in addition to SMBus devices. Standard mode
I2C devices only specify 3mA in a generic I2C system,
where Standard mode devices and multiple masters are
possible. Under certain conditions, higher termination
currents can be used.
The PI6ULS5V9515A has an EN pin to turn the
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PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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Pin Configuration
MSOP-8 and SOIC-8
TDFN2x3-8L(Top View)
Pin Description
Pin No
Name
Description
1
2
3
4
5
6
7
8
n.c.
SCL0
SDA0
GND
EN
SDA1
SCL1
VCC
Not connected
serial clock port 0 bus
serial data port 0 bus
supply ground (0 V)
active HIGH repeater enable input
serial data port 1 bus
serial clock port 1 bus
supply voltage (2.3 V to 3.6 V)
Block Diagram
EN
H
Function
SCL0 = SCL1;
SDA0 = SDA1;
L
disabled
Figure 1:Block Diagram
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PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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Maximum Ratings
Note:
o
o
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
StorageTemperature...................................................................................-55 Cto+125 C
DCInputVoltage .............................................................................................-0.5Vto+6.0V
ControlInputVotage(EN)...............................................................................-0.5Vto+6.0V
TotalPowerDissipation...................................................................100mA
Input/OutputCurrent(portA&B).........................................................50mA
InputCurrent(EN, VCC(A), VCC(B), GND)............................................50mA
ESD:HBMMode...........................................................................................................4000V
Recommended operation conditions
VCC = 2.3 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified
Symbol
Parameter
Test Conditions
Min.
Typ.
-
Max.
Unit
Vcc
supply voltage port
-
2.3
3.6
V
both channels HIGH;; SDAn = SCLn = VCC
VCC = 2.7 V
both channels HIGH;; SDAn = SCLn = VCC
VCC = 3.6 V
both channels LOW; VCC = 2.7 V; one SDA and
one SCL = GND; other SDA and SCL open
both channels LOW; VCC = 3.6 V; one SDA and
one SCL = GND; other SDA and SCL open
mA
-
-
0.5
5
5
5
5
5
HIGH-level supply
current
ICCH
mA
0.5
1.6
1.7
1.6
-
-
-
mA
mA
mA
LOW-level supply
current
ICCL
contention port A
supply current
ICCLC
VCC = 2.7V or 3.6V; SDAn = SCLn = GND
DC Electrical Characteristics
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified
Parameter
Description
Test Conditions(1)
Min. Typ.(2)
Max.
Unit
Input and output SDAn and SCLn
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
-
-
0.7VCC
-0.5
-
-
5.5
+0.3Vcc
(1)
V
VILc
VIK
Contention LOW-level input voltage
Input clamping voltage
-
-0.5
0.4
-
-
II = -18 mA
-
-
-1.2
±1
V
ILI
Input leakage current
VI = 3.6 V
-
-
μA
Vcc=2.3-2.7V ;
SDA, SCL; VI = 0.2 V
Vcc=3.0-3.6V ;
SDA, SCL; VI = 0.2 V
IOL = 20 μA or 6 mA
-
10
μA
IIL
LOW-level input current
LOW-level output voltage
-
-
5
μA
VOL
VOL-VILc
Cio
0.47
0.52
0.6
V
Difference between LOW-level output and LOW-
level input voltage contention
guaranteed by design
VI = 3 V or 0 V
-
-
70
6
-
-
mV
pF
input/output capacitance
Enable
VIH
HIGH-level input voltage
LOW-level input voltage
LOW-level input current
Input leakage current
Input capacitance
-
-
2.0
-0.5
-
-1
-
-
-
-10
-
5.5
+0.8
-30
+1
V
V
μA
μA
pF
VIL
IIL
ILI
Ci
VI = 0.2 V
VI=Vcc
VI = 3.0 V or 0 V
6
-
Notes:
1 VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the
SDAn/SCLn lines.
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PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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Dynamic characteristics
GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. (1)(2)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Vcc=2.3-2.7V
tPLH
tPHL
tTLH
tTHL
tSU
tH
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
LOW-to-HIGH transition time
HIGH-to-LOW transition time
Set-up time
-
-
-
-
-
-
33
113
82
148
57
-
190
130
-
-
-
-
ns
ns
ns
ns
ns
ns
-
-
100
130
Hold time
-
Vcc=3.0-3.6V
tPLH
tPHL
tTLH
tTHL
tSU
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
LOW-to-HIGH transition time
HIGH-to-LOW transition time
Set-up time
-
-
-
-
-
-
33
102
68
147
58
-
180
120
-
-
-
-
ns
ns
ns
ns
ns
ns
-
-
100
100
tH
Hold time
-
Notes:
(1) Typical values taken at VCC = 3.3 V and Tamb = 25C.
(2) Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
Figure 2: Propagation Delay and Transition Times
Figure 3: Test Circuit
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PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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Functional Description
The PI6ULS5V9515A is a CMOS integrated circuit intended for I2C bus and SMBus systems applications. The device
contains two identical bidirectional open-drain buffer circuits that enable I2C and similar bus systems to be extended without
degradation of system performance.
The PI6ULS5V9515A enables the system designer to isolate two halves of a bus for both voltage and capacitance.,
accommodating more I2C devices or longer trace length. It also permits extension of the I2C-bus by providing bidirectional
buffering for both the data (SDA) and the clock (SCL) lines, thus allowing two buses of 400 pF to be connected in an I2C
application.
The PI6ULS5V9515A has an EN pin to turn the drivers on and off. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an I2C-bus operation because disabling during
a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus parts being enabled. The
enable pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures.
The output low levels for sides are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV lower
(0.43V) or even more lower. When the output internally is driven low he low is not recognized as a low by the input.. This
prevents a lockup condition from occurring when the input low condition is released.
Two or more PI6ULS5V9515A devices can’t be used in series. The PI6ULS5V9515A design does not allow this configuration.
Since there is no direction pin, slightly different valid low-voltage levels are used to avoid lockup conditions between the input
and the output of each repeater. A valid low applied at the input of a PI6ULS5V9515A will be propagated as a buffered low with a
slightly higher value on the output. When this buffered low is applied to another PI6ULS5V9515A-type device in series, the
second device does not recognize it as a valid low and will not propagate it as a buffered low again.
The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from becoming
active until Vcc is at a valid level (Vcc = 2.3 V).
As with the standard I2C system, pull-up resistors are required to provide the logic-high levels on the buffered bus. The
PI6ULS5V9515A has standard open-collector configuration of the I2C bus. The size of these pull-up resistors depends on the
system, but each side of the repeater must have a pull-up resistor. The device is designed to work with Standard mode and Fast
mode I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3 mA in a generic I2C system, where
Standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.
Application Information
A typical application is shown in Figure 4. In this example, the system master is running on a 3.3 V I2C-bus while the slave is
connected to a 5V bus. Both buses run at 400 kHz. Master devices can be placed on either bus.
The PI6ULS5V9515A is 5V tolerant, so it does not require any additional circuitry to translate between different bus voltages.
When one side of the PI6ULS5V9515A is pulled LOW by a device on the I2C-bus, a CMOS hysteresis type input detects the
falling edge and causes the internal driver on the other side to turn on, thus causing the other side to also go LOW. The side driven
LOW by the PI6ULS5V9515A will typically be at VOL = 0.5 V.
Figure 5 and Figure 6 show the waveforms that are seen in a typical application. If the bus master in Figure4 writes to the slave
through the PI6ULS5V9515A, Bus 0 has the waveform shown in Figure 5. This looks like a normal I2C transmission until the
falling edge of the eighth clock pulse. At that point, the master releases the data line (SDA) while the slave pulls it low through the
PI6ULS5V9515A. Because the VOL of the PI6ULS5V9515A typically is around 0.5V, a step in the SDA is seen. After the master
has transmitted the ninth clock pulse, the slave releases the data line.
On the Bus 1 side of the PI6ULS5V9515A, the clock and data lines have a positive offset from ground equal to the VOL of the
PI6ULS5V9515A. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is very close to ground
in the example.
It is important to note that any arbitration or clock-stretching events on Bus 1 require that the VOL of the devices on Bus 1 be
70 mV below the VOL of the PI6ULS5V9515A (see VOL - VILC in Electrical Characteristics) to be recognized by the
PI6ULS5V9515A and transmitted to Bus 0.
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PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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PI6ULS5V9515A
Figure 4: Typical Application
VOL of PI6ULS5V9515A
Figure 5: Bus 0 Waveforms
VOL of PI6ULS5V9515A
Figure 6: Bus 1 Waveforms
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PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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Mechanical Information
MSOP-8
Dimensions In Millimeters
Symbol
Min
0.82
0.02
0.75
0.25
0.09
2.90
2.90
4.75
Max
1.10
0.15
0.95
0.38
0.23
3.10
3.10
5.05
A
A1
A2
b
c
D
E
Note:
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MO-187E/BA
E1
e
0.65 BSC
L
0.40
0°
0.80
6°
θ
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PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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SOIC-8
Dimensions In Millimeters
Symbol
Min
1.350
0.100
1.350
0.330
0.170
4.700
3.800
5.800
Max
1.750
0.250
1.550
0.510
0.250
5.100
4.000
6.200
A
A1
A2
b
Note:
c
D
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MS-012E/AA
E
E1
e
L
θ
1.27 BSC
0.400
0°
1.270
8°
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PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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TDFN2x3-8L
PKG. DIMENSIONS(MM)
SYMBOL
MIN.
0.70
0.00
MAX
0.80
0.50
A
A1
A3
D
0.20REF
1.92
2.92
1.40
1.40
2.08
3.07
1.60
1.60
E
D1
E1
k
0.20MIN
Note:
b
e
0.20
0.30
0.38
Ref: JEDEC MO-229
0.50TYP
L
0.22
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PI6ULS5V9515A
I2C-Bus/SMBus Repeater
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Recommended Land pattern for TDFN2*3-8L
Note:
All linear dimensions are in millimeters
Ordering Information
Part No.
Package Code
Package
PI6ULS5V9515AUE
PI6ULS5V9515AUEX
PI6ULS5V9515AWE
PI6ULS5V9515AWEX
U
U
Lead free and Green 8-pin MSOP
Lead free and Green 8-pin MSOP, Tape & Reel
Lead free and Green 8-pin SOIC
W
W
Lead free and Green 8-pin SOIC, Tape & Reel
Lead free and Green 8 TDFN2x3-8L, Tape &
Reel
PI6ULS5V9515AZEEX
ZE
Note:
E = Pb-free
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
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