PI90LVT211QX [PERICOM]
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| 型号： | PI90LVT211QX |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | 暂无描述 时钟 |
| 文件： | 总9页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI90LV211/PI90LVT211
1:6 Differential Clock Distribution Chip
Description
Features
ThePI90LV211implementslowvoltagedifferentialsignaling(LVDS)
to achieve clocking rates as high as 320 MHz with low skew. The
PI90LV211isalowskew1:6fanoutdevicedesignedexplicitlyforlow
skew clock distribution applications. The device features a multi-
plexedclockinputtoallowforthedistributionofalowerspeedscan
ortestclockwiththehigh-speedsystemclock.WhenLOW theSEL
pin will select the differential clock input.
Both a common enable and individual output enables are provided.
WhenassertedthepositiveoutputwillgoLOWonthenextnegative
transition of the CLK (or SCLK) input. The enable function is
synchronoussothattheoutputswillonlybeenabled/disabledwhen
they are already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/disabled
as can happen with an asynchronous control. The internal flip flop
is clocked on the falling edge of the input clock, therefore all
associated specification limits are referenced to the negative edge
of the clock input.
• MeetsorExceedsRequirementsofANSITIA/EIA-644-1995
• Designed for Clocking Rates up to 320MHz
• Operates from a single 3.3-V Supply
• Low-VoltageDifferentialSignaling(LVDS)withOutput
Voltagesof±350mVintoa100-ohmload
• Choice between LVDS or TTL clock input
• Synchronous Enable/Disable
• Multiplexedclockinput
– Internal 300 kohm pullup resistor on all control pins
–CLKandCLKhave110-ohmtermination(PI90LVT211)
• Common and individual Enable/Disable control
• 50ps Output-to-Output Skew
• ±24psPeriodJitter
• Bus Pins are High Impedance when disabled or with V <1.5V
CC
• TTL Inputs are 5V Tolerant
• Power Dissipation at 300 MHz
• P190LV211 isfunctionallycompatiblewithMotorola’s
(PECL)MC10E211/MC100E211
• >12kVESDProtection
Individual synchronous enable controls and multiplexed clock in-
puts make this device ideal as the first level distribution unit in a
distributiontree. Theindividualenablescouldbeusedtoallowforthe
disabling of individual cards on a backplane in fault tolerant designs.
• Packaging(Pb-free&Greenavailable):
-28-pinTSSOP(L)
-28-pin QSOP(Q)
FunctionTable
BlockDiagram&PinConfiguration
CLK/CLK SCLK SEL ENx CEN CLK OUT (±)
H/L
X
X
H/L
↓
L
H
X
H
L
L
H
L
L
L
L
H
CLK
SCLK
Z*
VCC
EN1
1
2
28
27
VCC
D
↓
CLK1OUT+
26
↓
↓
Z**
CLK1OUT–
3
4
Q
Q
GND
EN2
25
24
D
*
ENx disables individual banks
CLK2OUT+
CLK2OUT–
5
6
1
SCLK
CLK
** CEN disables all six banks
↓ = NegativetransitionofCLKorSCLK
Z = High Impedance
PI90LVT211
Only
110Ω
23
22
D
D
CLK3OUT+
CLK3OUT–
7
0
CLK
EN3
8
9
Q
Q
21
20
CLK4OUT+
CLK4OUT–
SEL
EN4
10
19
18
D
D
CLK5OUT+
CLK5OUT–
11
12
EN5
EN6
Q
Q
17
16
CLK6OUT+
CLK6OUT–
13
14
CEN
GND
15
GND
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PI90LV211/PI90LVT211
1:6 Differential Clock
DistributionChip
ElectricalCharacteristicsoverRecommendedOperatingConditions(unlessotherwisenoted).
Symbol
Parameter
Test Conditions
Min.
Typ.(1) Max. Units
VOD
Differential output voltage magnitude
247
340
454
50
RL = 100Ω
mV
V
Change in differential output voltage
magnitude between logic states
See Figures 1 and 2
∆ VOD
VOC(SS)
∆VOC(SS)
VOC(PP)
–50
1.125
–50
Steady-state common-mode output
voltage
1.30
1.60
50
Change in steady-state common-mode
output voltage between logic states
See Figure 3
mV
Peak-to-peak common-mode output
voltage
40
150
Enabled, RL = 100Ω VIN = VCC or GND
Disabled, VIN = VCC or GND
VIH = 2V
27
3.0
4.8
9
35
3.9
20
ICC
Supply Current
mA
µA
IIH
IIL
High-level input current
Low-level input current
VIL = 0.8V
20
V
ODOUT+ or VODOUT– = 0V
OD = 0V
±7
IOS
Short-circuit output current
mA
µA
V
±4.5
±1
IOZ
IO(OFF)
CIN
High-impedance output current
Power-off output current
Input capacitance,
VO = 0V or VCC
VCC = 1.1V, VO = 2.4V
VI = 0.4 sin (4E6πt) +0.5V
VI = 0.4 sin (4E6πt) +0.5V, Disabled
PI90LVT211
±1
9
pF
CO
Output capacitance
10
RTERM
Termination Resistor
90
110
132
Ω
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PI90LV211/PI90LVT211
1:6 Differential Clock
DistributionChip
SwitchingCharacteristicsoverRecommendedOperatingConditions(unlessotherwisenoted)(8,9).
Characteristic
Symbol
Min.
Typ.
Max.
Units
Condition
Propagation Delay to Output
CLK to CLKOUT ±
SCLK to CLKOUT ±
SEL to CLKOUT ±
tPLH
tPHL
1.5
1.5
1.5
2.7
2.7
2.7
3.4
3.24
3.6
ns
Disable Time
CLK or SCLK to CLKOUT ±
tPHZ
tPLZ
tPZH
tPZL
2.2
2.1
3.6
2.8
2.8
2.8
4.8
4.8
2
1
Part-to-Part Skew
CLK (Diff) to Q
CLK (SE), SCLK to Q
With Device Skew
tskew
TBD
TBD
TBD
Cycle-to-Cycle Jitter
Period Jitter
Setup Time
ENx to CLK
CEN to CLK
tjit(cc)
–48
–24
+48
+24
Figure 6
Figure 7
tjit(per)
ps
V
ts
200
200
–100
0
2
Hold Time
2
CLK to ENx, CEN
th
600
760
0.800
Minimum Input Swing (CLK)
Com. Mode Range (CLK)
VPP
0.20
3
4
VCMR
0.125
1.5
VCC - 0.2
Rise/Fall Times
20 – 80%
tr, tf
150
400
1200
Duty Cycle Distortion Pulse Skew ( tPLH - tPHL
)
ps
SCLK to CLKOUT±
tSK1R
tSK1R
140
25
180
60
5
CLK to CLKOUT±
Channel-to-Channel Skew, same edge
Maximum Operating Frequency
Notes:
tSK2R
30
100
6
7
250
MHz
1. Within-Device skew is defined for identical transitions on similar paths through a device.
2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.
3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input
swings.
4. The range in which the high level of the input swing must fall while meeting the VPP spec.
5. tSKIR is the difference in receiver propagation delay (tPLH-tPHL) of one device, and is the duty cycle distortion of the output at any given
temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage, and temperature.
6. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This
parameter is guaranteed by design and characterization.
7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).
Output Criteria: 60%/40% duty cycle, VOL (max) 0-4V, VOH (min) 2.7V, Load - 7pF (stray plus probes).
8. CL includes probe and fixture capacitance.
9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50 ohms, tr = 1ns, tf = 1ns (35%-65%). To ensure fastest propagation
delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
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PI90LV211/PI90LVT211
1:6 Differential Clock
DistributionChip
ParameterMeasurementInformation
IOY
DOUT+
II
DIN
VOD
IOZ
VODOUT+
VOC
DOUT–
GND
VI
VODOUT–
(VODOUT++VODOUT–)/2
Figure1. VoltageandCurrentDefinitions
3.75kΩ
100Ω
3.75kΩ
DOUT+
VOD
Input
DOUT–
±
0V ≤ V
≤ 2.4V
TEST
Figure 2. VOD Test Circuit
3V
0V
49.9Ω ±1% (2 places)
DOUT+
VI
V
OC(PP)
Input
V
V
OC(SS)
OC
DOUT–
Figure3.TestCircuit&DefinitionsfortheDriverCommon-ModeOutputVoltage
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition Rate
(PRR) = 50 Mpps, Pulse width = 10 ±0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
Themeasurement of VOC(PP) is made on test equipment with a –3dB bandwidth of at least 300MHz.
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PI90LV211/PI90LVT211
1:6 Differential Clock
DistributionChip
ParameterMeasurementInformation(continued)
32V
Input
1.4V
0.8V
DOUT+
t
t
PLH
PHL
V
V
100Ω ±1%
Input
OD
100%
80%
Output
V
DOUT–
C = 10pF
L
(2 places)
OD(H)
0V
OD(L)
20%
0%
t
t
r
f
Figure4. TestCircuit, Timing, &VoltageDefinitionsfortheDifferentialOutputSignal
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition Rate
(PRR) = 15 Mpps, Pulse width = 10 ±0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
49.9Ω ±1% (2 places)
DOUT+
0.8V or 2V
+
1.2V
DOUT–
–
VODOUT+ VODOUT–
Input
2V
1.4V
0.8V
Input
t
t
PHZ
PZH
1.4V
V
ODOUT+
or
ODOUT–
1.3V
1.2V
V
t
t
PLZ
PZL
1.2V
V
V
ODOUT–
or
ODOUT+
1.1V
1V
Figure5.Enable&DisableTimeCircuit&Definitions
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition Rate
(PRR) = 0.5 Mpps, Pulse width = 500 ±10ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
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PI90LV211/PI90LVT211
1:6 Differential Clock
DistributionChip
CLKOUT–
CLKOUT+
tcycle n
tjit(cc) tcycle n
tcycle n+1
=
-
tcycle n+1
Figure6.Cycle-to-CycleJitter
CLKOUT–
CLKOUT+
tcycle n
CLKOUT–
CLKOUT+
1
fO
1
fO
t jit(per)
=
tcycle n
Figure 7. Period Jitter
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PI90LV211/PI90LVT211
1:6 Differential Clock
DistributionChip
GeneralDesciption
is characterized and tested with all of the outputs switching,
therefore the numbers in the data book are guaranteed only for this
situation. If all of the outputs of the PI90LV211 are not needed and
there is a desire to save power, the unused output pairs can be left
unterminated. Unterminatedoutputscaninfluencethepropagation
delay on adjacent pins by 15ps–20ps. Therefore, under these
conditions, this 15ps–20ps needs to be added to the overall skew
of the device. Pins which are separated by a package corner are not
considered adjacent pins in the context of propagation delay
influence. Therefore if all of the outputs on a single side of the
packageareterminated,thespecificationlimitsinthedatasheetwill
apply.
The PI90LV211isa 1:6fanouttreedesignedexplicitlyforlow-skew,
high-speed clock distribution. The device was targeted to work in
conjunction with the PI90LV14 device to provide another level of
flexibility in the design and implementation of clock distribution
trees. Theindividualsynchronousenablecontrolsandmultiplexed
clockinputsmakethedeviceidealasthefirstleveldistributionunit
in a distribution tree. The device provides the ability to distribute
a lower speed scan or test clock along with the high-speed system
clock to ease the design of system diagnostics and self test
procedures. The individual enables could be used to allow for the
disabling of individual cards on a backplane in fault tolerant
designs.
UsingtheEnablePins
HandlingOpenInputsandOutputs
Boththecommonenable(CEN)andtheindividualenables(ENx)are
synchronous to the CLK or SCLK input depending on which is
selected.Theactivelowsignalsareclockedintotheenableflipflops
on the negative edges of the PI90LV211 clock inputs. In this way,
thedeviceswillonlybedisabledwhentheoutputsarealreadyinthe
LOW state. The internal propagation delays are such that the delay
to the output through the distribution buffers is less than that
through the enable flip flops. This will ensure that the disabling of
thedevicewillnotsliceanytimeofftheclockpulse.Oninitialpower
up,theenableflipflopswillrandomlyattainastablestate;therefore
precautions should be taken on initial power up to ensure the
PI90LV211 is in the desired state.
Withthesimultaneousswitchingcharacteristicsandthetightskew
specificationsoftheP90LV211,thehandlingoftheunusedoutputs
becomes critical. To minimize the noise generated on the die
all outputs should be terminated in pairs, i.e. both the true and
compliment outputs should be terminated even if only one of the
outputs will be used in the system. With both complimentary pairs
terminated, the current in the V pins will remain essentially
CC
constant and thus inductance induced voltage glitches on V will
CC
not occur. V glitches will result in distorted output waveforms
CC
and degradations in the skew performance of the device.
The package parasitics of the 28-lead package cause the signals on
agivenpintobeinfluencedbysignalsonadjacentpins.PI90LV211
PI90LV14
PI90LV211
D0
PI90LV14
D5
Figure8.StandardPI90LV211LVDSApplication
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PI90LV211/PI90LVT211
1:6 Differential Clock
DistributionChip
PackagingMechanical:28-PinTSSOP(L)
28
.169
.177
4.3
4.5
0.09
0.20
.004
.008
1
.378
.386
0.45 .018
0.75 .030
9.6
9.8
.252
BSC
6.4
.047
1.20
Max
SEATING
PLANE
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
.002
.006
0.05
0.15
.0256
BSC
.007
.012
0.19
0.30
0.65
PackagingMechanical:28-PinQSOP(Q)
28
.008
0.20
MIN.
.008
.013
0.20
0.33
0.150
0.157
3.81
3.99
Guage Plane
0˚-6˚
.010
.016
.035
0.41
0.89
0.254
1
Detail A
.041
1.04
REF
.386 9.804
.394 10.009
.015 x 45˚
.033
REF
0.84
1.35 .053
1.75 .069
Detail A
SEATING
PLANE
0.178
0.254
.007
.010
0.41 .016
1.27 .050
0.101
0.254
.004
.010
.228
.244
5.79
6.19
.025
BSC
0.635
.008
.012
0.203
0.305
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
PS8535C
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PI90LV211/PI90LVT211
1:6 Differential Clock
DistributionChip
OrderingInformation
Ordering Code
PI90LV211L
PI90LV211LE
PI90LV211Q
PI90LV211QE
PI90LVT211L
PI90LVT211LE
PI90LVT211Q
PI90LVT211QE
Package Code
PackageType
28-pin173-milTSSOP
Pb-free&Green,28-pin173-milTSSOP
28-pin150-milQSOP
Pb-free&Green,28-pin150-milQSOP
28-pin173-milTSSOP
Pb-free&Green,28-pin173-milTSSOP
28-pin150-milQSOP
L
L
Q
Q
L
L
Q
Q
Pb-free&Green,28-pin150-milQSOP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
PS8535C
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