概述
数据手册PI90SD1636C 概述
SERDES Gigabit Ethernet Transceiver SERDES千兆以太网收发器
PI90SD1636C 数据手册
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PDF下载PI90SD1636C
SERDES Gigabit Ethernet Transceiver
Features
Description
• IEEE 802.3z Gigabit Ethernet Compliant
• Supports 1.25 Gbps Using NRZ Coding over uncompensated
twin coax cable
• Fully integrated CMOS IC
• Low Power Consumption
The PI90SD1636C is a single chip, Gigabit Ethernet transceiver.
It performs all the functions of the Physical Medium Attachment
(PMA) portion of the Physical layer, as specified by the IEEE
802.3zGigabitEthernetstandard. Thesefunctionsincludeparallel-
to-serial and serial-to-parallel conversion, clock generation, clock
data recovery, and word synchronization. In addition, an internal
loopback function is provided for system debugging.
• ESD rating >2000V (Human Body Model) or > 200V (Ma-
chine Model)
• 5-Volt Input Tolerance
The PI90SD1636C is ideal for Gigabit Ethernet, serial backplane
and proprietary point-to-point applications. The device sup-
ports 1000BASE-LX and 1000BASE-SX fiber-optic media, and
1000BASE-CX copper media.
• Pin-Compatible with Agilent HDMP1636A/HDMP- 1646A
and Vitesse VSC7123 transceivers (see Appendix A)
• Packaging (Pb-free & Green available):
- 64-pin LQFP (FC)
- 64-pin LQFP (FD)
The transmitter section of the PI90SD1636C accepts 10-bit wide
parallel TTL data and converts it to a high speed serial data stream.
The parallel data is encoded in 8b/10b format. This incoming
parallel data is latched into an input register, and synchronized
on the rising edge of the 125 MHz reference clock supplied by
the user. A phase locked loop (PLL) locks to the 125 MHz clock.
The clock is then multiplied by 10 to produce a 1.25 GHz serial
clock that is used to provide the high speed serial data output. The
output is sent through a Pseudo Emitter Coupled Logic (PECL)
driver. This output connects directly to a copper cable in the case
of 1000BASE-CX medium, or to a fiber optic module in the case
of 1000BASE-LX or 1000BASE SX fiber optic medium.
Applications
• Gigabit Ethernet
• Serial Backplane
• Proprietary point-to-point applicaitons
• Passive Optical Networks
The receiver section of the PI90SD1636C accepts a serial PECL-
compatible data stream at a 1.25 Gbps rate, recovers the original
10-bit wide parallel data format, and retimes the data. APLLlocks
onto the incoming serial data stream, and recovers the 1.25 GHz
high speed serial clock and data. This is accomplished by con-
tinually frequency locking onto the 125 MHz reference clock, and
by phase locking onto the incoming data stream. The serial data
is converted back to parallel data format. The ‘comma’ character
is used to establish byte alignment. Two 62.5 MHz clocks, 180
degrees out of phase, are recovered. These clocks are alternately
used to clock out the parallel data on the rising edge. This parallel
data is sent to the user in TTL-compatible form.
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Functional Block Diagram
EWRAP
10
10
DOUT+
Input Data
Latch
TX<9:0>
TX_CLK
Shift Registers
DOUT-
TX PLL Clock
Generator
62.5 MHz
62.5 MHz
RX_CLK<1>
RX_CLK<0>
÷
2
125 MHz
10
RX PLL Clock
Recovery
RX<9:0>
Output Latch
10
EN_CDET
COM_DET
10
FRAME
ENABLE
Shift
Registers
DIN+
DIN-
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Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND_ESD
TX<0>
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
2
COM_DET
GND_RXT
RX<0>
TX<1>
3
TX<2>
4
VCC_ESD
TX<3>
5
RX<1>
6
RX<2>
TX<4>
7
VCC_RXT
RX<3>
TX<5>
8
TX<6>
9
RX<4>
VCC_ESD
TX<7>
10
11
12
13
14
15
16
RX<5>
RX<6>
TX<8>
VCC_RXT
RX<7>
TX<9>
GND_ESD
GND_TXA
NC
RX<8>
RX<9>
GND_RXT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Table 1. I/O Type Definitions
Type
Definition
TTL_IN
TTL_OUT
HS_IN
HS_OUT
P
TTL Input
TTL Output
Hight-Speed Input
High-Speed Output
Power Ground
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Table 2. Pin Description
Name
Pin #
Type
Description
GND_ESD
VCC_ESD
1, 14
5, 10
P
Power and ground pairs for pad ESD structure.
TX<0>
TX<1>
TX<2>
TX<3>
TX<4>
TX<5>
TX<6>
TX<7>
TX<8>
TX<9>
2
3
4
6
7
8
9
11
12
13
0-bit parallel data input pins. This data should be 10b/8b encoded. The least
significant bit is TX<0> and is transmitted first.
TTL_IN
GND_TXA
VCC_TXA
15
18
P
Power and ground pair for TX PLL analog circuits.
No Connect
16, 17,27,
48, 49
NC
NC
Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial data
are internally wrapped from the transmitter serial data output back to the receiver
data input. Also, when asserted, DOUT± are held static at logic 1. When deasserted,
DOUT± and .DIN± are active.
EWRAP
19
TTL_IN
P
VCC_TXD
GND_TXD
20
21
Power and ground pair for TX digital circuits.
Reference clock and transmit byte clock. This is a 125 MHz system clock supplied
by the host system. On the positive edge of the clock, the input data, TX<9:0>, are
latched into the register. This clock is multiplied by 10 internally, to generate the
transmit serial bit clock.
TX_CLK
22
TTL_IN
VCC_RXD
GND_RXD
23 28,
25
P
Power and ground pair for digital circuits in the receiver portion.
Comma Detect Enable. This pin is active HIGH. When asserted, the internal byte
alignment function is turned on, to allow the clock to synchronize with the comma
character (0011111XXX). When de-asserted, the function is disabled and will not align
the clock and data. In this mode COM_DET is set to LOW.
EN_CDET
24
TTL_IN
Signal Detect. This pin is active HIGH. It indicates the loss of input signal on the
high-speed serial inputs, DIN±. SIG_DET is set to LOW when differential inputs are
less than 50 mV.
TTL_
OUT
SIG_DET
26
VCC_RX
GND_RX
29
32
P
Power and ground pair for the clock signal of the receiver portion.
Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals that are
recovered by the receiver section. The received bytes are alternately clocked by the
rising edges of these signals. The rising edge of RX_CLK<1> aligns with a comma
character when detected.
RX_CLK<1> 30
RX_CLK<0> 31
TTL_
OUT
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Table 2. Pin Description (Continued.)
Name
Pin#
Type
Description
GND_RXT
VCC_RXT
33 46,
37, 42
P
Power and ground pairs for ESD structure.
34
35
36
RX<9>
RX<8>
RX<7>
RX<6>
RX<5>
RX<4>
RX<3>
RX<2>
RX<1>
RX<0>
37
38
39
40
41
43
44
45
Received Parallel Data Output. RX<0> is the least significant bit and is
received first. When DIN± lose input data, all RX pins will be held HIGH.
TTL_OUT
Comma detect. This pin is active HIGH. When asserted, it indicates the
detection of comma character (0011111XXX). It is active only when EN_CEDT
is enabled.
COM_DET
47
TTL_OUT
VCC_RXF
GND_RXF
50
51
P
Power and ground pair for the front-end of the receiver section.
DIN-
52
54
HS_IN
High-speed serial data input. Serial data input is received when
DIN+
EWRAP is disabled.
VCC_RXESD
GND_RXESD
53,55
56
P
Power and ground pair for ESD structure.
VCC_RXA
GND_RXA
57, 59
58
P
Power and ground pair for analog circuits of the receiver section.
Power supply to line driver circuits. Ground supply is from pin 64.
VCC_TX_ECL 60
P
DOUT-
DOUT+
61
62
High-speed serial data output. These pins are active when EWRAP is disabled
and are held static at logic 1 when EWRAP is enable.
HS_OUT
VCC_TX_HS
GND_TX_HS
63
64
Power and ground pair for high-speed transmit logic in the parallel-to-serial
section.
P
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SERDES Gigabit Ethernet Transceiver
Functional Block Description
Input Data Latch
The input data latch block latches the 10-bit TTL input parallel byte, TX<9:0>, on the rising edge of the 125 MHz user-provided
TX_CLK into the holding registers.
Parallel-to-Serial Converter
The received 10-bit TTL parallel input byte is converted to serial PECL level data stream by the parallel-to-serial block, and is trans-
mitted differentially to the line driver block at 1.25 Gbps. The 8b/10b encoded data is transmitted sequentially with bit 0 being sent
first.
Clock Generator
The 125 MHz signal used for clocking the serial outputs is generated by the TX PLL block based on the user-provided TX_CLK.
This clock should have a ±100 ppm tolerance.
Internal Loopback
When EWRAP is set to a logic HIGH, the serial data stream generated by the transmitter is looped back to the receiver path, instead
of going out to the DOUT± pins. When in loopback mode, a static logic 1 is transmitted at the line driver (DOUT+ is HIGH and
DOUT- is LOW).
Signal Detect
Signal detect block is used to sense the serial input data stream at pins DIN±. If the serial input is lower than 50mV differentially, this
block deasserts SIG_DET and sets the output, RX<9:0>, to all logic ones. When the serial input at pins DIN± is greater than 50mV,
the signal is directed to the receive path.
Equalizer and Slicer
The signal received from the line (DIN± pins) is distorted by the cable bandwidth. In order to maintain a low bit-error rate, an equalizer
is used to compensate for the signal loss. The slicer recovers the differential low-level signal to a CMOS-level single-ended signal,
for clock recovery and data re-timing.
Clock Recovery
The serial input data stream contains both data and clock. The clock recovery block is used to extract both data and clocks from this
input. In addition to data, two clocks of 62.5 MHz are recovered.
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SERDES Gigabit Ethernet Transceiver
Table 3. Absolute Maximun Ratings
StressesabovethoselistedunderAbsolute
Units
Symbol
Parameter
Min.
-0.5
-0.7
2.0
Max.
Maximum Ratings may cause permanent
damage to the device. These ratings are
V
V
V
Supply voltage
5.0
CC
stress specifications only and correct
functional operation of the device at
TTL Input Voltage
V
+ 2.8
V
IN,TTL
IN,HS_IN
OUT,TTL
CC
High-Speed Input Voltage
TTL Output Source Current
Storage Temperature
V
CC
these or any other conditions above those
listed in the operational sections of the
specifications is not implied. Exposure
I
13
mA
T
stg
-65
0
+150
+150
to absolute maximum rating conditions
for extended periods may affect product
°C
T
Junction Operating Temperature
j
reliability.
o
o
Table 4. Guaranteed Operating Rates T = 0 C to +70 C, V = 3.15V to 3.45V
A
CC
Parallel Clock Rate (MHz)
Min. Max.
124.0 126.0
SerialBaud Rate (Mbaud)
Min.
Max.
1240
1260
Table 5. AC Electrical Characteristics T = 0°C to +70°C, V = 3.15V to 3.45V
A
CC
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
t
t
t
t
t
t
t
REFCLK Rise Time, 0.8 to 2.0 Volts
2.4
2.4
r,REFCLK
f,REFCLK
r,TTL_IN
REFCLK Fall Time, 2.0 to 0.8 Volts
Input TTL Rise Time, 0.8 to 2.0 Volts
2
2
ns
Input TTL Fall Time, 2.0 to 0.8 Volts
f,TTL_IN
Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load
Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load
HS_OUT Single-Ended (DOUT+) Rise Time
HS_OUT Single-Ended (DOUT+) Fall Time
HS_IN Input Peak-to-Peak Differential Voltage
1.5
1.1
225
200
1200
2.4
2.4
r,TTL_OUT
f,TTL_OUT
rs,HS_OUT
fs,HS_OUT
85
85
327
327
2000
ps
V
200
IP,HS_IN
mV
V
OP,HS_
(1)
HS_OUT Output Peak-to-Peak Differential Voltage
1200
1600
2000
OUT
Note:
1. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-
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SERDES Gigabit Ethernet Transceiver
Table 6. DC Electrical Characteristics T = 0°C to +70°C, V = 3.15V to 3.45V
A
CC
Symbol
Parameter
Min.
2
Typ.
Max.
5.5
Unit
V
V
V
V
TTL Input High Voltage Level, Guaranteed High Signal for All Inputs
TTL Input Low Voltage Level, Guaranteed Low Signal for All Inputs
IH,TTL
IL,TTL
OH,TTL
OL,TTL
IH,TTL
IL,TTL
0
0.8
V
TTL Output High Voltage Level, I = -12 mA
2.2
0
V
CC
OH
TTL Output Low Voltage Level, I = 12 mA
0.6
OL
I
I
I
Input High Current, V = V , V = 3.45 V
5
IN
CC
CC
μA
Input Low Current, V = 0V, V = 3.45 V
–5
IN
CC
[1,2]
Transceiver V Supply Current, TA = 25°C
220
mA
CC,TRX
CC
Notes:
1. Measurement Conditions: Tested sending 1250 MBd PRBS 27-1 sequence from a serial Bit Error Rate Tester (BERT) with DOUT± outputs
terminated with 150Ω resistors to GND.
2. Typical values are at VCC = 3.3 volts.
Table 7. Transceiver Reference Clock Requirements T = 0°C to +70°C, V = 3.15V to 3.45V
A
CC
Symbol
Parameter
Min.
Typ.
Max.
Unit
MHz
ppm
%
f
Nominal Frequency (for gigabit Ethernet Compliance)
Frequency Tolerance
125
F
tol
-100
40
+100
60
Symm
Symmetry (Duty Cycle)
Table 8. Transmitter Timing Characteristics T = 0°C to +70°C, V = 3.15V to 3.45V
A
CC
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
t
Setup Time to Rising Edge of TX_CLK
Hold Time to Rising Edge of TX_CLK
1.5
setup
1.0
ns
hold
3.5
4.4
[1]
t_txlat
Transmitter Latency
bits
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising
edge of the transmit by clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit
transmitted).
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SERDES Gigabit Ethernet Transceiver
1.4V
2.0V
TX_CLK
TX<9:0>
DATA
DATA
DATA
DATA
DATA
0.8V
tSETUP
tHOLD
Figure 3. Transmitter Section Timing
DATA BYTE A
DATA BYTE B
±
DOUT T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5
t_TXLAT
TX<9:0>
TX_CLK
DATA BYTE B
DATA BYTE C
1.4V
Figure 4. Transmitter Latency
Table 9. Receiver Timing Characteristics T = 0°C to +70°C, V = 3.15V to 3.45V
A
CC
Symbol
Parameter
Min.
Typ.
Max.
Unit
bits
μs
[1]
b_sync
f_lock
Bit Sync Time
2500
500
Frequency Lock at Powerup
t
t
t
t
Data Setup Before Rising Edge of RX_CLK
Data Hold After Rising Edge of RX_CLK
RX_CLK Duty Cycle
2.5
1.5
40
SETUP
HOLD
DUTY
A-B
ns
60
%
ns
RX_CLK Skew
7.5
8.5
22.4
28.0
ns
[2]
T_rxlat
Receiver Latency
bits
Notes:
1. This is the recovery for input phase jumps.
2. The receiver latency as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the
first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either RBC1 or
RBC0).
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tSETUP
tHOLD
1.4V
2.0V
RX_CLK<1>
RX<9:0>
K28.5
DATA
DATA
DATA
DATA
0.8V
2.0V
COM_DET
0.8V
1.4V
RX_CLK<0>
tA-B
Figure 5. Receiver Section Timing
DATA BYTE C
DATA BYTE D
±
DIN
R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
R2 R3 R4 R5
t_rxlat
RX<9:0>
DATA BYTE A
DATA BYTE D
1.4V
RX_CLK<1>/<0>
Figure 6. Receiver Latency
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SERDES Gigabit Ethernet Transceiver
Packaging Mechanical: 64-pin LQFP (FC)
.472 12.00 BSC
Square
.004
.008
.394
10.00 BSC
Square
0.09
0.20
GAUGE PLANE
0.45
0.75
.018
.030
1.00 REF
.039
1.60
Max.
.063
.004
0.10
.053
.057
Seating Plane
.019
0.50 BSC
.002
.006
0.17
0.27
.007
.010
1.35
1.45
0.05
0.15
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
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SERDES Gigabit Ethernet Transceiver
Packaging Mechanical: 64-pin LQFP (FD)
.630 16.00 BSC
Square
.004
.008
.551
14.00 BSC
Square
0.09
0.20
GAUGE PLANE
0.45
0.75
.018
.030
1.00 REF
.039
1.60
Max.
.063
.004
0.10
.053
.057
Seating Plane
.031
0.80 BSC
.002
.006
0.17
0.27
.007
.010
1.35
1.45
0.05
0.15
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
Ordering Information
Ordering Code
Package Code
Package Description
64-pin 10mm x10mm LQFP
PI90SD1636CFC
FC
FC
FD
FD
PI90SD1636CFCE
PI90SD1636CFD
Pb-free & Green, 64-pin 10mm x10mm LQFP
64-pin 14mm x14mm LQFP
PI90SD1636CFDE
Pb-free & Green, 64-pin 14mm x14mm LQFP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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SERDES Gigabit Ethernet Transceiver
Appendix A
Gigabit Ethernet Transceiver
Pin Cross Reference Guide
PI90SD1636C, VSC7123 and HDMP1636A/1646A
Summary:
Pericom Semiconductor’s PI90SD1636C is functionally pin compatible with Vitesse’s VSC7123 and Agilent’s HDMP-1636A/46A.
Minor differences exist amongst the parts regarding the use of certain pins that are used by the manufacturer for internal tests, as is
further clarified below. These differences will not affect plug compatibility during normal operations.
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SERDES Gigabit Ethernet Transceiver
Pericom
PI90SD1636C
GND_ESD
TX<0>
Vitesse
VSC7123
VSSD
T0
Agilent
HDMP1636A/46A
GND
Pin #
1
Comments
Connect to the ground plane.
10-bit parallel data input pins.
2
TX[0]
3
TX<1>
T1
TX[1]
4
TX<2>
T2
TX[2]
6
TX<3>
T3
TX[3]
7
TX<4>
T4
TX[4]
8
TX<5>
T5
TX[5]
9
TX<6>
T6
TX[6]
11
12
13
5
TX<7>
T7
TX[7]
TX<8>
T8
TX[8]
TX<9>
T9
TX[9]
VDD_ESD
VDD_ESD
GND_ESD
GND_TXA
NC
VDDD
VDDD
VSSD
VSSA
CAP0
VCC
Connect to 3.3V
10
14
15
16
VCC
Connect to 3.3V
GND
Connect to the ground plane.
Connect to the ground plane.
GND_TXA
TXCAP1
Pericom requires no external caps.
External capacitor will not affect performance
17
NC
CAP1
TX_CAP0
Pericom requires no external caps.
External capacitor will not affect performance
18
19
VDD_TXA
EWRAP
VDDA
VCC_TXA
LOOPEN
Connect to 3.3V
EWRAP
Loop-back Enable when HIGH. Set LOW for
normal operation
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD_TXD
GND_TXD
TX_CLK
VDDD
VSSD
VCC
GND
Connect to 3.3V
Connect to the ground plane
125MHz reference clock.
Connect to 3.3V
REFCLK
VDDD
ENCDET
VSSD
REFCLK
VCC
VDD_RXD
EN_CDET
GND_RXD
SIG_DET
NC
ENBYTSYNC
GND
Comma Detect Enable (Active HIGH)
Connect to the ground plane.
Signal Detect (Active HIGH)
NCTD0, No connect for normal operation.
Connect to 3.3V
SIGDET
(Note 1)
VDDD
VDDT
RCLKN
RCLK
SIG_DET
NC
VDD_RXD
VDD_RX
RX_CLK<1>
RX_CLK<0>
GND_RX
GND_RXT
VCC
VCC_RXTTL
RBC1
Connect to 3.3V
Receiver Byte Clock
RBC0
Receiver Byte Clock
VSST
GND_RXTTL
GND_RXTTL
Connect to the ground plane
Connect to the ground plane
VSST
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SERDES Gigabit Ethernet Transceiver
Pericom
Vitesse
Agilent
HDMP1636A/
46A
Pin #
PI90SD1636C
VSC7123
Comments
34
35
36
38
39
40
41
43
44
45
37
42
46
47
RX<9>
RX<8>
R9
R8
RX[9]
RX[8]
Received Parallel Data Output
RX<7>
R7
RX[7]
RX<6>
R6
RX[6]
RX<5>
R5
RX[5]
RX<4>
R4
RX[4]
RX<3>
R3
RX[3]
RX<2>
R2
RX[2]
RX<1>
R1
RX[1]
RX<0>
R0
RX[0]
VDD_RXT
VDD_RXT
GND_RXT
COM_DET
VDDT
VDDT
VSST
COMDET
VCC_RXTTL
VCC_RXTTL
GND_RXTTL
BYTSYNC
Connect to 3.3V
Connect to 3.3V
Connect to the ground plane
Comma Detect ( Byte Sync)
Pericom requires no external caps. External capaci-
tor will not affect performance
48
49
NC
NC
TDI
RXCAP0
RXCAP1
Pericom requires no external caps. External capaci-
tor will not affect performance
TCK
50
51
52
53
VDD_RXF
GND_RXF
DIN-
VDDD
VSSD
RX-
VCC_RXA
GND_RXA
-DIN
Connect to 3.3V
Connect to the ground plane
High-speed serial data input
VDD_RXESD
N/C
VCC
(Note 2)
RX+
Connect to 3.3V
54
55
56
57
58
59
60
61
62
63
64
DIN+
+DIN
VCC
High-speed serial data input
Connect to 3.3V
VDD_RXESD
GND_RXESD
VDD_RXA
GND_RXA
VDD_RXA
VDD_TX_ECL
DOUT-
TMS
TRSTN
VDDD
VSSD
VDDD
VDDP
TX-
GND
Connect to the ground plane
Connect to 3.3V
VCC
GND
Connect to the ground plane
Connect to 3.3V
VCC
VCC_TXECL
-DOUT
+DOUT
VCC_TXHS
GND_TXHS
Connect to 3.3V
High-speed serial data output
High-speed serial data output
Connect to 3.3V
DOUT+
TX+
VDD_TX_HS
GND_TX_HS
VDDP
VSSD
Connect to the ground plane
Notes:
1. For VSC7123, this pin is in high-impedance state in normal operation.
2. For VSC7123, this pin has no internal connection.
PS8922A
11/08/07
15
07-0253
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