PT7C4337WE [PERICOM]
Real-time Clock Module;
| 型号： | PT7C4337WE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Real-time Clock Module 时钟 光电二极管 外围集成电路 |
| 文件： | 总23页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PT7C4337
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Real-time Clock Module (I2C Bus)
Description
Features
The PT7C4337 serial real-time clock is a low-power
Using external 32.768kHz quartz crystal for
PT7C4337
clock/calendar with two programmable time-of-day
alarms and a programmable square-wave output.
Supports I2C-Bus's high speed mode (400 kHz)
Includes time (Hour/Minute/Second) and calendar
(Year/Month/Date/Day) counter functions (BCD
code)
Address and data are transferred serially via a 2-wire,
bidirectional bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year. The clock operates in either the
24-hour or 12-hour format with AM/PM indicator.
The device is fully accessible through the serial interface
while VCC is between 1.8V and 5.5V. I2C operation is
not guaranteed below 1.8V. Timekeeping operation is
maintained with VCC as low as 1.2V.
Programmable square wave output signal
Two Time-of-Day Alarms
Oscillator Stop Flag
Operating range: 1.8V to 5.5V
Timekeeping range: 1.2V to 1.8V
Table 1 shows the basic functions of PT7C4337. More
details are shown in section: overview of functions.
Table 1. Basic functions of PT7C4337
Item
Function
PT7C4337
Source
Crystal(32.768KHz)
External crystal
1
Oscillator
Oscillator enable/disable
Oscillator fail detect
12-hour
24-hour
Time
display
2
Time
Century bit
-
Time count chain enable/disable
Alarm interrupt output
3
4
5
Interrupt
2
Programmable square wave output (Hz)
Communication
2-wire I2C bus
1, 4.096k, 8.192k, 32.768k
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Real-time Clock Module (I2C Bus)
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Pin Assignment
PT7C4337
8
1 X1
VCC
7
6
5
2
3
4
X2
SQW/INTB
SCL
INTA
SDA
GND
Pin Description
Pin No.
Pin
Type
Description
Oscillator Circuit Input. Together with X1, 32.768kHz crystal is connected between them.
Or external clock input.
1
X1
I
Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between
them. When 32.768kHz external input, X2 must be float.
2
6
X2
O
I
SCL
Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface.
Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The
SDA pin is open-drain output and requires an external pull-up resistor.
5
3
7
SDA
I/O
O
Interrupt Output. When enabled, INTA is asserted low when the time matches the values
set in the alarm registers. This pin is an open-drain output and requires an external pull up
resistor.
INTA
SQW/I
NTB
Square-Wave/Interrupt Output. Programmable square-wave or interrupt output signal. It
is an open-drain output and requires an external pull up resistor.
O
8
4
VCC
GND
P
P
Power. Primary power for PT7C4337.
Ground.
No Connect. These pins are not connected internally, but must be grounded for proper
operation.
/
NC
Maximum Ratings
Note:
Stresses greater than those listed under
Storage Temperature ............................................................-65℃ to +150℃
Ambient Temperature with Power Applied ...........................-40℃ to +85℃
Supply Voltage to Ground Potential (VCC to GND)............... -0.3V to +6.5V
DC Input (AllOtherInputsexceptVcc&GND)...................................... -0.3Vto(Vcc+0.3V)
DC Output Voltage (SDA,/INTA,/INTBpins)........................................-0.3V to +6.5V
DC Output Current (FOUT)............................................... -0.3Vto(Vcc+0.3V)
Power Dissipation .............................................320mW(depend on package)
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
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Real-time Clock Module (I2C Bus)
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Operating Mode
The amount of current consumed by the PT7C4337 is determined, in part, by the I2C interface and oscillator operation. The
following table shows the relationship between the operating mode and the corresponding ICC parameter.
VCC
Operating Mode
Power
ICC Active (ICCA)
ICC Standby (ICCS
Timekeeping (ICCTOSC
Data Retention (ICCTDDR
I2C Interface Active
1.8V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
1.2V ≤ VCC ≤ 1.8V
1.2V ≤ VCC ≤ 1.8V
I2C Interface Inactive
)
I2C Interface Inactive
)
I2C Interface Inactive, Oscillator Disabled
)
Recommended Operating Conditions
Part No.
Sym.
Description
Min
1.8
Type
Max
5.5
Unit
V
VCC
3.3
VCC supply voltage
VCCT
VOSC
1.2
-
-
-
-
-
-
1.8
Oscillator start up voltage
Input high level
1.2
5.5
PT7C4337
SCL, SDA
0.7VCC
-
VCC+0.3
5.5
VIH
INTA, SQW/INTB
VIL
TA
Input low level
-0.3
-40
0.3VCC
85
Operating temperature
ºC
DC Electrical Characteristics
Unless otherwise specified, VCC = 1.8~5.5V, TA = -40 °C to +85 °C
Sym.
Item
Supply voltage
Pin
Condition
Full operation
Timekeeping (Note 5)
Min
Typ
Max Unit
VCC
1.8
1.2
1.2
-0.3
-
5.5
V
VCC
VCCT
-
1.8
VOSC Oscillator voltage
VCC
SCL
SCL
X1
-
5.5
V
V
VIL1 Low-level input voltage
VIH1 High-level input voltage
VIL2 Low-level input voltage
VIH2 High-level input voltage
-
0.3VCC
0.7VCC
-
VCC+0.3
-
-
0.53
-
V
X1
0.53
-
IOL
IIL
Low-level output current
Input leakage current
SDA, /INTA, /INTB
SCL
VOL = 0.4V
3
-
-
-
-
mA
A
A
-1
-1
1
1
IOZ
Output current when OFF
SDA, /INTA, /INTB
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Real-time Clock Module (I2C Bus)
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DC Electrical Characteristics
Sym.
Item
Pin
Condition
Min
Typ
Max Unit
Unless otherwise specified, VCC = 1.3~1.8V, TA = -40 °C to +85 °C
Timekeeping current
Data retention current
VCC
VCC
Note 2, 4, 5
Note 2,4,5,6
-
-
450
-
800
nA
ICCTOSC
ICCTDDR
160
Unless otherwise specified, VCC = 1.8~3.6V, TA = -40 °C to +85 °C
ICCA
ICCS
Active supply current
Standby current
VCC
VCC
Note 1, 5
-
-
-
100
A
1.0
Note 2, 3, 5
0.6
Unless otherwise specified, VCC = 3.6~5.5V, TA = -40 °C to +85 °C
ICCA
ICCS
Note:
Active supply current
Standby current
VCC
VCC
Note 1, 5
-
-
-
150
A
1.8
Note 2, 3, 5
1.0
1. SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC.
2. Specified with 2-wire bus inactive, VIL = 0.0V, VIH = VCC.
3. SQW enabled.
4. Specified with the SQW function disabled by setting INTCN = 1.
5. Using recommended crystal on X1 and X2.
6. Crystal oscillator is disabled.
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Real-time Clock Module (I2C Bus)
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Recommended Layout for Crystal
Note: The crystal, traces and crystal input pins
should be isolated from RF generating signals.
Built-in Capacitors Specifications and Recommended External Capacitors
Parameter
Symbol
CG
Typ
12
12
13
13
0
Unit
pF
pF
pF
pF
X1 to GND
X2 to GND
X1 to GND
X2 to GND
X1 to GND
X2 to GND
Build-in capacitors
CD
C1
C2
Recommended External capacitors for
crystal CL=12.5pF
C1
C2
pF
pF
Recommended External capacitors for
crystal CL=6pF
0
Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768KHz, C1 and C2 should
meet the equation as below:
Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL
Cpar is all parasitical capacitor between X1 and X2.
CL is crystal’s load capacitance.
Crystal Specifications
Parameter
Symbol
fO
ESR
CL
Min
Typ
32.768
-
Max
Unit
kHz
k
Nominal Frequency
Series Resistance
Load Capacitance
-
-
-
-
70
-
6/12.5
pF
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Real-time Clock Module (I2C Bus)
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AC Electrical Characteristics
Sym
VHM
VHL
Description
Rising and falling threshold voltage high
Rising and falling threshold voltage low
Value
0.8 VCC
0.2 VCC
Unit
V
V
Signal
VHM
VLM
tr
tf
Over the operating range
Symbol
Item
Min.
-
Typ.
Max.
Unit
kHz
s
fSCL
SCL clock frequency
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT1
tHD;DAT2
tSU;STO
tBUF
START condition set-up time
START condition hold time
0.6
0.6
200
35
0
-
-
s
ns
Data set-up time (RTC read/write)
Data hold time (RTC write)
Data hold time (RTC read)
-
-
ns
-
s
STOP condition setup time
Bus idle time between a START and STOP condition
When SCL = "L"
0.6
1.3
1.3
0.6
-
-
s
-
s
tLOW
tHIGH
tr
-
s
When SCL = "H"
-
s
Rise time for SCL and SDA
Fall time for SCL and SDA
Allowable spike time on bus
Capacitance load for each bus line
I/O Capacitance (SDA, SCL)
Oscillator Stop Flag (OSF) Delay
0.3
0.3
50
400
10
100
s
tf
-
s
ns
tSP*
-
CB
-
pF
pF
ms
CI/O
*
-
TOSF
-
* Note: only reference for design
tSU;STA
S
Sr
P
SCL
tLOW
tHIGH
tHD;STA
tSP
fSCL
tBUF
SDA
tSU;DAT
tHD;STA
tSU;STO
tHD;STA
tHD;DAT
tSU;STA
S
P
Start condition
Stop condition
Sr
Restart condition
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Real-time Clock Module (I2C Bus)
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Function Block
Alarm 1 Register
Comparator 1
(Sec, Min, Hour, Day/Date)
PT7C4337
Alarm 2 Register
Comparator 2
(Min, Hour, Day/Date)
X1
CG
32.768
kHz
Time Counter
(Sec,Min,Hour,Day,Date,Month,Year)
OSC
Counter Chain
CD
X2
Address
Decoder
Address
Register
Control Register
SCL
SDA
I /O
Interface
(I2C)
INTA
Interrupt Control
Square Wave Output Control
Shift Register
SQW/INTB
Oscillator Circuit
PT7C4337
The PT7C4337 uses an external 32.768 kHz crystal. Table2 specifies several crystal parameters for the external crystal. The
Block Diagram shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a
crystal with the specified characteristics.
Table2 Crystal Specifications
Parameter
Symbol
fO
ESR
CL
Min
Typ
32.768
-
Max
Unit
kHz
k
Nominal Frequency
Series Resistance
Load Capacitance
-
-
-
-
70
-
6/12.5
pF
Note: The crystal, traces, and crystal input pins should be isolated from RF generating signals.
Clock Accuracy
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive
load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal frequency drift caused by
temperature shifts creates additional error. External circuit noise coupled into the oscillator circuit can result in the clock running
fast. Figure 1 shows a typical PC board layout for isolating the crystal and oscillator from noise.
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Real-time Clock Module (I2C Bus)
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Function Description
Overview of Functions
Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year
that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.
Alarm function
This device has two alarm system (Alarm 1 and Alarm 2) that outputs interrupt signals from INTA or INTB to CPU when the date,
day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a
specified time. The alarm is be selectable between on and off for matching alarm or repeating alarm.
Programmable square wave output
A square wave output enable bit controls square wave output at pin 7. Frequencies are selectable: 1, 4.096k, 8.192k, 32.768k Hz.
Interface with CPU
Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data).
Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is
also open drain.
The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode.
Oscillator fail detect
When oscillator fail, PT7C4337 OSF bit will be set.
Oscillator enable/disable
Oscillator and time count chain can be enabled or disabled at the same time by /ETIME bit.
Registers
Allocation of registers
Register definition
Addr.
Function
(hex)*1
Bit 7
0
Bit 6
S40
Bit 5
S20
Bit 4
S10
Bit 3
S8
Bit 2
S4
Bit 1
S2
Bit 0
S1
00
Seconds (00-59)
Minutes (00-59)
Hours (00-23 / 01-12)
Days of the week (01-07)
Dates (01-31)
01
02
03
04
05
06
07
0
M40
12, /24
0
M20
M10
H10
0
M8
H8
0
M4
H4
M2
H2
M1
H1
H20 or
P, /A
0
0
0
W4
D4
W2
D2
W1
D1
0
0
D20
0
D10
MO10
Y10
S10
D8
MO8
Y8
S8
Months (01-12)
Century
Y80
A1M1*2
0
MO4
Y4
MO2
Y2
MO1
Y1
Years (00-99)
Y40
S40
Y20
S20
Alarm 1: Seconds
S4
S2
S1
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Real-time Clock Module (I2C Bus)
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08
09
Alarm 1: Minutes
Alarm 1: Hours
Alarm 1: Day, Date
Alarm 2: Minutes
Alarm 2: Hours
Alarm 2: Day, Date
Control
A1M2*2
A1M3*2
A1M4*2
A2M2*3
A2M3*3
A2M4*3
/ETIME*4
OSF*9
M40
M20
M10
H10
M8
H8
M4
H4
M2
H2
M1
H1
H20 or
P, /A
0,
12, /24
Day,
0,
0,
W4,
D4
W2,
D2
W1,
D1
0A
0B
0C
0D
0E
0F
/Date
D20
D10
D8
M40
M20
M10
H10
M8
H8
M4
H4
M2
H2
M1
H1
H20 or
P, /A
0,
12, /24
Day,
0,
0,
W4,
D4
W2,
D2
W1,
D1
/Date
D20
D10
D8
0
0
0
0
RS2*5
RS1*5
INTCN*6 A2IE*7
A1IE*7
Status
0
0
0
A2F*8
A1F*8
Caution points:
*1. PT7C4337 uses 8 bits for address. For excess 0FH address, PT7C4337 will not respond (no acknowledge signal was given).
*2. Alarm 1 mask bits. Select alarm repeated rate when an alarm occurs.
*3. Alarm 2 mask bits. Select alarm repeated rate when an alarm occurs.
*4. Oscillator and time count chain enable/disable bit.
*5. Square wave output frequency select.
*6. Interrupt output pin select bit.
*7. Alarm 1 and alarm 2 enable bits.
*8. Alarm 1 and alarm 2 flag bits.
*9. Oscillator stop flag.
*10. All bits marked with "0" are read-only bits. Their value when read is always "0".
Control and status register
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
0E
Control
/ETIME
0
0
0
0
0
RS2
1
RS1
1
INTCN
0
A2IE
0
A1IE
0
(default)
Status
OSF
1
0
0
0
0
0
0
0
0
0
0
A2F
A1F
0F
(default)
Undefined Undefined
Oscillator related bits
/ETIME
Enable oscillator and time count chain bit.
/ETIME
Data
Description
Default
0
1
Enable oscillator and time count chain.
Disable oscillator and time count chain.
Read / Write
OSF
Oscillator Stop Flag.
A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge
the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples
of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC is insufficient to support oscillation.
3) The /ETIME bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0.
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Square wave frequency selection bits
RS2, RS1
Square wave Rate Select. These bits control the frequency of the square-wave output when the square wave has been enabled.
RS2, RS1
Data
00
SQW output freq. (Hz)
1
01
4.096k
8.192k
32.768k
Read / Write
10
Default
11
Interrupt related bits
INTCN
Interrupt Output pin select bit. This bit controls the relationship between the two alarms and the interrupt output pins.
INTCN
Data
1
Description
A match between the timekeeping registers and the alarm 1 registers activates the INTA pin (if the
alarm 1 is enabled) and a match between the timekeeping registers and the alarm 2 registers activates
the SQW/INTB pin (if the alarm 2 is enabled).
Read /
Write
Default
A match between the timekeeping registers and either alarm 1 or alarm 2 registers activates
the INTA pin (if the alarms are enabled). In this configuration, a square wave is output on
the SQW/INTB pin.
0
A1IE
Alarm 1 Interrupt Enable.
Description
A1IE
Data
0
Default
The A1F bit does not initiate the INTA signal.
Read /
Write
1
Permits the alarm 1 flag (A1F) bit in the status register to assert INTA.
A1F
Alarm 1 Flag.
Description
A1F
Data
0
Default
Read / Write
The time do not match the alarm 1 registers.
Indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the INTA pin goes
low. A1F is cleared when written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
Read
1
A2IE
Alarm 2 Interrupt Enable.
A2IE
Data
Description
Default
0
The A2F bit does not initiate an interrupt signal.
Read /
Write
Permits the alarm 2 flag (A2F) bit in the status register to assert INTA (when INTCN = 0) or to assert
SQW/INTB (when INTCN = 1).
1
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A2F
Alarm 2 Flag.
A1F
Data
0
Description
Default
Read /
Write
The time do not match the alarm 2 registers.
Indicates that the time matched the alarm 1 registers. This flag can be used to generate an interrupt on
either INTA or SQW/INTB depending on the status of the INTCN bit. If the INTCN = 0 and A2F = 1
(and A2IE = 1), the INTA pin goes low. If the INTCN = 1 and A2F = 1 (and A2IE = 1), the
SQW/INTB pin goes low. A2F is cleared when written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Read
1
Time Counter
Time digit display (in BCD code):
Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to
12 a.m. or 23 to 00.
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Seconds
(default)
0
0
S40
S20
S10
S8
S4
S2
S1
00
01
02
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
M40 M20 M10 M8 M4 M2 M1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
12, /24 H20 or P,/A H10 H8 H4 H2 H1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Minutes
(default)
0
0
Hours
0
0
(default)
Note: Any registered imaginary time should be replaced with correct time, otherwise it will cause the clock counter malfunction.
12, /24 bit
This bit is used to select between 12-hour clock system and 24-hour clock system.
12, /24
Data
Description
0
1
24-hour system
12-hour system
Read / Write
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This bit is used to select between 12-hour clock operation and 24-hour clock operation.
12, /24
Description
Hours register
24-hour clock
12-hour clock
24-hour clock
12-hour clock
72 ( PM 12)
61 ( PM 01 )
62 ( PM 02 )
63 ( PM 03 )
64 ( PM 04 )
65 ( PM 05 )
66 ( PM 06 )
67 ( PM 07 )
68 ( PM 08 )
69 ( PM 09 )
70 ( PM 10 )
71 ( PM 11 )
00
01
02
03
04
05
06
07
08
09
10
11
52 ( AM 12 )
41 ( AM 01 )
42 ( AM 02 )
43 ( AM 03 )
44 ( AM 04 )
45 ( AM 05 )
46 ( AM 06 )
47 ( AM 07 )
48 ( AM 08 )
49 ( AM 09 )
50 ( AM 10 )
51 ( AM 11 )
12
13
14
15
16
17
18
19
20
21
22
23
0
24-hour time display
1
12-hour time display
* Be sure to select between 12-hour and 24-hour clock operation before writing the time data.
Days of the week Counter
The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that
correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on).
Illogical time and date entries result in undefined operation.
Addr.
Description
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
Days of the week
(default)
0
0
0
0
0
0
0
0
0
0
W4
W2
W1
03
Undefined Undefined Undefined
Calendar Counter
The data format is BCD format.
Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December).
Range from 1 to 30 (for April, June, September and November).
Range from 1 to 29 (for February in leap years).
Range from 1 to 28 (for February in ordinary years).
Carried to month digits when cycled to 1.
Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.
Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years.
Addr.
(hex)
Description
D7
D6
D5
D4
D3
D8
D2
D4
D1
D2
D0
D1
Dates
0
0
0
0
D20
D10
04
05
06
(default)
Undefined Undefined Undefined Undefined Undefined Undefined
Months
Century*1
Undefined
0
0
0
0
M10
Undefined Undefined Undefined Undefined Undefined
Y10 Y8 Y4 Y2 Y1
M8
M4
M2
M1
(default)
Years
Y80
Y40
Y20
(default)
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
*1: The century bit is toggled when the years register overflows from 99 to 00.
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Alarm Register
Alarm 1, Alarm 2 Register
Addr.
Description
D7
D6
D5
D4
D3
S8
D2
S4
D1
S2
D0
S1
Alarm 1: Seconds
(default)
A1M1*1
S40
S20
S10
07
08
09
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
A1M2*1
M40 M20 M10 M8 M4 M2 M1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
A1M3*1
12, /24 H20 or P,/A H10 H8 H4 H2 H1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Alarm 1: Minutes
(default)
Alarm 1: Hours
(default)
Day,
/Date*1
0,
0,
0,
W4,
D4
W2,
D2
W1,
D1
Alarm 1: Day, Date A1M4*1
0A
D20
D10
D8
(default)
Alarm 2: Minutes
(default)
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
A2M2*2
M40 M20 M10 M8 M4 M2 M1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
A2M3*2
12, /24 H20 or P,/A H10 H8 H4 H2 H1
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
0B
0C
Alarm 2: Hours
(default)
Day,
/Date*2
0,
0,
0,
W4,
D4
W2,
D2
W1,
D1
Alarm 2: Day, Date A2M4*2
0D
D20
D10
D8
(default)
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
*1 Note: Alarm mask bit, using to select Alarm 1 alarm rate.
*2 Note: Alarm mask bit, using to select Alarm 2 alarm rate.
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Alarm Function
Related register
Addr.
(hex)
Register definition
Function
Bit 7
0
Bit 6
S40
Bit 5
S20
Bit 4
Bit 3
Bit 2
S4
Bit 1
S2
Bit 0
S1
00
01
02
03
04
07
08
09
0A
0B
0C
0D
0E
0F
Seconds
Minutes
Hours
S10
S8
0
0
M40
12, /24
0
M20
M10
H10
0
M8
H8
0
M4
H4
W4
D4
S4
M2
H2
W2
D2
S2
M1
H1
W1
D1
S1
H20 or
A, /P
Days of the week
Dates
0
0
0
0
D20
S20
M20
D10
S10
M10
H10
D8
S8
M8
H8
Alarm 1: Seconds
Alarm 1: Minutes
Alarm 1: Hours
Alarm 1: Day, Date
Alarm 2: Minutes
Alarm 2: Hours
Alarm 2: Day, Date
Control
A1M1
A1M2
A1M3
A1M4
A2M2
A2M3
A2M4
/ETIME
OSF
S40
M40
12, /24
M4
H4
M2
H2
M1
H1
H20 or
A, /P
0,
Day,
0,
0,
W4,
D4
W2,
D2
W1,
D1
/Date
D20
D10
D8
M40
M20
M10
H10
M8
H8
M4
H4
M2
H2
M1
H1
H20 or
A, /P
0,
12, /24
Day,
0,
0,
W4,
D4
W2,
D2
W1,
D1
/Date
D20
D10
D8
0
0
0
0
RS2
0
RS1
0
INTCN
0
A2IE
A2F
A1IE
A1F
Status
Note: Alarm function does not support different hour system adopted in time and alarm register.
The PT7C4337 contains two time-of-day/date alarms. The alarms can be programmed (by the INTCN bit of the control register)
to operate in two different modes - each alarm can drive its own separate interrupt output or both alarms can drive a common
interrupt output. Bit 7 of each of the time-of-day/date alarm registers are mask bits.
When all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h ~ 04h
match the values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second,
minute, hour, day, or date. Table 2 and Table 3 shows the possible settings.
The Day, /Date bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 ~ 5 of that register
reflects the day of the week or the date of the month. If the bit is written to logic 0, the alarm is the result of a match with date of
the month. If the bit is written to logic 1, the alarm is the result of a match with day of the week.
When the PT7C4337 register values match alarm register settings, the corresponding alarm flag (A1F or A2F) bit is set to logic 1.
If the corresponding alarm interrupt enable (A1IE or A2IE) is also set to logic 1, the alarm condition activates one of the interrupt
output (INTA or SQW/INTB) signals. The match is tested on the once-per-second update of the time and date registers.
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Table 1. Alarm 1 Mask Bits
Day,
Alarm 1 register mask bits
Alarm rate
/Date
A1M4 A1M3 A1M2 A1M1
1
1
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
Alarm once per second
0
1
1
Alarm when seconds match
1
Alarm when minutes and seconds match
Alarm when hours, minutes, and seconds match
Alarm when date, hours, minutes, and seconds match
Alarm when day, hours, minutes, and seconds match
Ignored.
0
0
0
Others
Table 2. Alarm 2 Mask Bits
Day,
Alarm 2 register mask bits
Alarm rate
/Date
A2M4
A2M3
A2M2
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per minute (00 seconds of every minute)
Alarm when minutes match
0
1
Alarm when hours, minutes
Alarm when date, hours, and minutes match
Alarm when day, hours, and minutes match
Ignored.
Others
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I2C Bus Interface
Overview of I2C-BUS
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination
of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and
stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data
transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the
data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per
clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its
slave address matches the slave address in the received data.
System Configuration
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to
multiple devices.
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high
level when the bus is released (when communication is not being performed).
Fig 1. System configuration
Vcc
RP
RP
SDA
SCL
Master
MCU
Slave
RTC
Other Peripheral
Device
Note: When there is only one master, the MCU is ready for driving SCL to "H" and RP of SCL may not required.
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Starting and Stopping I2C Bus Communications
Fig 2. Starting and stopping on I2C bus
1) START condition, repeated START condition, and STOP condition
a) START condition
SDA level changes from high to low while SCL is at high level
b) STOP condition
SDA level changes from low to high while SCL is at high level
c) Repeated START condition (RESTART condition)
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in
which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
2) Data Transfers and Acknowledge Responses during I2C-BUS Communication
a) Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount
(bytes) of data that are transferred between the START condition and STOP condition.
The address auto increment function operates during both write and read operations.
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.
The receiver (receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
b) Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
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SCL from Master
8
9
2
1
SDA from transmitter
(sending side)
Release SDA
Low active
ACK signal
SDA from receiver
(receiving side)
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
Slave Address
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,
slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device
responds to this communication only when the specified slave address it has received matches its own slave address.
Slave addresses have a fixed length of 7 bits. See table for the details.
An R/W bit is added to each 7-bit slave address during 8-bit transfers.
Table
Slave address
bit 4
R / W bit
bit 0
Operation
Transfer data
bit 7
1
bit 6
1
bit 5
0
bit 3
0
bit 2
0
bit 1
0
Read
D1 h
D0 h
1 (= Read)
0 (= Write)
1
Write
I2C Bus’s Basic Transfer Format
S
Start indication
P
Stop indication
A
A
RTC Acknowledge
Sr
Restart indication
Master Acknowledge
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1) Write via I2C bus
Addr. setting
bit bit bit
bit bit bit bit bit
Slave address (7 bits)
S
A
A
A
P
write
0
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
Start
Stop
A
C
K
A
C
K
A
C
K
Slave address + write specification
Address
Specifies the write start address.
Write data
2) Read via I2C bus
a) Standard read
Slave address (7 bits)
Addr. setting
S
A
A
write
1
1
0
1
0
0
0
0
Start
A
C
K
A
C
K
Slave address + write specification
Address
Specifies the read start address.
bit bit bit bit bit bit bit bit
bit bit
bit bit bit bit bit bit
Slave address (7 bits)
Sr
A
A
/A
P
Read
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
1
Restart
A
C
K
A
C
K
Stop
N
O
Data read (1)
Data is read from the specified start
address and address auto increment.
Data read (2)
Address auto increment to set the
address for the next data to be read.
Slave address + read specification
A
C
K
b) Simplified read
bit bit bit bit bit bit bit bit
bit bit
bit bit bit bit bit bit
Slave address (7 bits)
S
A
A
/A
P
Read
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
1
Start
A
C
K
A
C
K
Stop
N
O
Data read (2)
Data read (1)
Slave address + read specification
Address register auto increment to set
the address for the next data to be
read.
Data is read from the address pointed
by the internal address register and
address auto increment.
A
C
K
Note:
1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred
during actual communications.
2. 49H, 4AH are used as test mode address. Customer should not use the addresses.
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Mechanical Information
WE (Lead free and Green SOIC-8)
Dimensions In Millimeters
Symbol
Min
1.350
0.100
1.350
0.330
0.170
4.700
3.800
Max
1.750
0.250
1.550
0.510
0.250
5.100
4.000
A
A1
A2
b
c
D
E
Note:
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MS-012E/AA
E1
e
5.800
6.200
1.27 BSC
L
θ
0.400
0°
1.270
8°
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UE(Lead free and Green MSOP-8)
Dimensions In Millimeters
Symbol
Min
0.82
0.02
0.75
0.25
0.09
2.90
2.90
4.75
Max
1.10
0.15
0.95
0.38
0.23
3.10
3.10
5.05
A
A1
A2
b
c
D
E
Note:
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MO-187E/BA
E1
e
0.65 BSC
L
0.40
0°
0.80
6°
θ
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LE (Lead free and Green 8-Pin TSSOP)
PKG. DIMENSIONS(MM)
SYMBOL
MIN
MAX
1.20
0.15
1.00
0.30
0.20
A
A1
A2
b
0.02
0.80
0.19
0.09
c
Note:
D
E
E1
e
2.90
4.30
6.25
3.10
4.50
6.55
1) Controlling dimensions in millimeters.
0.65 BSC
L
θ
0.50
1°
0.70
7°
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ZEE (Lead free and Green 8-Pin TDFN)
PKG. DIMENSIONS(MM)
SYMBOL
MIN.
0.700
0.000
MAX
0.800
0.500
A
A1
A3
D
0.203REF
1.924
2.924
1.400
1.400
2.076
3.076
1.600
1.600
E
D1
E1
k
0.200MIN
Note:
b
0.200
0.300
Ref: JEDEC MO-229
0.500TYP
e
L
0.224
0.376
Ordering Information
Part Number
PT7C4337WE
PT7C4337UE
PT7C4337ZEE
PT7C4337LE
Notes:
Package Code
Package
W
U
ZE
L
Lead free and Green 8-Pin SOIC
Lead free and Green 8-Pin MSOP
Lead free and Green 8-Pin TDFN
Lead free and Green 8-Pin TSSOP
E = Pb-free or Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
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相关型号：
PT7C433833UE
Real Time Clock, Non-Volatile, 1 Timer(s), CMOS, PDSO8, GREEN, MO-187E/BA, MSOP-8
PERICOM
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