SEL3934AA-FREQ(T) [PERICOM]

PECL Output Clock Oscillator, 19.44MHz Min, 200MHz Max,;


型号：	SEL3934AA-FREQ(T)
厂家：	PERICOM SEMICONDUCTOR CORPORATION
描述：	PECL Output Clock Oscillator, 19.44MHz Min, 200MHz Max, 机械振荡器
文件：	总2页 (文件大小：1431K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SaRonix

Crystal Clock Oscillator

3.3V, PECL, FR4

SEL393x Series

Technical Data

Frequency Range:

19.44 MHz to 200 MHz

Frequency Stability:

20, 25, 50 or 100 ppm over all conditionsꢀ calibration tolerance,

operating temperature, rated input (supply) voltage, load, *aging,

shock and vibration.

*Aging:

30 days (guaranteed long-term aging available)

Temperature Range:

Operatingꢀ

Storageꢀ

0 to +70°C or -40 to +85°C

-55 to +125°C

Supply Voltage (V ):

+3.3V 5ꢁ PECL

Supply Current:

Output Drive:

60mA typ (70mA max) terminated as specified

ACTUAL SIZE

Symmetryꢀ

Rise & Fall Timesꢀ

Logic 0ꢀ

45/55ꢁ max @ V

or Complementary Outputs Crossing

350ps typ, 550ps max, 20ꢁ to 80ꢁ of waveform

≤ V

≥ V

-1.595V (-40 to 85°C )

-1.02V (0 to +70°C), V

Description

Logic 1ꢀ

-1.08V (-40 to 85°C)

Loadꢀ

50Ω to V

-2V (output requires termination)

An FR4 SMD, LVPECL crystal oscilla-

tor for 3.3Volt operation. This oscillator

features a wide array of pad connection

options (see part number builder), tight

stabilityandexcellentjitterperformance.

RMS Period Jitterꢀ

RMS Phase Jitterꢀ

Total Jitterꢀ

5ps (1-sigma) max, accumulated jitter in 20,000 adjacent periods

1ps (1-sigma) max, phase jitter in 12kHz to 40MHz Freq. Band

30ps peak-to-peak max total jitter in 100,000 periods

Output Enable/Disable (n/a for SEL3930):

Output Enable Voltageꢀ

Disable Voltageꢀ

-1.475V or open

-1.165V (Q output disabled to a fixed level of Logic 0)

≤

≥

Applications & Features

Mechanical:

• SONET/SDH/DWDM

• ATM

Shockꢀ

Solderabilityꢀ

MIL-STD-883, Method 2002, Condition B

MIL-STD-883, Method 2003

Terminal Strengthꢀ

Vibrationꢀ

Resistance to Soldering Heatꢀ

Solvent Resistanceꢀ

MIL-STD-883, Method 2004, Condition D

MIL-STD-883, Method 2007, Condition A

MIL-STD-202, Method 210, Condition I or J

MIL-STD-202, Method 215

• Fibre Channel

• Gigabit Ethernet and 10GigE routers &

switches

• 3.3V PECL (LVPECL) capability

• Frequencyrangefrom19.44to200MHz

• Economical and rugged FR4 package

• Designedforstandardreflowandwash-

ing techniques

• Available on tape & reel; 16mm tape,

500pcs per reel

• Replaces more costly SEL36/SEL37

series with comparable layout and per-

formance

• See SEL481x Series for frequencies

≥200MHz

• SeeSEL381xSeriesforsmallerceram-

ic 5x7mm package designed for optical

NICs

Environmental:

Thermal Shockꢀ

Moisture Resistanceꢀ

MIL-STD-883, Method 1011, Condition A

MIL-STD-833, Method 1004

Part Numbering Guide

SEL39 3 0 B - 155.5200 (T)

Packing Method

Series

(T) = Tape & Reel

full reel increments only

Blank = Bulk

SaRonix, LVPECL FR4SO20

+3.3V PECL

Frequency

Stability

Connection Options

AA = 20 ppm, 0 to +ꢀ0ꢁC

A = 25 ppm, 0 to +ꢀ0ꢁC

B = 50 ppm, 0 to +ꢀ0ꢁC

E = 50 ppm, ꢂ40 to +ꢃ5ꢁC

F = 100 ppm, ꢂ40 to +ꢃ5ꢁC

Pad: 1 /

• SeeSDS3811Seriesforsmallerceram-

ic 5x7mm package designed for optical

NICs with new LVDS capability

0 = OUT

OUT

1 = EN

OUT

2 = OUT EN

3 = OUT N/C

4 = EN N/C

5 = N/C EN

OUT N/C

OUT EN

OUT OUT

DS-227 REV B

SaRonix

www.pericom.com/saronix

SaRonix

Crystal Clock Oscillator

3.3V, PECL, FR4

SEL393x Series

Technical Data

Package Details

Test Circuit*

14.0

.551

POSITIVE SUPPLY (LVPECL)

9.0

.354

Ω

INTERNAL SCOPE

+2V

TERMINATION TO GND

Ω INTERNAL SCOPE

5.7

.224

OSCILLATOR

TERMINATION TO GND

ENABLE/DISABLE

(SEL3934)

5.08

.200

Pad 1

Pad 3

1.78

.070

N/C

(no connect SEL3934)

-1.3V

Pad 2

5.0

.196

Pad 5

1.78

.070

*Test circuit shown for SEL3934 configuration only. Test circuits for other configurations as per

specified pad connections.

1.39

.055

Pad 6

Pad 4

Output Waveform

Pad Functions: See Part Numbering Guide for pad

functions. Configurations include either four (4) or six

(6) pads.

Complementary

Logic 1

80%

Min

Marking Format

Outputs

Crossing

YY WW X

Country of Origin

Week of Mfg.

Year of Mfg.

SARONIX

20%

MHz

FREQUENCY

Logic 0

Max

Denotes

Pad 1

PART NUMBER

SYMMETRY

45% Min, 55% Max

Exact location of items may vary

Solder Reflow Guide

Recommended Land Pattern

1.65

065

Reflow 235 5ꢀC

Cooling

250

4ꢀC/sec max

200

150

Preheat 183 10ꢀC

7.2

.284

4ꢀC/sec max

2.54

.100

5.08

.200

Time

1 – 2 minutes

5 sec min

10 sec max

**External high frequency power supply decoupling required.

Scale: None (Dimensions in

)

inches

All specifications are subject to change without notice.

DS-227 REV B

SaRonix

www.pericom.com/saronix

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