74ABT126D-602 [NXP]

Quad buffer; 3-state; 四缓冲器;三态
74ABT126D-602
型号: 74ABT126D-602
厂家: NXP    NXP
描述:

Quad buffer; 3-state
四缓冲器;三态

文件: 总15页 (文件大小:91K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
74ABT126  
Quad buffer; 3-state  
Rev. 04 — 17 February 2005  
Product data sheet  
1. General description  
The 74ABT126 high-performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT126 device is a quad buffer that is ideal for driving bus lines. The device  
features four output enable inputs (nOE each controlling one of the 3-state outputs (nY).  
2. Features  
Quad bus interface  
3-state buffers  
Live insertion and extraction permitted  
Output capability: +64 mA and 32 mA  
Inputs are disabled during 3-state mode  
Power-up 3-state  
Latch-up protection:  
JESD78: exceeds 500 mA  
ESD protection:  
MIL STD 883 method 3015: exceeds 2000 V  
Machine model: exceeds 200 V  
3. Quick reference data  
Table 1:  
Quick reference data  
Tamb = 25 °C; GND = 0 V.  
Symbol Parameter  
Conditions  
Min  
Typ  
2.9  
3.0  
4
Max Unit  
tPLH  
tPHL  
CI  
propagation delay nA to nY CL = 50 pF; VCC = 5 V  
propagation delay nA to nY CL = 50 pF; VCC = 5 V  
-
-
-
-
-
-
-
-
ns  
ns  
pF  
pF  
input capacitance  
output capacitance  
VI = 0 V or VCC  
CO  
outputs disabled;  
VO = 0 V or VCC  
7
ICC  
quiescent supply current  
outputs 3-state;  
-
65  
-
µA  
VCC = 5.5 V  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
4. Ordering information  
Table 2:  
Type number Package  
Temperature range  
40 °C to +85 °C  
Ordering information  
Name  
Description  
Version  
74ABT126D  
SO14  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
74ABT126DB 40 °C to +85 °C  
74ABT126PW 40 °C to +85 °C  
SSOP14  
plastic shrink small outline package; 14 leads;  
body width 5.3 mm  
SOT337-1  
SOT402-1  
TSSOP14 plastic thin small outline package; 14 leads;  
body width 4.4 mm  
5. Functional diagram  
2
2
1
5
4
9
1A  
1Y  
2Y  
3Y  
3
6
8
1
3
1
5
1OE  
2A  
EN1  
6
8
4
2OE  
3A  
9
10  
12  
13  
10 3OE  
12 4A  
4Y 11  
11  
13 4OE  
001aac483  
001aac482  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
6. Pinning information  
6.1 Pinning  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
V
CC  
4OE  
4A  
1Y  
2OE  
2A  
126  
4Y  
3OE  
3A  
2Y  
8
GND  
3Y  
001aac484  
Fig 3. Pin configuration  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
2 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
6.2 Pin description  
Table 3:  
Symbol  
1OE  
1A  
Pin description  
Pin  
1
Description  
1 output enable input  
1 data input  
2
1Y  
3
1 data output  
2OE  
2A  
4
2 output enable input  
2 data input  
5
2Y  
6
2 data output  
GND  
3Y  
7
ground (0 V)  
8
3 data output  
3A  
9
3 data input  
3OE  
4Y  
10  
11  
12  
13  
14  
3 output enable input  
4 data output  
4A  
4 data input  
4OE  
VCC  
4 output enable input  
supply voltage  
7. Functional description  
7.1 Function table  
Table 4:  
Function table[1]  
Input  
nOE  
H
Output  
nA  
L
nY  
L
H
H
H
Z
L
X
[1] H = HIGH voltage level;  
L = LOW voltage level;  
X = don’t care;  
Z = high-impedance OFF-state.  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
3 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
8. Limiting values  
Table 5:  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to  
GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
0.5  
1.2  
0.5  
Max  
+7.0  
+7.0  
+5.5  
Unit  
V
VCC  
VI  
supply voltage  
input voltage  
output voltage  
[1]  
[1]  
V
VO  
output in OFF-state or  
HIGH-state  
V
IIK  
input diode current  
output diode current  
output current  
VI < 0 V  
-
18  
50  
128  
150  
+150  
mA  
mA  
mA  
°C  
IOK  
IO  
VO < 0 V  
-
output in LOW-state  
-
[2]  
Tj  
junction temperature  
storage temperature  
-
Tstg  
65  
°C  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal  
environment can create junction temperatures which are detrimental to reliability.  
9. Recommended operating conditions  
Table 6:  
Recommended operating conditions  
Symbol Parameter  
Conditions  
Min  
4.5  
0
Typ  
Max  
5.5  
VCC  
-
Unit  
V
VCC  
VI  
supply voltage  
-
-
-
-
-
-
-
-
input voltage  
V
VIH  
HIGH-level input voltage  
LOW-level input voltage  
HIGH-level output current  
LOW-level output current  
input transition rise or fall rate  
ambient temperature  
2.0  
-
V
VIL  
0.8  
32  
64  
V
IOH  
-
mA  
mA  
ns/V  
°C  
IOL  
-
t/V  
Tamb  
0
10  
in free air  
40  
+85  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
4 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
10. Static characteristics  
Table 7:  
Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ  
Max Unit  
Tamb = 25 °C  
VIK  
input clamp voltage  
VCC = 4.5 V; IIK = 18 mA  
VCC = 4.5 V; VI = VIL or VIH  
IOH = 3 mA  
-
0.9 1.2  
V
VOH  
HIGH-level output voltage  
2.5  
2.0  
2.9  
2.4  
-
-
V
V
IOH = 32 mA  
VCC = 5.0 V; VI = VIL or VIH  
IOH = 3 mA  
3.0  
3.4  
-
V
V
VOL  
LOW-level output voltage  
VCC = 4.5 V; VI = VIL or VIH  
IOL = 64mA  
-
-
-
-
0.35 0.55  
ILI  
input leakage current  
VCC = 5.5 V; VI = GND or 5.5 V  
VCC = 0 V; VO or VI 4.5 V  
VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC  
±0.01 ±1.0 µA  
±5.0 ±100 µA  
IOFF  
power-off leakage current  
[1]  
IPU, IPD power-up or power-down  
down 3-state output current  
;
±5.0 ±50  
µA  
VOE = don’t care  
IOZ  
3-state output current  
VCC = 5.5 V; VI = VIL or VIH  
output HIGH-state at VO = 2.7 V  
output LOW-state at VO = 0.5 V  
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC  
-
-
-
1.0  
1.0 50  
5.0 50  
50  
µA  
µA  
µA  
ICEX  
output HIGH-state leakage  
current  
[2]  
IO  
output current  
VCC = 5.5 V; VO = 2.5 V  
VCC = 5.5 V; VI = GND or VCC  
outputs HIGH-state  
50  
100 180 mA  
ICC  
quiescent supply current  
-
-
-
65  
12  
65  
250  
15  
µA  
mA  
µA  
outputs LOW-state  
outputs 3-state  
250  
ICC  
additional supply current  
per data input pin  
[3]  
[3]  
one data input at 3.4 V and other inputs at  
VCC or GND; VCC = 5.5 V  
outputs enabled  
outputs 3-state  
-
-
0.5  
50  
1.5  
mA  
250  
µA  
per enable input pin  
one enable input at 3.4 V and other inputs at  
VCC or GND; VCC = 5.5 V  
outputs 3-state  
-
-
-
0.5  
4
1.5  
mA  
pF  
pF  
CI  
input capacitance  
output capacitance  
VI = 0 V or VCC  
-
-
CO  
outputs disabled; VO = 0 V or VCC  
7
Tamb = 40 °C to +85 °C  
VIK  
input clamp voltage  
VCC = 4.5 V; IIK = 18 mA  
-
-
1.2  
V
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
5 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
Table 7:  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
VOH HIGH-level output voltage  
Conditions  
Min  
Typ  
Max Unit  
VCC = 4.5 V; VI = VIL or VIH  
IOH = 3 mA  
2.5  
2.0  
-
-
-
-
V
V
IOH = 32 mA  
VCC = 5.0 V; VI = VIL or VIH  
IOH = 3 mA  
3.0  
-
-
V
V
VOL  
LOW-level output voltage  
VCC = 4.5 V; VI = VIL or VIH  
IOL = 64 mA  
-
-
-
-
-
-
-
-
0.55  
ILI  
input leakage current  
VCC = 5.5 V; VI = GND or 5.5 V  
VCC = 0.0 V; VO or VI 4.5 V  
VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC  
±1.0 µA  
±100 µA  
IOFF  
power-off leakage current  
[1]  
IPU, IPD power-up or power-down  
down 3-state output current  
;
±50  
µA  
VnOE = don’t care  
IOZ  
3-state output current  
VCC = 5.5 V; VI = VIL or VIH  
output HIGH-state at VO = 2.7 V  
output LOW-state at VO = 0.5 V  
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC  
-
-
-
-
-
-
50  
µA  
µA  
µA  
50  
50  
ICEX  
output HIGH-state leakage  
current  
[2]  
IO  
output current  
VCC = 5.5 V; VO = 2.5 V  
VCC = 5.5 V; VI = GND or VCC  
outputs HIGH-state  
50  
-
180 mA  
ICC  
quiescent supply current  
-
-
-
-
-
-
250  
15  
µA  
mA  
µA  
outputs LOW-state  
outputs 3-state  
250  
ICC  
additional supply current  
per data input pin  
[3]  
[3]  
one data input at 3.4 V and other inputs at  
VCC or GND; VCC = 5.5 V  
outputs enabled  
outputs 3-state  
-
-
-
-
1.5  
mA  
250  
µA  
per enable input pin  
one enable input at 3.4 V and other inputs at  
VCC or GND; VCC = 5.5 V  
outputs 3-state  
-
-
1.5  
mA  
[1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 %  
a transition time of up to 100 µs is permitted.  
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
[3] This is the increase in supply current for each input at 3.4 V.  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
6 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
11. Dynamic characteristics  
Table 8:  
Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max Unit  
Tamb = 25 °C; VCC = 5.0 V  
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
propagation delay nA to nY  
see Figure 4  
see Figure 4  
see Figure 5  
see Figure 5  
1.0  
1.0  
1.5  
1.9  
1.0  
1.0  
2.9  
3.0  
3.2  
4.4  
4.2  
2.9  
4.2  
4.3  
5.8  
5.9  
5.2  
4.9  
ns  
ns  
ns  
ns  
ns  
ns  
propagation delay nA to nY  
output enable time to HIGH-level  
output enable time to LOW-level  
output disable time from HIGH-level see Figure 5  
output disable time from LOW-level see Figure 5  
Tamb = 40 °C to +85 °C; VCC = 5.0 V ± 0.5 V  
tPLH  
tPHL  
tPZH  
tPZL  
tPHZ  
tPLZ  
propagation delay nA to nY  
propagation delay nA to nY  
output enable time to HIGH-level  
output enable time to LOW-level  
see Figure 4  
see Figure 4  
see Figure 5  
see Figure 5  
1.0  
1.0  
1.5  
1.9  
1.0  
1.0  
-
-
-
-
-
-
4.4  
4.6  
6.5  
6.5  
5.8  
5.5  
ns  
ns  
ns  
ns  
ns  
ns  
output disable time from HIGH-level see Figure 5  
output disable time from LOW-level see Figure 5  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
7 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
12. Waveforms  
V
I
nA input  
V
M
V
M
GND  
t
t
PLH  
PHL  
V
OH  
V
V
M
nY output  
M
V
OL  
mnb072  
VM = 1.5 V.  
VOL and VOH are typical voltage output drop that occur with the output load.  
Fig 4. Propagation delay input (nA) to output (nY)  
V
I
nOE input  
nY output  
nY output  
V
M
t
GND  
3.5 V  
t
PZL  
PLZ  
V
V
M
M
V
+ 0.3 V  
OL  
V
OL  
t
t
PHZ  
PZH  
V
OH  
V
0.3 V  
OH  
0 V  
001aac486  
VM = 1.5 V.  
VOL and VOH are typical voltage output drop that occur with the output load.  
Fig 5. Enable and disable times of 3-state outputs  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
8 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
t
W
V
I
90 %  
90 %  
negative  
pulse  
V
V
M
M
10 %  
0 V  
t
(t )  
f
t
(t )  
TLH r  
THL  
t
(t )  
t
(t )  
THL f  
TLH  
r
V
I
90 %  
positive  
pulse  
V
M
V
M
10 %  
10 %  
0 V  
t
W
001aac221  
VM = 1.5 V.  
a. Input pulse definition  
V
EXT  
V
CC  
R
L
V
I
V
O
PULSE  
GENERATOR  
D.U.T.  
C
L
R
L
R
T
mna616  
Test data is given in Table 9.  
Definitions test circuit:  
RL = Load resistor.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
VEXT = Test voltage for switching times.  
b. Test circuit  
Fig 6. Load circuitry for switching times  
Table 9:  
Input  
VI  
Test data  
Load  
CL  
VEXT  
fi  
1 MHz  
tW  
tr, tf  
RL  
tPHZ, tPZH tPLZ, tPZL  
tPLH, tPHL  
3.0 V  
500 ns  
2.5 ns 50 pF  
500 open  
7.0 V  
open  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
9 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
13. Package outline  
SO14: plastic small outline package; 14 leads; body width 3.9 mm  
SOT108-1  
D
E
A
X
c
y
H
v
M
A
E
Z
8
14  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
7
e
detail X  
w
M
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
8.75  
8.55  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.75  
1.27  
0.05  
1.05  
0.25  
0.01  
0.25  
0.1  
0.25  
0.01  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.35  
0.014 0.0075 0.34  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches  
0.041  
0.01 0.004  
0.069  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT108-1  
076E06  
MS-012  
Fig 7. Package outline SOT108-1 (SO14)  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
10 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm  
SOT337-1  
D
E
A
X
c
y
H
v
M
A
E
Z
8
14  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
7
1
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
6.4  
6.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
1.4  
0.9  
mm  
2
0.25  
0.65  
1.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT337-1  
MO-150  
Fig 8. Package outline SOT337-1 (SSOP14)  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
11 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm  
SOT402-1  
D
E
A
X
c
y
H
v
M
A
E
Z
8
14  
Q
(A )  
3
A
2
A
A
1
pin 1 index  
θ
L
p
L
1
7
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
5.1  
4.9  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.72  
0.38  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT402-1  
MO-153  
Fig 9. Package outline SOT402-1 (TSSOP14)  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
12 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
14. Revision history  
Table 10: Revision history  
Document ID  
74ABT126_4  
Modifications:  
Release date Data sheet status  
20050217 Product data sheet  
Change notice Doc. number  
Supersedes  
-
9397 750 14597 74ABT126_3  
The format of this data sheet has been redesigned to comply with the new presentation and  
information standard of Philips Semiconductors.  
Section 2 “Features”: modified ‘JEDEC Std 17’ into ‘JESD78’.  
Table 8 “Dynamic characteristics”: changed min value of tPZH from 1.9 ns into 1.5 ns for both  
conditions VCC = 5.0 V at Tamb = 25 °C and VCC = 5.0 V ± 0.5 V at Tamb = 40 °C to +85 °C.  
74ABT126_3  
74ABT126_2  
74ABT126_1  
20021213  
19980116  
-
Product specification  
-
-
-
9397 750 10856 74ABT126_2  
9397 750 03462 74ABT126_1  
Product specification  
-
-
-
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
13 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
15. Data sheet status  
Level Data sheet status[1] Product status[2] [3]  
Definition  
I
Objective data  
Development  
This data sheet contains data from the objective specification for product development. Philips  
Semiconductors reserves the right to change the specification in any manner without notice.  
II  
Preliminary data  
Qualification  
This data sheet contains data from the preliminary specification. Supplementary data will be published  
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in  
order to improve the design and supply the best possible product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips Semiconductors reserves the  
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant  
changes will be communicated via a Customer Product/Process Change Notification (CPCN).  
[1]  
[2]  
Please consult the most recently issued data sheet before initiating or completing a design.  
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at  
URL http://www.semiconductors.philips.com.  
[3]  
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
16. Definitions  
17. Disclaimers  
Short-form specification The data in a short-form specification is  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Life support — These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Right to make changes — Philips Semiconductors reserves the right to  
make changes in the products - including circuits, standard cells, and/or  
software - described or contained herein in order to improve design and/or  
performance. When the product is in full production (status ‘Production’),  
relevant changes will be communicated via a Customer Product/Process  
Change Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are  
free from patent, copyright, or mask work right infringement, unless otherwise  
specified.  
Application information Applications that are described herein for any  
of these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
18. Contact information  
For additional information, please visit: http://www.semiconductors.philips.com  
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com  
9397 750 14597  
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.  
Product data sheet  
Rev. 04 — 17 February 2005  
14 of 15  
74ABT126  
Philips Semiconductors  
Quad buffer; 3-state  
19. Contents  
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
7.1  
8
Functional description . . . . . . . . . . . . . . . . . . . 3  
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 4  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Contact information . . . . . . . . . . . . . . . . . . . . 14  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
© Koninklijke Philips Electronics N.V. 2005  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner. The information presented in this document does  
not form part of any quotation or contract, is believed to be accurate and reliable and may  
be changed without notice. No liability will be accepted by the publisher for any  
consequence of its use. Publication thereof does not convey nor imply any license under  
patent- or other industrial or intellectual property rights.  
Date of release: 17 February 2005  
Document number: 9397 750 14597  
Published in The Netherlands  

相关型号:

74ABT126D-T

4-Bit Buffer/Driver
ETC

74ABT126DB

Quad buffer 3-State
NXP

74ABT126DB-T

4-Bit Buffer/Driver
ETC

74ABT126N

Quad buffer 3-State
NXP

74ABT126PW

Quad buffer 3-State
NXP

74ABT126PW

Quad buffer; 3-stateProduction
NEXPERIA

74ABT126PW-T

4-Bit Buffer/Driver
ETC

74ABT126PWDH

Quad buffer 3-State
NXP

74ABT126PWDH-T

暂无描述
NXP

74ABT161543

16-bit latched transceiver with dual enable and master reset 3-State
NXP

74ABT161543DG-T

IC ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver
NXP

74ABT161543DGG

16-bit latched transceiver with dual enable and master reset 3-State
NXP