74ABT845PW [NXP]
8-bit bus interface latch with set and reset 3-State; 8位总线接口与锁存置位和复位三态
| 型号： | 74ABT845PW |
| 厂家： | 
NXP |
| 描述： | 8-bit bus interface latch with set and reset 3-State |
| 文件： | 总7页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
8-bit bus interface latch with set and reset
(3-State)
74ABT845
FEATURES
• High speed parallel latches
DESCRIPTION
The 74ABT845 consists of eight D-type latches with 3-State outputs.
In addition to the LE, OE, MR and PRE pins, the 74ABT845 has two
additional OE pins, making a total of three Output Enable (OE0,
OE1, OE2) pins. The multiple Output enables allow multiuser control
of the interface, e.g., CS, DMA, and RD/WR.
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Broadside pinout
• Output capability: +64mA/–32mA
• Power-up 3-State
• Power-up reset
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
Dn to Qn
PLH
PHL
C = 50pF; V = 5V
5.4
4
ns
pF
pF
nA
L
CC
C
Input capacitance
V = 0V or V
I CC
IN
Outputs disabled;
= 0V or V
C
Output capacitance
Total supply current
7
OUT
CCZ
V
O
CC
I
Outputs disabled; V = 5.5V
500
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT845 N
DWG NUMBER
SOT222-1
24-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT845 N
74ABT845 D
74ABT845 DB
74ABT845 PW
24-Pin plastic SO
74ABT845 D
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT845 DB
74ABT845PW DH
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
Output enable inputs
(active-Low)
1, 2, 23
OE0 – OE2
D0-D7
24
OE0
OE1
D0
1
2
3
4
5
6
7
8
9
V
CC
23 OE2
22 Q0
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
3, 4, 5, 6,
7, 8, 9, 10
Data inputs
D1
22, 21, 20, 19,18,
17, 16, 15
Q0-Q7
MR
Data outputs
D2
11
13
Master reset input (active-Low)
D3
Latch enable input
(active-High)
D4
LE
D5
14
12
24
PRE
GND
Preset input (active-Low)
Ground (0V)
D6
D7 10
MR 11
15
14
13
Q7
V
CC
Positive supply voltage
PRE
LE
GND 12
TOP VIEW
SA00258
1
1995 Sep 06
853-1703 15702
Philips Semiconductors
Product specification
8-bit bus interface latch with set and reset
(3-State)
74ABT845
LOGIC SYMBOL (IEEE/IEC)
LOGIC SYMBOL
&
1
2
3
4
5
6
7
8
9
10
EN
23
14
11
13
S2
R
D0 D1 D2 D3 D4 D5 D6 D7
LE
13
14
C1
PRE
11
1
MR
OE0
22
21
3
4
5
6
7
8
9
1D
2
2
OE1
OE2
23
20
19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
18
17
16
15
22 21 20 19 18 17 16 15
10
SA00260
SA00259
FUNCTION TABLE
H
h
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low LE
transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low LE
transition
OUTPU
TS
OPERATING
MODE
INPUTS
OE
n
PR
E
L
l
=
=
MR
LE
Dn
Qn
L
L
L
X
L
X
X
X
X
H
L
Preset
Clear
NC= No change
H
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-Low transition
L
L
H
H
H
H
H
H
L
H
L
H
Transparent
Latched
L
L
H
H
H
H
↓
↓
l
h
L
H
H
L
X
H
X
H
X
L
X
X
Z
High impedance
Hold
NC
LOGIC DIAGRAM
D0
3
D1
D2
D3
D4
D5
D6
D7
10
4
5
6
7
8
9
14
PRE
P
D
P
P
P
P
P
P
P
D
L
D
L
D
L
D
L
D
L
D
L
D
L
Q
Q
Q
Q
Q
Q
Q
L
Q
C
C
C
C
C
C
C
C
11
MR
13
LE
1
OE0
2
OE1
23
22
Q0
21
Q1
20
Q2
19
Q3
18
Q4
17
Q5
16
Q6
15
Q7
OE2
SA00261
2
1995 Sep 06
Philips Semiconductors
Product specification
8-bit bus interface latch with set and reset
(3-State)
74ABT845
1,2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
5
T
amb
Operating free-air temperature range
–40
+85
3
1995 Sep 06
Philips Semiconductors
Product specification
8-bit bus interface latch with set and reset
(3-State)
74ABT845
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.9
2.9
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
V
OH
High–level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
IH
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
Low–level output voltage
Power-up output low
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
0.55
0.55
OL
I
IL
V
RST
V
CC
= 5.5V; I = 1mA; V = GND or V
CC
0.13
V
O
I
3
voltage
I
Input leakage current
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5.0
±1.0
±1.0
µA
µA
I
CC
I
I
Power-off leakage current
= 0.0V; V or V 4.5V
±100
±100
≤
I
OFF
CC
O
Power-up/down
3-state output current
V
= 2.1V; V = 0.5V; V
= V
OE CC;
CC
O
I
±5.0
±50
±50
µA
PU/PD
4
V = GND or V
I CC
I
3-State output High current
3-State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
IH
5.0
–5.0
5.0
–80
0.5
24
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
I
= 5.5V; V = 0.5V; V = V or V
O I IL IH
OZL
I
= 5.5V; V = 5.5V; V = GND or V
O I CC
CEX
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–180
250
30
–50
–180
250
30
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
CCL
I
CC
= 5.5V; Outputs 3-State;
I
0.5
0.5
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
mA
CC
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. For V = 2.1V to V = 5V " 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
4
1995 Sep 06
Philips Semiconductors
Product specification
8-bit bus interface latch with set and reset
(3-State)
74ABT845
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
T
= -40 to
+85 C
= +5.0V ±0.5V
amb
o
T
V
= +25 C
amb
CC
o
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
V
CC
Min
Typ
Min
Max
t
t
Propagation delay
Dn to Qn
1.0
2.2
3.9
5.4
5.4
6.8
1.0
2.2
6.2
7.8
PLH
PHL
1
2
1
1
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
LE to Qn
2.0
2.8
5.1
6.4
6.6
7.9
2.0
2.8
7.5
8.9
PLH
PHL
t
t
Propagation delay
PRE to Qn
2.2
3.0
4.9
5.3
6.6
6.8
2.2
3.0
7.8
7.4
PLH
PHL
t
t
Propagation delay
MR to Qn
2.4
3.1
4.9
5.9
6.4
7.3
2.4
3.1
7.3
8.5
PLH
PHL
t
Output enable time
OEn to Qn
4
5
1.0
2.0
3.8
4.7
5.4
6.1
1.0
2.0
6.3
6.7
PZH
t
PZL
t
Output disable time
OEn to Qn
4
5
1.9
2.2
4.6
4.7
6.2
6.4
1.9
2.2
7.2
7.0
PHZ
t
PLZ
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
Min
Typ
Min
t (H)
t (L)
s
Setup time, High or Low
Dn to LE
2.8
3.5
1.0
1.4
2.8
3.5
s
3
3
ns
ns
t (H)
Hold time, High or Low
Dn to LE
1.0
1.0
–1.2
–0.6
1.0
1.0
h
t (L)
h
t (H)
LE pulse width, High
PRE pulse width, Low
MR pulse width, Low
PRE recovery time
MR recovery time
3
6
6
6
6
3.0
3.5
2.8
3.0
3.4
1.5
2.0
1.3
1.4
1.6
3.0
3.5
2.8
3.0
3.4
ns
ns
ns
ns
ns
w
t (L)
w
t (L)
w
t
t
rec
rec
5
1995 Sep 06
Philips Semiconductors
Product specification
8-bit bus interface latch with set and reset
(3-State)
74ABT845
AC WAVEFORMS
NOTE: For all waveforms, V = 1.5V.
M
Dn
LE
PRE
V
V
M
M
MR, Dn
V
V
M
M
t
t
PHL
PLH
t
t
PHL
Qn
PLH
V
V
M
M
Qn
V
V
M
M
SA00254
SA00255
Waveform 1. Propagation Delay, Data to Output,
Preset to Output, and Master Reset to Output
Waveform 2. Propagation Delay, Latch Enable
to Output
V
V
V
V
Dn
LE
M
M
M
M
V
V
M
OE
Qn
M
t (H)
s
t (H)
h
t (L)
t (L)
h
s
t
w
(H)
t
t
PHZ
PZH
V
V
M
V
M
M
V
–0.3V
OH
V
M
0V
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00256
SA00066
Waveform 3. Data Setup and Hold Times and Latch Enable
Pulse Width
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
V
V
M
PRE, MR
M
V
V
M
OE
Qn
M
t
w
(L)
t
REC
t
t
PLZ
PZL
V
M
LE
V
M
V
V
+0.3V
OL
OL
Qn
Qn
SA00109
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
SA00257
Waveform 6. Master Reset and Preset Pulse Width and Master
Reset and Preset to Latch Enable Recovery Time
6
1995 Sep 06
Philips Semiconductors
Product specification
8-bit bus interface latch with set and reset
(3-State)
74ABT845
TEST CIRCUIT AND WAVEFORM
V
t
W
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
L
0V
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
(t
)
R
THL
F
TLH
)
(t )
F
R
R
L
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00012
7
1995 Sep 06
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