74HCT195PW [NXP]
IC HCT SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, Shift Register;
| 型号： | 74HCT195PW |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, Shift Register 输入元件 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT195
4-bit parallel access shift register
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
by the state of the parallel load enable (PE) input. Serial
data enters the first flip-flop (Q0) via the J and K inputs
when the PE input is HIGH and shifted one bit in the
direction Q0 → Q1 → Q2 → Q3 following each
LOW-to-HIGH clock transition. The J and K inputs provide
the flexibility of the JK type input for special applications
and by tying the pins together, the simple D-type input for
general applications. The “195” appears as four common
clocked D flip-flops when the PE input is LOW.
FEATURES
• Asynchronous master reset
• J, K, (D) inputs to the first stage
• Fully synchronous serial or parallel data transfer
• Shift right and parallel load capability
• Complement output from the last stage
• Output capability: standard
• ICC category: MSI
After the LOW-to-HIGH clock transition, data on the
parallel inputs (D0 to D3) is transferred to the respective
Q0 to Q3 outputs. Shift left operation (Q3 → Q2) can be
achieved by tying the Qn outputs to the Dn-1 inputs and
holding the PE input LOW.
GENERAL DESCRIPTION
The 74HC/HCT195 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
All parallel and serial data transfers are synchronous,
occurring after each LOW-to-HIGH clock transition.
There is no restriction on the activity of the J, K, Dn and
PE inputs for logic operation other than the set-up and
hold time requirements. A LOW on the asynchronous
master reset (MR) input sets all Q outputs LOW,
independent of any other input condition.
The 74HC/HCT195 performs serial, parallel,
serial-to-parallel or parallel-to-serial data transfer at very
high speeds. The “195” operates on two primary modes:
shift right (Qo→Q1) and parallel load, which are controlled
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
tPHL/ tPLH
PARAMETER
CONDITIONS
UNIT
ns
HC
15
HCT
15
propagation delay CP to Qn
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V
fmax
CI
57
57
MHz
pF
3.5
105
3.5
105
CPD
power dissipation capacitance per package
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo)
where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1,5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
MR
J
master reset input (active LOW)
first stage J-input (active HIGH)
first stage K-input (active LOW)
parallel data inputs
2
3
K
4, 5, 6, 7
D0 to D3
GND
PE
8
ground (0 V)
9
parallel enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
inverted output from the last stage
parallel outputs
10
11
CP
Q3
15, 14, 13, 12 Q0 to Q3
16
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
Fig.4 Functional diagram.
APPLICATIONS
• Serial data transfer
• Parallel data transfer
• Serial-to-parallel data transfer
• Parallel-to-serial data transfer
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODES
MR
CP
PE
J
K
Dn
Q0
Q1
Q2
Q3
Q3
asynchronous reset
L
X
X
X
X
X
L
L
L
L
H
shift, set first stage
H
H
H
H
↑
↑
↑
↑
h
h
h
h
h
l
h
l
h
l
l
X
X
X
X
H
L
q0
q0
q0
q0
q0
q0
q1
q1
q1
q1
q2
q2
q2
q2
q2
q2
q2
q2
shift, reset first stage
shift, toggle first stage
shift, retain first stage
h
parallel load
H
↑
l
X
X
dn
d0
d1
d2
d3
d3
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q, d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the
LOW-to-HIGH clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
December 1990
4
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL/ tPLH propagation delay
CP to Qn
50
18
14
150
30
26
190
38
33
225
45
38
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.6
4.5
6.0
tPHL
propagation delay
MR to Qn
41
15
12
150
30
26
190
38
33
225
45
38
2.0 Fig.8
4.5
6.0
t
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.6
4.5
6.0
tW
tW
trem
tsu
tsu
th
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.6
4.5
6.0
master reset pulse width
LOW
80
16
14
11
4
3
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
removal time
MR to CP
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
set-up time
J to CP
100 33
125
25
21
150
30
26
2.0 Figs 8 and 9
4.5
6.0
20
17
12
10
set-up time
K, PE, Dn to CP
80
16
14
25
9
7
100
20
17
120
24
20
2.0 Figs 8 and 9
4.5
6.0
hold time
J, K, PE, Dn to CP
3
3
3
−8
−3
−2
3
3
3
3
3
3
2.0 Figs 8 and 9
4.5
6.0
fmax
maximum clock pulse
frequency
6
30
35
17
52
62
5
24
28
4
20
24
MHz 2.0 Fig.6
4.5
6.0
December 1990
6
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
DC CHARACTERISTICS FOR HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
PE
all others
0.65
0.35
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
18
17
7
32
35
15
40
44
19
48
53
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.6
tPHL
propagation delay
MR to Qn
4.5 Fig.8
t
THL/ tTLH output transition time
4.5 Fig.6
tW
tW
trem
tsu
tsu
th
clock pulse width
HIGH or LOW
20
16
16
20
16
3
6
25
20
20
25
20
3
30
24
24
30
24
3
4.5 Fig.6
master reset pulse width
LOW
6
4.5 Fig.8
removal time
MR to CP
6
4.5 Fig.8
set-up time
J, K, PE to CP
12
6
4.5 Figs 8 and 9
4.5 Figs 8 and 9
4.5 Figs 8 and 9
set-up time
Dn to CP
hold time
−5
52
J, K, PE, Dn to CP
fmax
maximum clock pulse
frequency
27
22
18
MHz 4.5 Fig.6
December 1990
7
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3V; VI = GND to 3 V.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.7 Waveforms showing the master reset
(MR) pulse width, the master reset to output
(Qn) propagation delays and the master
reset to clock (CP) removal time
Fig.6 Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width, the output transition times and
the maximum clock frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.8 Waveforms showing the data set-up
and hold times for J, K and Dn inputs.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.9 Waveforms showing the set-up and hold
times from the parallel enable input
(PE) to the clock (CP).
December 1990
8
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
9
相关型号：
74HCT195PW-T
IC HCT SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, Shift Register
NXP
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