935273694115 [NXP]
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20;
| 型号： | 935273694115 |
| 厂家： | 
NXP |
| 描述： | HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20 驱动 输出元件 逻辑集成电路 |
| 文件： | 总21页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Rev. 6 — 26 January 2015
Product data sheet
1. General description
The 74HC573; 74HCT573 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
no. 7A.
The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type
inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable
(LE) input and an output enable (OE) input are common to all latches.
When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are
transparent, i.e. a latch output changes state each time its corresponding D input
changes.
When LE is LOW the latches store the information that was present at the D-inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches.
The 74HC573; 74HCT573 is functionally identical to:
• 74HC563; 74HCT563, but inverted outputs
• 74HC373; 74HCT373, but different pin arrangement
2. Features and benefits
Input levels:
For 74HC573: CMOS level
For 74HCT573: TTL level
Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
Useful as input or output port for microprocessors and microcomputers
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Multiple package options
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC573N
40 C to +125 C
40 C to +125 C
40 C to +125 C
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
SOT163-1
SOT339-1
SOT360-1
74HCT534N
74HC573D
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
74HCT573D
74HC573DB
74HCT573DB
SSOP20
TSSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
74HC573PW 40 C to +125 C
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
74HCT573PW
74HC573BQ
40 C to +125 C
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
74HCT573BQ
body 2.5 4.5 0.85 mm
4. Functional diagram
ꢆ
ꢀ
ꢇ
ꢈ
ꢉ
ꢃꢋ
ꢃꢄ
ꢃꢊ
ꢃꢉ
ꢃꢈ
ꢃꢇ
ꢃꢀ
ꢃꢆ
'ꢅ
'ꢃ
'ꢆ
'ꢀ
'ꢇ
4ꢅ
4ꢃ
4ꢆ
4ꢀ
4ꢇ
4ꢈ
4ꢉ
4ꢊ
/$7&+ꢂ
ꢃꢂWRꢂꢄ
ꢀꢁ67$7(ꢂ
2873876
ꢂꢊ 'ꢈ
ꢄ
ꢋ
'ꢉ
'ꢊ
/(
ꢃꢃ
ꢃ
2(
PQDꢀꢁꢂ
Fig 1. Functional diagram
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
2 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
'ꢅ
'ꢃ
'ꢆ
'ꢀ
'ꢇ
'ꢈ
'ꢉ
'ꢊ
'
4
'
4
'
4
'
4
'
4
'
4
'
4
'
4
/$7&+ꢂ
ꢃ
/$7&+ꢂ
ꢆ
/$7&+ꢂ
ꢀ
/$7&+ꢂ
ꢇ
/$7&+ꢂ
ꢈ
/$7&+ꢂ
ꢉ
/$7&+ꢂ
ꢊ
/$7&+ꢂ
ꢄ
/(
/(
/(
/(
/(
/(
/(
/(
/(
2(
4ꢅ
4ꢃ
4ꢆ
4ꢀ
4ꢇ
4ꢈ
4ꢉ
4ꢊ
ꢁꢁꢃDDHꢁꢄꢅ
Fig 2. Logic diagram
ꢃꢃ
&ꢃ
ꢃ
(1ꢃ
ꢃ
ꢆ
ꢃꢋ
ꢃ'
2(
ꢆ
ꢃꢋ
ꢃꢄ
ꢃꢊ
ꢃꢉ
ꢃꢈ
ꢃꢇ
ꢃꢀ
ꢃꢆ
'ꢅ
4ꢅ
ꢀ
ꢇ
ꢈ
ꢉ
ꢊ
ꢃꢄ
ꢃꢊ
ꢃꢉ
ꢃꢈ
ꢃꢇ
ꢀ
ꢇ
ꢈ
ꢉ
ꢊ
ꢄ
ꢋ
'ꢃ
'ꢆ
'ꢀ
'ꢇ
'ꢈ
'ꢉ
'ꢊ
4ꢃ
4ꢆ
4ꢀ
4ꢇ
4ꢈ
4ꢉ
4ꢊ
ꢄ
ꢋ
ꢃꢀ
ꢃꢆ
/(
ꢃꢃ
PQDꢀꢁꢄ
PQDꢀꢁꢀ
Fig 3. Logic symbol
Fig 4. IEC logic symbol
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
3 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
ꢀꢁ+&ꢂꢀꢃꢄ
ꢀꢁ+&7ꢂꢀꢃ
WHUPLQDOꢂꢃꢂ
LQGH[ꢂDUHD
ꢀꢁ+&ꢂꢀꢃꢄ
ꢀꢁ+&7ꢂꢀꢃ
ꢆ
ꢀ
ꢇ
ꢈ
ꢉ
ꢊ
ꢄ
ꢋ
ꢃꢋ
ꢃꢄ
ꢃꢊ
ꢃꢉ
ꢃꢈ
ꢃꢇ
ꢃꢀ
ꢃꢆ
'ꢅ
'ꢃ
'ꢆ
'ꢀ
'ꢇ
'ꢈ
'ꢉ
'ꢊ
4ꢅ
4ꢃ
4ꢆ
4ꢀ
4ꢇ
4ꢈ
4ꢉ
4ꢊ
ꢃ
ꢆ
ꢆꢅ
ꢃꢋ
ꢃꢄ
ꢃꢊ
ꢃꢉ
ꢃꢈ
ꢃꢇ
ꢃꢀ
ꢃꢆ
ꢃꢃ
2(
'ꢅ
9
&&
4ꢅ
4ꢃ
4ꢆ
4ꢀ
4ꢇ
4ꢈ
4ꢉ
4ꢊ
/(
ꢀ
'ꢃ
ꢇ
'ꢆ
ꢈ
'ꢀ
ꢌꢃꢍ
ꢉ
*1'
'ꢇ
ꢊ
'ꢈ
ꢄ
'ꢉ
ꢋ
'ꢊ
ꢁꢁꢃDDHꢁꢄꢄ
ꢃꢅ
*1'
7UDQVSDUHQWꢂWRSꢂYLHZ
ꢁꢁꢃDDHꢁꢄꢆ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DIP20, SO20, SSOP20 and
TSSOP20
Fig 6. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
3-state output enable input (active LOW)
data input
D[0:7]
GND
LE
2, 3, 4, 5, 6, 7, 8, 9
10
11
ground (0 V)
latch enable input (active HIGH)
Q[0:7]
VCC
19, 18, 17, 16, 15, 14, 13, 12 3-state latch output
20
supply voltage
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
4 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
6. Functional description
Table 3.
Function table[1]
Operating mode
Control
Input
Internal
latches
Output
OE
LE
Dn
L
H
l
Qn
L
Enable and read register (transparent
mode)
L
H
L
H
L
H
L
Latch and read register
L
L
L
h
l
H
L
H
Z
Latch register and disable outputs
H
h
H
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
35
+70
70
+150
750
500
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
65
[1]
[2]
DIP20 package
-
-
mW
mW
SO20, SSOP20, TSSOP20 and
DHVQFN20 packages
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO20: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
5 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC573
74HCT573
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
V
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
VCC
VCC
VO
output voltage
0
-
+25
-
0
-
+25
-
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
40
+125 C
-
-
-
-
-
-
-
ns/V
1.67
-
1.67
-
139 ns/V
VCC = 6.0 V
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC573
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 6.0 mA; VCC = 4.5 V 3.98 4.32
IO = 7.8 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1.0
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
IOZ
OFF-state
VI = VIH or VIL;
-
-
0.5
-
5.0
-
10.0 A
output current VO = VCC or GND;
VCC = 6.0 V
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
6 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
input
-
3.5
-
pF
capacitance
74HCT573
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 6 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
-
-
0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
IO = 6.0 mA
0.16 0.26
0.33
1.0
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
1.0
A
IOZ
OFF-state
VI = VIH or VIL; VCC = 5.5 V;
-
-
0.5
-
5.0
-
10
A
A
output current VO = VCC or GND per input
pin; other inputs at VCC or
GND; IO = 0 A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160
ICC
additional
VI = VCC 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; Dn inputs
per input pin; LE input
per input pin; OE input
-
-
-
-
35
65
126
234
450
-
-
-
-
-
158
293
563
-
-
-
-
-
172
319
613
-
A
A
A
pF
125
3.5
CI
input
capacitance
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
7 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions
74HC573
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ Max Min
Max
Min
Max
[1]
tpd
propagation Dn to Qn; see Figure 7
delay
VCC = 2.0 V
-
-
-
-
47
17
14
14
150
30
-
-
-
-
-
190
38
-
-
-
-
-
225
45
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
33
38
[1]
tpd
propagation LE to Qn; see Figure 8
delay
VCC = 2.0 V
-
-
-
-
50
18
15
14
150
30
-
-
-
-
-
190
38
-
-
-
-
-
225
45
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
33
38
[2]
[3]
[4]
ten
tdis
tt
enable time OE to Qn; see Figure 9
VCC = 2.0 V
-
-
-
44
16
13
140
28
-
-
-
175
35
-
-
-
210
42
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
24
30
36
disable time OE to Qn; see Figure 9
VCC = 2.0 V
-
-
-
55
20
16
150
30
-
-
-
190
38
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
26
33
38
transition
time
Qn; see Figure 7
VCC = 2.0 V
-
-
-
14
5
60
12
10
-
-
-
75
15
13
-
-
-
90
18
15
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
tW
tsu
th
pulse width LE HIGH; see Figure 8
VCC = 2.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
17
20
set-up time Dn to LE; see Figure 10
VCC = 2.0 V
50
10
9
11
4
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
3
hold time
Dn to LE; see Figure 10
VCC = 2.0 V
5
5
5
-
3
1
-
-
-
-
5
5
5
-
-
-
-
-
5
5
5
-
-
-
-
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
1
[5]
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
26
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
8 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min
Typ Max Min
Max
Min
Max
74HCT573
[1]
[1]
tpd
propagation Dn to Qn; see Figure 7
delay
VCC = 4.5 V
-
-
20
17
35
-
-
-
44
-
-
-
53
-
ns
ns
VCC = 5 V; CL = 15 pF
tpd
propagation LE to Qn; see Figure 8
delay
VCC = 4.5 V
-
-
18
15
35
-
-
-
44
-
-
-
53
-
ns
ns
VCC = 5 V; CL = 15 pF
enable time OE to Qn; see Figure 9
VCC = 4.5 V
[2]
[3]
[4]
ten
tdis
tt
-
-
17
18
5
30
30
12
-
-
-
38
38
15
-
-
-
45
45
18
-
ns
ns
ns
ns
ns
disable time OE to Qn; see Figure 9
VCC = 4.5 V
transition
time
Qn; see Figure 7
VCC = 4.5 V
-
-
-
tW
tsu
th
pulse width LE HIGH; see Figure 8
VCC = 4.5 V
16
13
5
20
16
24
20
set-up time Dn to LE; see Figure 10
VCC = 4.5 V
7
-
-
-
hold time
Dn to LE; see Figure 10
VCC = 4.5 V
9
-
4
-
-
11
-
-
-
15
-
-
-
ns
[5]
CPD
power
CL = 50 pF; f = 1 MHz;
26
pF
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] tpd is the same as tPLH and tPHL
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
9 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
11. Waveforms
'QꢂLQSXW
9
0
W
W
3+/
3/+
ꢋꢅꢂꢎ
9
4QꢂRXWSXW
0
ꢃꢅꢂꢎ
7/+
W
W
7+/
ꢁꢁꢃDDHꢁꢀꢇ
Measurement points are given in Table 8.
Fig 7. Propagation delay data input (Dn) to output (Qn) and output transition time
/(ꢂLQSXW
9
0
W
:
W
W
3+/
3/+
ꢋꢅꢂꢎ
9
4QꢂRXWSXW
0
ꢃꢅꢂꢎ
W
W
7/+
7+/
ꢁꢁꢃDDHꢁꢀꢈ
Measurement points are given in Table 8.
Fig 8. Pulse width latch enable input (LE), propagation delay latch enable input (LE) to output (Qn) and output
transition time
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
10 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
9
,
2(ꢂLQSXW
RXWSXWꢂ
9
0
*1'
W
W
3/=
3=/
9
&&
9
/2:ꢁWRꢁ2))ꢂ
0
2))ꢁWRꢁ/2:
ꢃꢅꢎ
9
2/
W
W
3=+
3+=
9
2+
ꢋꢅꢎ
RXWSXWꢂ
9
+,*+ꢁWRꢁ2))ꢂ
2))ꢁWRꢁ+,*+
0
*1'
RXWSXWVꢂ
HQDEOHG
RXWSXWVꢂ
GLVDEOHG
RXWSXWVꢂ
HQDEOHG
ꢁꢁꢃDDHꢈꢁꢄ
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Enable and disable times
9
K
/(ꢂLQSXW
0
W
W
VX
VX
W
W
K
9
'QꢂLQSXW
0
ꢁꢁꢃDDHꢁꢀꢉ
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. Set-up and hold times for data input (Dn) to latch input (LE)
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC573
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT573
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
11 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
W
:
9
,
ꢋꢅꢂꢎ
QHJDWLYHꢂ
SXOVH
9
9
9
9
0
0
ꢃꢅꢂꢎ
ꢅꢂ9
W
W
U
I
W
W
U
I
9
,
ꢋꢅꢂꢎ
SRVLWLYHꢂ
SXOVH
0
0
ꢃꢅꢂꢎ
ꢅꢂ9
W
:
9
9
&&
&&
9
,
9
2
ꢂ
5
/
6ꢃ
*
RSHQ
'87
5
7
&
/
ꢁꢁꢃDDGꢂꢀꢈ
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 11. Test circuit for measuring switching times
Table 9.
Type
Test data
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC573
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT573
open
GND
VCC
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
12 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
12. Package outline
',3ꢇꢊꢋꢄSODVWLFꢄGXDOꢄLQꢌOLQHꢄSDFNDJHꢍꢄꢇꢊꢄOHDGVꢄꢈꢃꢊꢊꢄPLOꢉꢄ
627ꢆꢁꢎꢌꢆꢄ
0ꢂ
(ꢂ
'ꢂ
$ꢂ
ꢆꢂ
$ꢂ
$ꢂ
ꢃꢂ
/ꢂ
Fꢂ
Hꢂ
Zꢂ 0ꢂ
=ꢂ
Eꢂ
ꢃꢂ
ꢌHꢂꢂꢍꢂ
ꢃꢂ
Eꢂ
0ꢂ
+ꢂ
ꢆꢅꢂ
ꢃꢃꢂ
SLQꢂꢃꢂLQGH[ꢂ
(ꢂ
ꢃꢂ
ꢃꢅꢂ
ꢅꢂ
ꢈꢂ
ꢃꢅꢂPPꢂ
VFDOHꢂ
',0(16,216ꢄꢈLQFKꢄGLPHQVLRQVꢄDUHꢄGHULYHGꢄIURPꢄWKHꢄRULJLQDOꢄPPꢄGLPHQVLRQVꢉꢄ
ꢈꢆꢉꢄ
ꢈꢆꢉꢄ
ꢈꢆꢉꢄ
$ꢄ
$ꢄꢄꢄ
ꢆꢄ
$ꢄꢄꢄ
ꢇꢄ
=ꢄ
81,7ꢄ
PPꢂ
Eꢄ
Eꢄ
Fꢄ
'ꢄ
(ꢄ
Hꢄ
Hꢄ
ꢆꢄ
/ꢄ
0ꢄ
0ꢄ
+ꢄ
Zꢄ
ꢆꢄ
(ꢄ
PD[ꢅꢄ
PLQꢅꢄ
PD[ꢅꢄ
PD[ꢅꢄ
ꢃꢏꢊꢀꢂ
ꢃꢏꢀꢅꢂ
ꢅꢏꢈꢀꢂ
ꢅꢏꢀꢄꢂ
ꢅꢏꢀꢉꢂ
ꢅꢏꢆꢀꢂ
ꢆꢉꢏꢋꢆꢂ
ꢆꢉꢏꢈꢇꢂ
ꢉꢏꢇꢅꢂ
ꢉꢏꢆꢆꢂ
ꢀꢏꢉꢅꢂ
ꢀꢏꢅꢈꢂ
ꢄꢏꢆꢈꢂ
ꢊꢏꢄꢅꢂ
ꢃꢅꢏꢅꢂ
ꢂꢂꢄꢏꢀꢂ
ꢇꢏꢆꢂ
ꢅꢏꢈꢃꢂ
ꢀꢏꢆꢂ
ꢆꢏꢈꢇꢂ
ꢅꢏꢃꢂ
ꢊꢏꢉꢆꢂ
ꢅꢏꢀꢂ
ꢅꢏꢆꢈꢇꢂ
ꢅꢏꢅꢃꢂ
ꢆꢂ
ꢅꢏꢅꢉꢄꢂ ꢅꢏꢅꢆꢃꢂ ꢅꢏꢅꢃꢇꢂ ꢃꢏꢅꢉꢅꢂ
ꢅꢏꢅꢈꢃꢂ ꢅꢏꢅꢃꢈꢂ ꢅꢏꢅꢅꢋꢂ ꢃꢏꢅꢇꢈꢂ
ꢅꢏꢆꢈꢂ
ꢅꢏꢆꢇꢂ
ꢅꢏꢃꢇꢂ
ꢅꢏꢃꢆꢂ
ꢅꢏꢀꢆꢂ
ꢅꢏꢀꢃꢂ
ꢅꢏꢀꢋꢂ
ꢅꢏꢀꢀꢂ
LQFKHVꢂ
ꢅꢏꢃꢊꢂ
ꢅꢏꢅꢆꢂ
ꢅꢏꢃꢀꢂ
ꢅꢏꢅꢊꢄꢂ
1RWHꢄ
ꢃꢏꢂ3ODVWLFꢂRUꢂPHWDOꢂSURWUXVLRQVꢂRIꢂꢅꢏꢆꢈꢂPPꢂꢌꢅꢏꢅꢃꢂLQFKꢍꢂPD[LPXPꢂSHUꢂVLGHꢂDUHꢂQRWꢂLQFOXGHGꢏꢂꢂ
ꢄ5()(5(1&(6ꢄ
287/,1(ꢄ
9(56,21ꢄ
(8523($1ꢄ
352-(&7,21ꢄ
,668(ꢄ'$7(ꢄ
ꢄ,(&ꢄ
ꢄ-('(&ꢄ
06ꢁꢂꢅꢅꢃꢂ
ꢄ-(,7$ꢄ
ꢋꢋꢁꢃꢆꢁꢆꢊꢂ
ꢅꢀꢁꢅꢆꢁꢃꢀꢂ
627ꢃꢇꢉꢁꢃꢂ
ꢂ
6&ꢁꢉꢅꢀꢂ
Fig 12. Package outline SOT146-1 (DIP20)
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
13 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
62ꢇꢊꢋꢄSODVWLFꢄVPDOOꢄRXWOLQHꢄSDFNDJHꢍꢄꢇꢊꢄOHDGVꢍꢄERG\ꢄZLGWKꢄꢀꢅꢂꢄPPꢄ
627ꢆꢎꢃꢌꢆꢄ
'ꢂ
(ꢂ
$ꢂ
;ꢂ
Fꢂ
\ꢂ
+ꢂ
(ꢂ
Yꢂ 0ꢂ
$ꢂ
=ꢂ
ꢆꢅꢂ
ꢃꢃꢂ
4ꢂ
$ꢂ
ꢆꢂ
$ꢂ
ꢌ$ꢂꢂꢍꢂ
ꢀꢂ
$ꢂ
ꢃꢂ
SLQꢂꢃꢂLQGH[ꢂ
șꢂ
/ꢂ
Sꢂ
/ꢂ
ꢃꢂ
ꢃꢅꢂ
Zꢂ 0ꢂ
GHWDLOꢂ;ꢂ
Hꢂ
Eꢂ
Sꢂ
ꢅꢂ
ꢈꢂ
ꢃꢅꢂPPꢂ
VFDOHꢂ
',0(16,216ꢄꢈLQFKꢄGLPHQVLRQVꢄDUHꢄGHULYHGꢄIURPꢄWKHꢄRULJLQDOꢄPPꢄGLPHQVLRQVꢉꢄ
$ꢄ
ꢈꢆꢉꢄ
ꢈꢆꢉꢄ
ꢈꢆꢉꢄ
81,7ꢄ
$ꢄ
$ꢄ
$ꢄ
Eꢄ
Sꢄ
Fꢄ
'ꢄ
(ꢄ
Hꢄ
+ꢄ
/ꢄ
/ꢄ
4ꢄ
Yꢄ
Zꢄ
\ꢄ
ꢅꢏꢃꢂ
șꢂ
ꢆꢄ
ꢇꢄ
ꢃꢄ
(ꢄ
Sꢄ
=ꢄ
PD[ꢅꢄ
ꢅꢏꢀꢂ
ꢅꢏꢃꢂ
ꢆꢏꢇꢈꢂ
ꢆꢏꢆꢈꢂ
ꢅꢏꢇꢋꢂ ꢅꢏꢀꢆꢂ ꢃꢀꢏꢅꢂ
ꢅꢏꢀꢉꢂ ꢅꢏꢆꢀꢂ ꢃꢆꢏꢉꢂ
ꢊꢏꢉꢂ
ꢊꢏꢇꢂ
ꢃꢅꢏꢉꢈꢂ
ꢃꢅꢏꢅꢅꢂ
ꢃꢏꢃꢂ
ꢅꢏꢇꢂ
ꢃꢏꢃꢂ
ꢃꢏꢅꢂ
ꢅꢏꢋꢂ
ꢅꢏꢇꢂ
PPꢂ
ꢆꢏꢉꢈꢂ
ꢅꢏꢆꢈꢂ
ꢅꢏꢅꢃꢂ
ꢃꢏꢆꢊꢂ
ꢅꢏꢅꢈꢂ
ꢃꢏꢇꢂ
ꢅꢏꢆꢈꢂ ꢅꢏꢆꢈꢂ
Rꢂ
ꢄꢂ
Rꢂ
ꢅꢂ
ꢅꢏꢅꢃꢆꢂ ꢅꢏꢅꢋꢉꢂ
ꢅꢏꢅꢅꢇꢂ ꢅꢏꢅꢄꢋꢂ
ꢅꢏꢅꢃꢋꢂ ꢅꢏꢅꢃꢀꢂ ꢅꢏꢈꢃꢂ ꢅꢏꢀꢅꢂ
ꢅꢏꢅꢃꢇꢂ ꢅꢏꢅꢅꢋꢂ ꢅꢏꢇꢋꢂ ꢅꢏꢆꢋꢂ
ꢅꢏꢇꢃꢋꢂ
ꢅꢏꢀꢋꢇꢂ
ꢅꢏꢅꢇꢀꢂ ꢅꢏꢅꢇꢀꢂ
ꢅꢏꢅꢃꢉꢂ ꢅꢏꢅꢀꢋꢂ
ꢅꢏꢅꢀꢈꢂ
ꢅꢏꢅꢃꢉꢂ
LQFKHVꢂ ꢅꢏꢃꢂ
ꢅꢏꢅꢈꢈꢂ
ꢅꢏꢅꢃꢂ ꢅꢏꢅꢃꢂ ꢅꢏꢅꢅꢇꢂ
1RWHꢄ
ꢃꢏꢂ3ODVWLFꢂRUꢂPHWDOꢂSURWUXVLRQVꢂRIꢂꢅꢏꢃꢈꢂPPꢂꢌꢅꢏꢅꢅꢉꢂLQFKꢍꢂPD[LPXPꢂSHUꢂVLGHꢂDUHꢂQRWꢂLQFOXGHGꢏꢂꢂꢂ
ꢄ5()(5(1&(6ꢄ
ꢄ-('(&ꢄ ꢄ-(,7$ꢄ
ꢂ06ꢁꢅꢃꢀꢂ
287/,1(ꢄ
9(56,21ꢄ
(8523($1ꢄ
352-(&7,21ꢄ
,668(ꢄ'$7(ꢄ
ꢄ,(&ꢄ
ꢋꢋꢁꢃꢆꢁꢆꢊꢂ
ꢅꢀꢁꢅꢆꢁꢃꢋꢂ
ꢂ627ꢃꢉꢀꢁꢃꢂ
ꢂꢅꢊꢈ(ꢅꢇꢂ
Fig 13. Package outline SOT163-1 (SO20)
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
14 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
6623ꢇꢊꢋꢄSODVWLFꢄVKULQNꢄVPDOOꢄRXWOLQHꢄSDFNDJHꢍꢄꢇꢊꢄOHDGVꢍꢄERG\ꢄZLGWKꢄꢂꢅꢃꢄPPꢄ
627ꢃꢃꢏꢌꢆꢄ
'ꢂ
(ꢂ
$ꢂ
;ꢂ
Fꢂ
+ꢂ
(ꢂ
Yꢂ 0ꢂ
$ꢂ
\ꢂ
=ꢂ
ꢆꢅꢂ
ꢃꢃꢂ
4ꢂ
$ꢂ
ꢆꢂ
$ꢂ
ꢌ$ꢂꢂꢍꢂ
ꢀꢂ
$ꢂ
ꢃꢂ
SLQꢂꢃꢂLQGH[ꢂ
șꢂ
/ꢂ
Sꢂ
/ꢂ
ꢃꢂ
ꢃꢅꢂ
Zꢂ 0ꢂ
GHWDLOꢂ;ꢂ
Eꢂ
Sꢂ
Hꢂ
ꢅꢂ
ꢆꢏꢈꢂ
ꢈꢂPPꢂ
VFDOHꢂ
',0(16,216ꢄꢈPPꢄDUHꢄWKHꢄRULJLQDOꢄGLPHQVLRQVꢉꢄ
$ꢄ
ꢈꢆꢉꢄ
ꢈꢆꢉꢄ
ꢈꢆꢉꢄ
81,7ꢄ
$ꢄ
ꢆꢄ
$ꢄ
ꢇꢄ
$ꢄ
ꢃꢄ
Eꢄ
Sꢄ
Fꢄ
'ꢄ
(ꢄ
Hꢄ
+ꢄ
/ꢄ
/ꢄ
Sꢄ
4ꢄ
Yꢄ
ꢅꢏꢆꢂ
Zꢄ
\ꢄ
=ꢄ
șꢂ
(ꢄ
PD[ꢅꢄ
Rꢂ
ꢅꢏꢆꢃꢂ ꢃꢏꢄꢅꢂ
ꢅꢏꢅꢈꢂ ꢃꢏꢉꢈꢂ
ꢅꢏꢀꢄꢂ ꢅꢏꢆꢅꢂ
ꢅꢏꢆꢈꢂ ꢅꢏꢅꢋꢂ
ꢊꢏꢇꢂ
ꢊꢏꢅꢂ
ꢈꢏꢇꢂ
ꢈꢏꢆꢂ
ꢊꢏꢋꢂ
ꢊꢏꢉꢂ
ꢃꢏꢅꢀꢂ
ꢅꢏꢉꢀꢂ
ꢅꢏꢋꢂ
ꢅꢏꢊꢂ
ꢅꢏꢋꢂ
ꢅꢏꢈꢂ
ꢄꢂ
PPꢂ
ꢆꢂ
ꢅꢏꢉꢈꢂ
ꢃꢏꢆꢈꢂ
ꢅꢏꢃꢀꢂ
ꢅꢏꢃꢂ
ꢅꢏꢆꢈꢂ
Rꢂ
ꢅꢂ
1RWHꢄ
ꢃꢏꢂ3ODVWLFꢂRUꢂPHWDOꢂSURWUXVLRQVꢂRIꢂꢅꢏꢆꢂPPꢂPD[LPXPꢂSHUꢂVLGHꢂDUHꢂQRWꢂLQFOXGHGꢏꢂꢂ
ꢄ5()(5(1&(6ꢄ
ꢄ-('(&ꢄ ꢄ-(,7$ꢄ
ꢂ02ꢁꢃꢈꢅꢂ
287/,1(ꢄ
9(56,21ꢄ
(8523($1ꢄ
352-(&7,21ꢄ
,668(ꢄ'$7(ꢄ
ꢄ,(&ꢄ
ꢋꢋꢁꢃꢆꢁꢆꢊꢂ
ꢅꢀꢁꢅꢆꢁꢃꢋꢂ
ꢂ627ꢀꢀꢋꢁꢃꢂ
Fig 14. Package outline SOT339-1 (SSOP20)
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
15 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
76623ꢇꢊꢋꢄSODVWLFꢄWKLQꢄVKULQNꢄVPDOOꢄRXWOLQHꢄSDFNDJHꢍꢄꢇꢊꢄOHDGVꢍꢄERG\ꢄZLGWKꢄꢁꢅꢁꢄPPꢄ
627ꢃꢎꢊꢌꢆꢄ
'ꢂ
(ꢂ
$ꢂ
;ꢂ
Fꢂ
+ꢂ
(ꢂ
Yꢂ 0ꢂ
$ꢂ
\ꢂ
=ꢂ
ꢆꢅꢂ
ꢃꢃꢂ
4ꢂ
$ꢂ
ꢆꢂ
ꢌ$ꢂꢂꢍꢂ
ꢀꢂ
$ꢂ
$ꢂ
ꢃꢂ
SLQꢂꢃꢂLQGH[ꢂ
șꢂ
/ꢂ
Sꢂ
/ꢂ
ꢃꢂ
ꢃꢅꢂ
GHWDLOꢂ;ꢂ
Zꢂ 0ꢂ
Eꢂ
Sꢂ
Hꢂ
ꢅꢂ
ꢆꢏꢈꢂ
ꢈꢂPPꢂ
VFDOHꢂ
',0(16,216ꢄꢈPPꢄDUHꢄWKHꢄRULJLQDOꢄGLPHQVLRQVꢉꢄ
$ꢄ
ꢈꢆꢉꢄ
ꢈꢇꢉꢄ
ꢈꢆꢉꢄ
81,7ꢄ
PPꢂ
$ꢄ
ꢆꢄ
$ꢄ
ꢇꢄ
$ꢄ
ꢃꢄ
Eꢄ
Sꢄ
Fꢄ
'ꢄ
(ꢄ
Hꢄ
+ꢄ
/ꢄ
/ꢄ
Sꢄ
4ꢄ
Yꢄ
Zꢄ
\ꢄ
ꢅꢏꢃꢂ
=ꢄ
șꢂ
(ꢄ
PD[ꢅꢄ
Rꢂ
ꢅꢏꢃꢈꢂ ꢅꢏꢋꢈꢂ
ꢅꢏꢅꢈꢂ ꢅꢏꢄꢅꢂ
ꢅꢏꢀꢅꢂ
ꢅꢏꢃꢋꢂ
ꢅꢏꢆꢂ
ꢅꢏꢃꢂ
ꢉꢏꢉꢂ
ꢉꢏꢇꢂ
ꢇꢏꢈꢂ
ꢇꢏꢀꢂ
ꢉꢏꢉꢂ
ꢉꢏꢆꢂ
ꢅꢏꢊꢈꢂ
ꢅꢏꢈꢅꢂ
ꢅꢏꢇꢂ
ꢅꢏꢀꢂ
ꢅꢏꢈꢂ
ꢅꢏꢆꢂ
ꢄꢂ
ꢃꢏꢃꢂ
ꢅꢏꢉꢈꢂ
ꢃꢂ
ꢅꢏꢆꢂ ꢅꢏꢃꢀꢂ
ꢅꢏꢆꢈꢂ
Rꢂ
ꢅꢂ
1RWHVꢄ
ꢃꢏꢂ3ODVWLFꢂRUꢂPHWDOꢂSURWUXVLRQVꢂRIꢂꢅꢏꢃꢈꢂPPꢂPD[LPXPꢂSHUꢂVLGHꢂDUHꢂQRWꢂLQFOXGHGꢏꢂ
ꢆꢏꢂ3ODVWLFꢂLQWHUOHDGꢂSURWUXVLRQVꢂRIꢂꢅꢏꢆꢈꢂPPꢂPD[LPXPꢂSHUꢂVLGHꢂDUHꢂQRWꢂLQFOXGHGꢏꢂ
ꢄ5()(5(1&(6ꢄ
ꢄ-('(&ꢄ ꢄ-(,7$ꢄ
ꢂ02ꢁꢃꢈꢀꢂ
287/,1(ꢄ
9(56,21ꢄ
(8523($1ꢄ
352-(&7,21ꢄ
,668(ꢄ'$7(ꢄ
ꢄ,(&ꢄ
ꢋꢋꢁꢃꢆꢁꢆꢊꢂ
ꢅꢀꢁꢅꢆꢁꢃꢋꢂ
ꢂ627ꢀꢉꢅꢁꢃꢂ
Fig 15. Package outline SOT360-1 (TSSOP20)
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
16 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
'+94)1ꢇꢊꢋꢄSODVWLFꢄGXDOꢄLQꢌOLQHꢄFRPSDWLEOHꢄWKHUPDOꢄHQKDQFHGꢄYHU\ꢄWKLQꢄTXDGꢄIODWꢄSDFNDJHꢍꢄQRꢄOHDGVꢍ
ꢇꢊꢄWHUPLQDOVꢍꢄERG\ꢄꢇꢅꢂꢄ[ꢄꢁꢅꢂꢄ[ꢄꢊꢅꢐꢂꢄPP
627ꢀꢎꢁꢌꢆ
%
$
(
'
$
$
ꢃ
F
GHWDLOꢂ;
WHUPLQDOꢂꢃ
LQGH[ꢂDUHD
WHUPLQDOꢂꢃ
LQGH[ꢂDUHD
H
&
ꢃ
Y
Z
&
&
$ %
\
\
H
E
&
ꢃ
ꢆ
ꢋ
/
ꢃ
ꢃꢅ
(
H
K
ꢆꢅ
ꢃꢃ
ꢃꢋ
ꢃꢆ
;
'
K
ꢅ
ꢆꢏꢈ
ꢈꢂPP
VFDOH
'LPHQVLRQVꢂꢌPPꢂDUHꢂWKHꢂRULJLQDOꢂGLPHQVLRQVꢍ
ꢌꢃꢍ
ꢌꢃꢍ
ꢌꢃꢍ
8QLW
$
$
E
F
'
'
K
(
(
H
H
ꢃ
/
Y
Z
\
\
ꢃ
ꢃ
K
PD[ ꢃꢏꢅꢅ ꢅꢏꢅꢈ ꢅꢏꢀꢅ
ꢇꢏꢉ ꢀꢏꢃꢈ ꢆꢏꢉ ꢃꢏꢃꢈ
ꢅꢏꢈ
QRP
PLQ
PP
ꢅꢏꢋꢅ ꢅꢏꢅꢆ ꢅꢏꢆꢈ ꢅꢏꢆ ꢇꢏꢈ ꢀꢏꢅꢅ ꢆꢏꢈ ꢃꢏꢅꢅ ꢅꢏꢈ ꢀꢏꢈ ꢅꢏꢇ ꢅꢏꢃ ꢅꢏꢅꢈ ꢅꢏꢅꢈ ꢅꢏꢃ
ꢅꢏꢄꢅ ꢅꢏꢅꢅ ꢅꢏꢃꢄ
ꢇꢏꢇ ꢆꢏꢄꢈ ꢆꢏꢇ ꢅꢏꢄꢈ
ꢅꢏꢀ
1RWH
ꢃꢏꢂ3ODVWLFꢂRUꢂPHWDOꢂSURWUXVLRQVꢂRIꢂꢅꢏꢅꢊꢈꢂPPꢂPD[LPXPꢂSHUꢂVLGHꢂDUHꢂQRWꢂLQFOXGHGꢏ
VRWꢄꢆꢉꢊꢃBSR
5HIHUHQFHV
2XWOLQH
YHUVLRQ
(XURSHDQ
SURMHFWLRQ
,VVXHꢂGDWH
,(&
ꢁꢂꢁꢂꢁ
-('(&
-(,7$
ꢁꢂꢁꢂꢁ
ꢅꢀꢁꢅꢃꢁꢆꢊ
ꢃꢇꢁꢃꢆꢁꢃꢆ
627ꢊꢉꢇꢁꢃ
02ꢁꢆꢇꢃ
Fig 16. Package outline SOT764-1 (DHVQFN20)
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
17 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20150126 Product data sheet
Change notice
Supersedes
74HC_HCT573 v.6
Modifications:
-
74HC_HCT573 v.5
• Table 7: Power dissipation capacitance condition for 74HCT573 is corrected.
74HC_HCT573 v.5
Modifications:
20120815
• Alternative descriptive title corrected (errata).
20120806 Product data sheet
Product data sheet
-
74HC_HCT573 v.4
74HC_HCT573 v.4
Modifications:
-
74HC_HCT573 v.3
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT573 v.3
20060117
Product data sheet
-
74HC_HCT573_CNV v.2
74HC_HCT573_CNV v.2
19901201
Product specification
-
-
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
18 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
15.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
19 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 6 — 26 January 2015
20 of 21
74HC573; 74HCT573
NXP Semiconductors
Octal D-type transparent latch; 3-state
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 January 2015
Document identifier: 74HC_HCT573
相关型号：
935273697115
HCT SERIES, QUAD 2-INPUT NAND GATE, PQCC14, 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT762-1, DHVQFN-14
NXP
935273729115
HCT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20
NXP
935273731115
HCT SERIES, QUAD 2-INPUT OR GATE, PQCC14, 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-762-1, DHVQFN-14
NXP
935273732115
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20
NXP
935273733115
Serial In Parallel Out, HCT Series, 8-Bit, Right Direction, True Output, CMOS, PQCC16
NXP
935273778115
IC HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, QCC16, SOT-763, 16 PIN, Decoder/Driver
NXP
935273783125
LVC/LCX/Z SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6, PLASTIC, SOT-363, SC-88, 6 PIN
NXP
935273784125
LVC/LCX/Z SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6, PLASTIC, SC-74, SOT-457, TSOP-6
NXP
935273787129
8-BIT, FLASH, 18MHz, MICROCONTROLLER, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20
NXP
935273787529
8-BIT, FLASH, 18MHz, MICROCONTROLLER, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20
NXP
935273788129
8-BIT, FLASH, 18MHz, MICROCONTROLLER, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20
NXP
©2020 ICPDF网 联系我们和版权申明