HEF4051BT-653 [PHILIPS]

8-channel analog multiplexer/demultiplexer; 8通道模拟多路复用器/
HEF4051BT-653
元器件型号: HEF4051BT-653
生产厂家: NXP SEMICONDUCTORS    NXP SEMICONDUCTORS
描述和应用:

8-channel analog multiplexer/demultiplexer
8通道模拟多路复用器/

复用器
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HEF4051B
8-channel analog multiplexer/demultiplexer
Rev. 10 — 17 November 2011
Product data sheet
1. General description
The HEF4051B is an 8-channel analog multiplexer/demultiplexer with three address
inputs (S1 to S3), an active LOW enable input (E), eight independent inputs/outputs
(Y0 to Y7) and a common input/output (Z). The device contains eight bidirectional analog
switches, each with one side connected to an independent input/output (Y0 to Y7) and the
other side connected to a common input/output (Z). With E LOW, one of the eight
switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches
are in the high-impedance OFF-state, independent of S1 to S3. If break before make is
needed, then it is necessary to use the enable input.
V
DD
and V
SS
are the supply voltage connections for the digital control inputs (S1 to S3,
and E). The V
DD
to V
SS
range is 3 V to 15 V. The analog inputs/outputs (Y0 to Y7, and Z)
can swing between V
DD
as a positive limit and V
EE
as a negative limit. V
DD
V
EE
may not
exceed 15 V. Unused inputs must be connected to V
DD
, V
SS
, or another input. For
operation as a digital multiplexer/demultiplexer, V
EE
is connected to V
SS
(typically
ground). V
EE
and V
SS
are the supply voltage connections for the switches.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
and
40 C
to +125
C
Complies with JEDEC standard JESD 13-B
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
NXP Semiconductors
HEF4051B
8-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +125
C.
Type number
HEF4051BP
HEF4051BT
HEF4051BTS
HEF4051BTT
Package
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
5. Functional diagram
V
DD
16
13 Y0
S1 11
14 Y1
15 Y2
S2 10
12 Y3
LOGIC
LEVEL
CONVERSION
S3 9
1
OF
8
DECODER
1 Y4
5 Y5
2 Y6
E 6
4 Y7
3 Z
8
V
SS
7
V
EE
001aac277
Fig 1.
Functional diagram
HEF4051B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
2 of 23
NXP Semiconductors
HEF4051B
8-channel analog multiplexer/demultiplexer
Yn
V
DD
V
DD
Z
V
EE
001aac281
Fig 2.
Schematic diagram (one switch)
11
10
9
1
X
3
EN
0
7
13
S1
S2
S3
11
10
9
14
15
12
1
5
2
E
6
3
Z
001aac278
Y0
6
Y1
Y2
Y3
Y4
Y5
Y6
Y7
3
MUX/DMUX
0
1
2
3
4
5
6
7
001aac279
13
14
15
12
1
5
2
4
4
Fig 3. Logic symbol
Fig 4. IEC logic symbol
HEF4051B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
3 of 23
NXP Semiconductors
HEF4051B
8-channel analog multiplexer/demultiplexer
Y0
Y1
S1
LEVEL
CONVERTER
Y2
S2
LEVEL
CONVERTER
Y3
S3
LEVEL
CONVERTER
Y4
E
LEVEL
CONVERTER
Y5
Y6
Y7
Z
001aac280
Fig 5.
Logic diagram
HEF4051B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
4 of 23
NXP Semiconductors
HEF4051B
8-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
HEF4051B
Y4
Y6
Z
Y7
Y5
E
V
EE
V
SS
1
2
3
4
5
6
7
8
001aak508
16 V
DD
15 Y2
14 Y1
13 Y0
12 Y3
11 S1
10 S2
9
S3
1
2
3
4
5
6
7
8
001aac282
HEF4051B
Y4
Y6
Z
Y7
Y5
E
V
EE
V
SS
16 V
DD
15 Y2
14 Y1
13 Y0
12 Y3
11 S1
10 S2
9
S3
Fig 6.
Pin configuration SOT38-4 and SOT109-1
Fig 7.
Pin configuration SOT338-1 and SOT403-1
6.2 Pin description
Table 2.
Symbol
E
V
EE
V
SS
S1, S2, S3
Z
V
DD
Pin description
Pin
6
7
8
11, 10, 9
3
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
common output or input
supply voltage
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4
HEF4051B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
5 of 23
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