HEF4086BN [NXP]
4-wide 2-input AND-OR-invert gate; 4-宽2输入与或反相门
| 型号： | HEF4086BN |
| 厂家： | 
NXP |
| 描述： | 4-wide 2-input AND-OR-invert gate |
| 文件： | 总5页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4086B
gates
4-wide 2-input AND-OR-invert gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4086B
gates
4-wide 2-input AND-OR-invert gate
DESCRIPTION
The HEF4086B is a 4-wide 2-input AND-OR-invert (AOI)
gate with two additional inputs (I8 or I9) which can be used
as either expander or inhibit inputs by connecting them to
any standard LOCMOS output. A HIGH on I8 or a LOW on
I9 forces the output (O) LOW independent of the other
eight inputs (I0 to I7). The output (O) is fully buffered for
highest noise immunity and pattern insensitivity of output
impedance.
Fig.2 Pinning diagram.
HEF4086BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4086BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4086BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.1 Functional diagram.
PINNING
I0 to I8
gate inputs
I9
gate input (active LOW)
output (active LOW)
O
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4086B
gates
4-wide 2-input AND-OR-invert gate
Fig.3 Logic diagram.
LOGIC EQUATION
O = I0 I1 + I2 I3 + I4 I5 + I6 I7 + I8 + I9
January 1995
3
Philips Semiconductors
Product specification
HEF4086B
gates
4-wide 2-input AND-OR-invert gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP. MAX.
Propagation delays
I0 to I7 → O
5
90
30
20
80
30
20
70
25
20
55
20
15
55
20
15
45
15
10
60
30
20
60
30
20
180
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
63 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
53 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
43 ns + (0,55 ns/pF) CL
14 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
28 ns + (0,55 ns/pF) CL
9 ns + (0,23 ns/pF) CL
7 ns + (0,16 ns/pF) CL
28 ns + (0,55 ns/pF) CL
9 ns + (0,23 ns/pF) CL
7 ns + (0,16 ns/pF) CL
18 ns + (0,55 ns/pF) CL
4 ns + (0,23 ns/pF) CL
2 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
10
15
5
tPHL
40
155
60
LOW to HIGH
10
15
5
tPLH
tPHL
tPLH
tPHL
tPLH
tTHL
tTLH
40
I8 → O
140
55
HIGH to LOW
10
15
5
40
115
40
LOW to HIGH
10
15
5
25
I9 → O
105
45
HIGH to LOW
10
15
5
30
90
LOW to HIGH
10
15
5
35
25
Output transition times
HIGH to LOW
120
60
10
15
5
40
120
60
LOW to HIGH
10
15
40
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
525 fi + ∑ (foCL) × VDD
where
2
2600 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
2
7300 fi + ∑ (foCL) × VDD
January 1995
4
Philips Semiconductors
Product specification
HEF4086B
gates
4-wide 2-input AND-OR-invert gate
APPLICATION INFORMATION
Figure 4 shows two HEF4086B ICs connected to obtain an 8-wide 2-input AOI function.
The output (OA) of the first IC is fed directly into the I9B gate input of the second IC. Similarly,
any NAND gate output can be fed directly into the I9 gate input to obtain a 5-wide AOI function.
In addition, any AND gate output can be fed directly into the I8 gate input with the same result.
Fig.4 Two HEF4086B ICs connected as an 8-wide 2-input AOI gate.
Logic equation for Fig.4:
OB = I0A 1A + I2A 3A + I4A
I
I
I
5A + I6A
I
7A + I0B
I
1B + I2B I3B + I4B I5B + I6B I7B
January 1995
5
相关型号：
HEF4086BT-T
IC 4000/14000/40000 SERIES, 8-INPUT AND-OR-INVERT GATE, PDSO14, PLASTIC, SO-14, Gate
NXP
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