MCM6706RJ6 [NXP]
IC,SRAM,32KX8,BICMOS-TTL,SOJ,32PIN,PLASTIC;
| 型号： | MCM6706RJ6 |
| 厂家： | 
NXP |
| 描述： | IC,SRAM,32KX8,BICMOS-TTL,SOJ,32PIN,PLASTIC 信息通信管理 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6706R/D
MCM6706R
32K x 8 Bit Static Random Access
Memory
The MCM6706R is a 262,144 bit static random access memory organized as
32,768 words of 8 bits, fabricated using high performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
J PACKAGE
300 MIL SOJ
CASE 857–02
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706R meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
PIN ASSIGNMENT
A0
A1
A2
A3
NC
1
32
31
30
29
28
27
•
•
•
•
•
Single 5.0 V ± 10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: MCM6706R–6 = 6 ns
MCM6706R–7 = 7 ns
A14
A13
A12
G
2
3
4
E
DQ0
DQ1
5
MCM6706R–8 = 8 ns
Center Power and I/O Pins for Reduced Noise
DQ7
DQ6
6
•
7
26
25
24
23
22
21
20
V
V
8
CC
SS
V
V
BLOCK DIAGRAM
9
SS
CC
DQ2
DQ3
W
DQ5
DQ4
A11
10
11
12
13
14
15
16
A
A
A
V
V
CC
SS
A4
A10
A9
A
MEMORY
A5
A6
A7
19
18
17
ROW
DECODER
MATRIX
512 ROWS x 64 x 8
COLUMNS
A
A
A
A
A
A8
NC
PIN NAMES
DQ0
A0 – A14 . . . . . . . . . . . . . . . . . . Address
W . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ7 . . . . . . . . Data Input/Output
COLUMN I/O
INPUT
DATA
CONTROL
COLUMN DECODER
DQ7
E
V
V
. . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . Ground
CC
SS
A
A
A
A
A
A
NC . . . . . . . . . . . . . . . . . No Connection
W
G
REV 1
5/95
Motorola, Inc. 1995
For More Information On This Product,
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Freescale Semiconductor, Inc.
TRUTH TABLE
E
G
W
Mode
I/O Pin
Cycle
H
L
L
L
X
H
L
X
H
H
L
Not Selected
Read
High–Z
High–Z
—
—
Read
Write
D
Read Cycle
Write Cycle
out
X
D
in
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol
Power Supply Voltage
Voltage Relative to V
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
thatnormal precautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
andtransverse air flow of at least500linearfeet
per minute is maintained.
Value
– 0.5 to + 7.0
– 0.5 to V + 0.5
Unit
V
V
CC
for Any Pin
V , V
in out
V
SS
CC
Except V
CC
Output Current
I
± 30
mA
W
out
Power Dissipation
P
D
2.0
Temperature Under Bias
Operating Temperature
T
– 10 to + 85
0 to + 70
°C
°C
°C
bias
T
A
Storage Temperature — Plastic
T
stg
– 55 to + 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
4.5
2.2
Typ
5.0
—
Max
Unit
V
Supply Voltage (Operating Voltage Range)
Input High Voltage
V
CC
5.5
V
IH
V
V
+ 0.3*
CC
Input Low Voltage
V
IL
—
0.8
V
– 0.5**
*V (max) = V
IH CC
IL
+ 0.3 V dc; V (max) = V + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
IH CC
**V (min) = – 0.5 V dc @ 30.0 mA; V (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
IL
DC CHARACTERISTICS
Parameter
Symbol
Min
—
Max
± 1.0
± 1.0
—
Unit
µA
µA
V
Input Leakage Current (All Inputs, V = 0 to V
in CC
)
I
lkg(I)
Output Leakage Current (E = V or G = V , V
= 0 to V
CC
)
I
lkg(O)
—
IH
IH out
Output High Voltage (I
OH
= – 4.0 mA)
V
OH
2.4
—
Output Low Voltage (I
OL
= + 8.0 mA)
V
OL
0.4
V
POWER SUPPLY CURRENTS
Parameter
= 0 mA, V
Symbol
6706R–6
6706R–7
200
6706R–8
195
Unit
Notes
1, 2, 3
1, 2. 3
AC Active Supply Current (I
out
= max, f = f
max
)
I
205
95
mA
mA
mA
CC
CCA
AC Standby Current (E = V , V
IH CC
= max, f = f
)
I
90
85
max
SB1
CMOS Standby Current (V
CC
= max, f = 0 MHz, E ≥ V
≤ V , or ≥ V – 0.2 V)
– 0.2 V,
I
20
20
20
CC
SB2
V
in
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (V /V , t /t , pulse level 0 to 3.0 V, V = 3.0 V).
SS CC
IH IL r f
IH
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
MCM6706R
2
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CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Address Input Capacitance
Symbol
Max
Unit
pF
C
C
5
6
6
in
in
Control Pin Input Capacitance (E, G, W)
I/O Capacitance
pF
C
pF
out
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLE (See Notes 1 and 2)
MCM6706R–6
MCM6706R–7
MCM6706R–8
Parameter
Symbol
Min
6
Max
—
6
Min
7
Max
—
7
Min
8
Max
—
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read Cycle Time
t
3
AVAV
Address Access Time
t
—
—
—
3
—
—
—
3
—
—
—
3
AVQV
Chip Enable Access Time
t
6
7
8
ELQV
GLQV
AXQX
Output Enable Access Time
t
t
4
4
4
Output Hold from Address Change
Chip Enable Low to Output Active
Chip Enable High to Output High–Z
Output Enable Low to Output Active
Output Enable High to Output High–Z
—
—
3
—
—
3.5
—
3.5
—
—
4
t
3
3
3
4 ,5, 6
4, 5, 6
4, 5, 6
4, 5, 6
ELQX
EHQZ
GLQX
GHQZ
t
t
0
0
0
0
—
3
0
0
—
4
t
0
0
0
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, t
device to device.
max < t
min, and t
max < t min, both for a given device and from
GLQX
EHQZ
ELQX
GHQZ
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = V , G = V ).
IL
IL
8. Addresses valid prior to or coincident with E going low.
AC TEST LOADS
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
requireit). Ontheotherhand, responsesfrom
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
+5 V
480
Ω
OUTPUT
OUTPUT
255
Z
= 50 Ω
R
= 50 Ω
0
L
Ω
5 pF
V
= 1.5 V
L
Figure 1A
Figure 1B
MCM6706R
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READ CYCLE 1 (See Note 7)
t
AVAV
A (ADDRESS)
Q (DATA OUT)
t
AXQX
PREVIOUS DATA VALID
DATA VALID
t
AVQV
READ CYCLE 2 (See Note 8)
t
AVAV
A (ADDRESS)
t
ELQV
E (CHIP ENABLE)
t
t
EHQZ
t
ELQX
G (OUTPUT ENABLE)
GHQZ
t
GLQV
t
GLQX
Q (DATA OUT)
DATA VALID
t
AVQV
MCM6706R
4
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WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6706R–6
MCM6706R–7
MCM6706R–8
Parameter
Write Cycle Time
Symbol
Min
6
Max
—
Min
7
Max
—
Min
8
Max
—
Unit
ns
Notes
t
3
AVAV
Address Setup Time
t
0
—
0
—
0
—
ns
AVWL
Address Valid to End of Write
Write Pulse Width
t
6
—
7
—
8
—
ns
AVWH
t
,
6
—
7
—
8
—
ns
WLWH
t
WLEH
Data Valid to End of Write
Data Hold Time
t
t
3
0
0
3
0
—
—
3.5
0
—
—
4
0
0
3
0
—
—
4
ns
ns
ns
ns
ns
DVWH
WHDX
Write Low to Data High–Z
Write High to Output Active
t
3.5
—
0
3.5
—
4, 5, 6
4, 5, 6
WLQZ
t
3
—
—
WHQX
Write Recovery Time
NOTES:
t
—
0
—
WHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
5. Parameter is sampled and not 100% tested.
6. At any given voltage and temperature, t
max is < t min both for a given device and from device to device.
WHQX
WLQZ
WRITE CYCLE 1
t
AVAV
A (ADDRESS)
t
t
AVWH
WHAX
E (CHIP ENABLE)
t
WLEH
t
WLWH
W (WRITE ENABLE)
t
AVWL
t
t
WHDX
DVWH
D (DATA IN)
DATA VALID
t
WLQZ
HIGH–Z
HIGH–Z
Q (DATA OUT)
t
WHQX
MCM6706R
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WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6706R–6
MCM6706R–7
MCM6706R–8
Parameter
Write Cycle Time
Symbol
Min
6
Max
—
Min
7
Max
—
Min
8
Max
—
Unit
ns
Notes
t
3
AVAV
Address Setup Time
t
0
—
0
—
0
—
ns
AVEL
Address Valid to End of Write
Chip Enable to End of Write
t
6
—
7
—
8
—
ns
AVEH
t
,
5
—
6
—
7
—
ns
4,5
ELWH
t
ELEH
Data Valid to End of Write
Data Hold Time
t
t
3
0
0
—
—
—
3.5
0
—
—
—
4
0
0
—
—
—
ns
ns
ns
DVEH
EHDX
Write Recovery Time
NOTES:
t
0
EHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
t
AVAV
A (ADDRESS)
t
AVEH
t
ELEH
E (CHIP ENABLE)
t
t
t
EHAX
AVEL
ELWH
W (WRITE ENABLE)
D (DATA IN)
t
t
EHDX
DVEH
DATA VALID
HIGH–Z
Q (DATA OUT)
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6706R
X
XX XX
Motorola Memory Prefix
Part Number
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (6 = 6 ns, 7 = 7 ns, 8 = 8 ns)
Package (J = 300 mil SOJ)
Full Part Numbers — MCM6706J6
MCM6706RJ6R2
MCM6706RJ7
MCM6706RJ7R2
MCM6706RJ8
MCM6706RJ8R2
MCM6706R
6
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PACKAGE DIMENSIONS
32–LEAD
300 MIL SOJ
CASE 857–02
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DATUM PLANE -X- LOCATED AT TOP OF MOLD
PARTING LINE AND COINCIDENT WITH TOP OF
LEAD, WHERE LEAD EXITS BODY.
4. TO BE DETERMINED AT PLANE -X-.
5. TO BE DETERMINED AT PLANE -T-.
6. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
F
32 PL
S
S
0.17(0.007)
NOTE 4
A
32
1
17
16
M
32 PL
NOTE 5
D
7. 857-01 IS OBSOLETE, NEW STANDARD 857-02.
S
S
0.17(0.007)
P
0.17(0.007)
A
MILLIMETERS
INCHES
DIM
A
B
C
D
E
MIN
20.83
7.50
3.26
0.41
2.24
0.67
MAX
21.08
7.74
3.75
0.50
2.48
0.81
MIN
MAX
0.830
0.305
0.148
0.020
0.098
0.032
-A-
S
S
B
B
0.820
0.295
0.128
0.016
0.088
0.026
L
G
-B-
-X-
-T-
NOTE 3
C
F
E
G
K
L
1.27 BSC
0.050 BSC
0.10 (0.004)
SEATING
PLANE
0.89
1.14
0.035
0.045
DETAIL Z
K
R
S
RADIUS
NOTE 5
0.64 BSC
0.025 BSC
N
P
R
S
0.76
8.38
6.60
0.77
1.14
8.64
6.86
1.01
0.030
0.330
0.260
0.030
0.045
0.340
0.270
0.040
S
S
0.25 (0.010)
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM6706R
7
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Literature Distribution Centers:
USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
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MCM6706R/D
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