MPC92469AC [NXP]
400MHz, OTHER CLOCK GENERATOR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32;
| 型号： | MPC92469AC |
| 厂家： | 
NXP |
| 描述： | 400MHz, OTHER CLOCK GENERATOR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32 时钟 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC92469
Rev 1, 06/2005
Freescale Semiconductor
Technical Data
400 MHz Low Voltage PECL
Clock Synthesizer w/Spread
Spectrum
MPC92469
The MPC92469 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance tele-
com, networking and computing applications. With output frequencies from
25 MHz to 400 MHz and the support of differential PECL output signals the
device meets the needs of the most demanding clock applications.
400 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
w/SPREAD SPECTRUM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
25 MHz to 400 MHz synthesized clock output signal
Differential PECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
Spread Spectrum output for EMI reduction
3.3 V power supply
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
32-lead LQFP packaging
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
32-lead Pb-free package available
SiGe Technology
Ambient temperature range 0°C to +70°C
Pin compatible to the MC12429, MPC9229 and MPC92429
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 400
to 800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator
frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 2⋅M times the reference frequency
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (400 to 800 MHz). The M-value
must be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 Ω to VCC – 2.0 V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating.
The serial interface centers on a eighteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAM-
MING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]
bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
XTAL_IN
XTAL_OUT
Ref
÷2
÷1
÷2
÷4
÷8
VCO
XTAL
÷16
00
01
10
11
FOUT
FOUT
10 – 20 MHz
PLL
400 – 800 MHz
OE
FB
SYNC
÷0 TO ÷511
9-BIT M-DIVIDER
TEST
TEST
3
2
9
V
CC
M-LATCH
N-LATCH
T-LATCH
SSM-LATCH
LE
P/S
P_LOAD
S_LOAD
0
1
0
1
BITS 7-8
BITS 9-17
BITS 4-6
BITS 0-3
S_DATA
S_CLOCK
18-BIT SHIFT REGISTER
V
CC
M[0:8]
N[1:0]
OE
Figure 1. MPC92469 Logic Diagram
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
NC
GND
TEST
M[3]
V
M[2]
CC
CC
V
M[1]
MPC92469
GND
M[0]
FOUT
P_LOAD
OE
FOUT
V
XTAL_OUT
CC
1
2
3
4
5
6
7
8
Figure 2. MPC92469 32-Lead Package Pinout
(Top View)
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
2
Table 1. Pin Configurations
Pin
XTAL_IN, XTAL_OUT
FOUT, FOUT
TEST
I/O
Default
Type
Function
Analog
Crystal oscillator interface.
Output
Output
Input
LVPECL Differential clock output.
LVCMOS Test and device diagnosis output.
LVCMOS Serial configuration control input.
S_LOAD
0
1
This inputs controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition.
P_LOAD
Input
LVCMOS Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive.
S_DATA
S_CLOCK
M[0:8]
Input
Input
Input
0
0
1
LVCMOS Serial configuration data input.
LVCMOS Serial configuration clock input.
LVCMOS Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
OE
Input
Input
1
1
LVCMOS Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD.
LVCMOS Output enable (active high).
The output enable is synchronous to the output clock to eliminate the possibility
of runt pulses on the F
output. OE = L low stops F
in the logic low state
OUT
OUT
(F
= L, FOUT = H).
OUT
GND
Supply
Supply
Supply
Supply
Ground
Negative power supply (GND).
V
V
Positive power supply for I/O and core. All V pins must be connected to the
CC
CC
CC
positive power supply for correct operation.
V
Supply
Supply
V
PLL positive power supply (analog power supply).
CC_PLL
CC
Table 2. Output Frequency Range and PLL Post-Divider N
N
Output Division
Output Frequency Range
1
0
0
1
1
0
0
1
0
1
1
2
4
8
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
25 – 50 MHz
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
– 2
Max
Unit
V
Condition
V
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
V
TT
CC
MM
HBM
LU
200
2000
200
V
V
mA
pF
C
Input Capacitance
4.0
Inputs
IN
θ
LQFP 32 Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
JA
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
JESD 51-6, 2S2P multilayer test board
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
θ
LQFP 32 Thermal Resistance Junction to Case
23.0
26.3
°C/W MIL-SPEC 883E
JC
Method 1012.1
Table 4. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
–0.3
–0.3
–0.3
Max
Unit
V
Condition
V
Supply Voltage
3.9
CC
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
V
V
+ 0.3
V
IN
CC
CC
V
+ 0.3
V
OUT
I
±20
mA
mA
°C
IN
I
±50
OUT
T
–65
125
S
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE)
V
Input High Voltage
Input Low Voltage
2.0
V
+ 0.3
V
V
LVCMOS
LVCMOS
= V or GND
IH
CC
V
I
0.8
IL
(1)
Input Current
±200
µA
V
IN
IN
CC
(2)
Differential Clock Output F
OUT
(3)
V
Output High Voltage
V
V
–1.02
V
V
–0.74
V
V
LVPECL
LVPECL
OH
CC
CC
CC
(3)
V
Output Low Voltage
–1.95
–1.60
OL
CC
Test and Diagnosis Output TEST
(3)
V
Output High Voltage
2.0
V
V
I
I
= –0.8 mA
= 0.8 mA
OH
OH
OH
(3)
V
Output Low Voltage
0.55
OL
Supply Current
I
Maximum PLL Supply Current
Maximum Supply Current
TBD
TBD
mA
V
Pins
CC_PLL
CC_PLL
I
mA All V Pins
CC
CC
1. Inputs have pull-down resistors affecting the input current.
2. Outputs terminated 50 Ω to V = V – 2 V.
TT
CC
3. The MPC92469 TEST output levels are compatible to the MC12429 output levels.
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
4
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1)
Symbol
Characteristics
Min
10
Typ
Max
20
Unit
MHz
MHz
Condition
f
Crystal Interface Frequency Range
XTAL
(2)
f
VCO Frequency Range
400
800
VCO
MAX
f
Output Frequency
N = 00 (÷1)
N = 01 (÷2)
N = 10 (÷4)
N = 11 (÷8)
200
100
50
400
200
100
50
MHz
MHz
MHz
MHz
25
DC
Output Duty Cycle
45
0.05
0
50
55
0.3
10
%
ns
t , t
Output Rise/Fall Time
20% to 80%
r
f
(3)
f
Serial Interface Programming Clock Frequency
MHz
ns
S_CLOCK
t
Minimum Pulse Width
Setup Time
(S_LOAD, P_LOAD)
50
P,MIN
t
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
ns
ns
S
S
t
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
t
Cycle-to-Cycle Jitter
Period Jitter
50
50
ps
JIT(CC)
t
ps
JIT(PER)
Phase Noise
dBC/Hz
ms
t
Maximum PLL Lock Time
10
LOCK
SSM
Spread Spectrum Modulation Frequency
Spread Spectrum Modulation Deviation
32
KHz
f
= 16
XTAL
fmod
SSM
SS[3:0] = 1010
SS[3:0] = 1100
SS[3:0] = 0010
SS[3:0] = 0100
-1.0
-2.0
+-1.0
+-2.0
%
%
%
%
f
= 200 MHz
out
dev
1. AC characteristics apply for parallel output termination of 50 Ω to V
.
TT
2. The input frequency f
and the PLL feedback divider M must match the VCO frequency range: f
= f x M ÷ 8.
XTAL
XTAL
VCO
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
5
PROGRAMMING INTERFACE
match the VCO frequency range of 400 to 800 MHz in order
Programming the MPC92469
to achieve stable PLL operation:
Programming the MPC92469 amounts to properly
configuring the internal PLL dividers to produce the desired
synthesized frequency at the output. The output frequency
can be represented by this formula:
MMIN = fVCO,MIN ÷ fXTAL * 8 and
(2)
(3)
MMAX = fVCO,MAX ÷ fXTAL * 8
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between
M = 200 and M = 400. Table 7 shows the usable VCO
frequency and M divider range for other example input
frequencies. Assuming that a 16 MHz input frequency is
used, equation 1 reduces to:
FOUT = (fXTAL ÷ 16) x (M) ÷ (N)
(1)
where fXTAL is the crystal frequency, M is the PLL feedback-
divider and N is the PLL post-divider. The input frequency and
the selection of the feedback divider M is limited by the
VCO-frequency range. fXTAL and M must be configured to
FOUT = M ÷ N
(4)
Table 7. MPC9230 Frequency Operating Range
Output frequency for f
= 16 MHz and for N =
VCO frequency for an crystal interface frequency of
XTAL
M
M[8:0]
10
12
14
16
18
20
1
2
4
16
160 010100000
170 010101010
180 010110100
190 010111110
200 011001000
210 011010010
220 011011100
230 011100110
240 011110000
250 011111010
260 100000100
270 100001110
280 100011000
290 100100010
300 100101100
310 100110110
320 101000000
330 101001010
340 101010100
350 101011110
360 101101000
370 101110010
380 101111100
390 110000110
400 110010000
410 110011010
420 110100100
430 110101110
440 110111000
450 111000010
510 111111110
400
425
450
475
500
525
550
575
600
625
650
675
700
725
750
775
800
405
427.5
450
400
420
440
460
480
500
520
540
560
580
600
620
640
660
680
700
720
740
760
780
800
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
100
105
110
115
120
125
130
135
140
145
150
155
160
165
170
175
180
185
190
195
200
50
52.5
55
25
472.5
495
26.25
27.50
28.75
30
402.5
420
517.5
540
57.5
60
437.5
455
562.5
585
62.5
65
31.25
32.50
33.75
35
405
420
435
450
465
480
495
510
525
540
555
570
585
600
615
630
645
660
675
765
472.5
490
607.5
630
67.5
70
507.5
525
652.5
675
72.5
75
36.25
37.5
38.75
40
542.5
560
697.5
720
77.5
80
400
412.5
425
577.5
595
742.5
765
82.5
85
41.25
42.5
43.75
45
437.5
450
612.5
630
787.5
87.5
90
462.5
475
647.5
665
92.5
95
46.25
47.5
48.75
50
487.5
500
682.5
700
97.5
100
512.5
525
717.5
735
537.5
550
752.5
770
562.5
637.5
787.5
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
6
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Example Frequency Calculation for an 16 MHz Input
Frequency
If an output frequency of 131 MHz was desired the
following steps would be taken to identify the appropriate M
and N values. According to Table 8, 131 MHz falls in the
frequency set by an value of 2 so N[1:0] = 01. For N = 2 the
output frequency is FOUT = M ÷ 2 and M = FOUT x 2.
Therefore M = 2 x 131 = 262, so M[8:0] = 100000110.
Following this procedure a user can generate any whole
frequency between 25 MHz and 400 MHz. Note than for
N > 2 fractional values of can be realized. The size of the
programmable frequency steps (and thus the indicator of the
fractional output frequencies achievable) will be equal to:
Table 8. Output Frequency Range for fXTAL = 16 MHz
N
F
F
Range
F
Step
OUT
OUT
OUT
1
0
0
1
1
0
0
1
0
1
Value
1
2
4
8
M
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
25 – 50 MHz
1 MHz
M÷2
M÷4
M÷8
500 kHz
250 kHz
125 kHz
fSTEP = fXTAL ÷ 16 ÷ N
(5)
APPLICATIONS INFORMATION
performance verification of the MPC92469 itself. However
Using the Parallel and Serial Interface
the PLL bypass mode may be of interest at the board level for
functional debug. When T[2:0] is set to 110 the MPC92469 is
placed in PLL bypass mode. In this mode the S_CLOCK input
is fed directly into the M and N dividers. The N divider drives
the FOUT differential pair and the M counter drives the TEST
output pin. In this mode the S_CLOCK input could be used for
low speed board level functional test or debug. Bypassing the
PLL and driving FOUT directly gives the user more control on
the test clocks sent through the clock tree. Because the
S_CLOCK is a CMOS level the input frequency is limited to
200 MHz. This means the fastest the FOUT pin can be toggled
via the S_CLOCK is 100 MHz as the divide ratio of the
Post-PLL divider is 2 (if N = 1). Note that the M counter output
on the TEST output will not be a 50% duty cycle.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOAD signal such that a LOW-to-HIGH transition
will latch the information present on the M[8:0] and N[1:0]
inputs into the M and N counters. When the P_LOAD signal
is LOW the input latches will be transparent and any changes
on the M[8:0] and N[1:0] inputs will affect the FOUT output
pair. To use the serial port the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two and
the M register with the final eight bits of the data stream on
the S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after
the shift register is fully loaded will transfer the divide values
into the counters. The HIGH-to-LOW transition on the
S_LOAD input will latch the new divide values into the
counters. Figure 3 illustrates the timing diagram for both a
parallel and a serial load of the MPC92469 synthesizer.
M[8:0] and N[1:0] are normally specified once at power-up
through the parallel interface, and then possibly again
through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine-tune the clock as the ability to control the serial interface
becomes available.
Table 9. Test and Debug Configuration for TEST
T[2:0]
TEST Output
T2
0
T1
0
T0
0
(1)
18-bit shift register out
Logic 1
0
0
1
0
1
0
f
÷ 16
XTAL
0
1
1
M-Counter out
FOUT
1
0
0
1
0
1
Logic 0
Using the Test and Diagnosis Output TEST
1
1
0
M-Counter out in PLL-bypass mode
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. Although it is possible to select the node
that represents FOUT, the CMOS output is not able to toggle
fast enough for higher output frequencies and should only be
used for test and diagnosis. The T2, T1 and T0 control bits
are preset to ‘000' when P_LOAD is LOW so that the PECL
FOUT outputs are as jitter-free as possible. Any active signal
on the TEST output pin will have detrimental affects on the
jitter of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin. Most of the signals
available on the TEST output pin are useful only for
1
1
1
FOUT ÷ 4
1. Clocked out at the rate of S_CLOCK.
Table 10. Debug Configuration for PLL Bypass(1)
Output
Configuration
F
S_CLOCK ÷ N
OUT
(2)
TEST
M-Counter out
1. T[2:0] = 110. AC specifications do not apply in PLL bypass
mode.
2. Clocked out at the rate of S_CLOCK÷(4⋅N)
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
7
S_CLOCK
S_DATA
S_LOAD
SS3 SS2 SS1 SS0 T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3
M2 M1
M0
First
Bit
Last
Bit
M[8:0]
N[1:0]
M,
N
P_LOAD
Figure 3. Serial Interface Timing Diagram
are labeled SS3, SS2, SS1 and SS0. The initial state of SS3,
SS2, SS1 and SS0 is 0, 0, 0, 0 which places the MPC92469
in the mode of spread spectrum off. Additionally a parallel
load will result in spread spectrum modulation being off. The
MPC92469 offers down-spread or center spread.
Table 11. SSM Operation
SS Bit Pattern
Operation
SS3
0
SS2
0
SS1
0
SS0
0
Mode
%
Power Supply Filtering
off
0
The MPC92469 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCC_PLL pin impacts the device
characteristics. The MPC92469 provides separate power
supplies for the digital circuitry (VCC) and the internal PLL
(VCC_PLL) of the device. The purpose of this design technique
is to try and isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked
loop. In a controlled environment such as an evaluation
board, this level of isolation is sufficient. However, in a digital
system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may
be required. The simplest form of isolation is a power supply
filter on the VCC_PLL pin for the MPC92469. Figure 4
illustrates a typical power supply filter scheme. The
MPC92469 is most susceptible to noise with spectral content
in the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop that
will be seen between the VCC supply and the VCC_PLL pin of
the MPC92469. From the data sheet, the VCC_PLL current
(the current sourced through the VCC_PLL pin) is maximum
TBD mA, assuming that a minimum of 2.835 V must be
maintained on the VCC_PLL pin. The resistor shown in
Figure 4 must have a resistance of 10-15 Ω to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 kHz. As the noise
frequency crosses the series resonant point of an individual
capacitor its overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
0
0
0
1
center
center
center
center
center
center
center
off
+-0.5%
+-1%
+-1.5%
+-2.%
+-2.5%
+-3%
+-3.5%
0
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
down
down
down
down
down
down
down
-0.5%
-1%
1
0
1
0
1
0
1
1
-1.5%
-2.0%
-2.5%
-3.0%
-3.5%
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Spread Spectrum Modulation
The MPC92469 offers the option of a spread spectrum
modulated output clock. The spread spectrum is controlled
via 4 additional bits (w/respect to the MPC9229) in the serial
bit stream. These four bits configure the SSM to be enabled
and the amount of spread modulation to be selected. See
Table 11 for the definition of the three bits. The four additional
bits are added at the beginning of the serial data stream and
bandwidth of the PLL. Generally, the resistor/capacitor filter
will be cheaper, easier to implement and provide an adequate
level of supply filtering. A higher level of attenuation can be
achieved by replacing the resistor with an appropriate valued
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
8
inductor. A 1000 µH choke will show a significant impedance
at 10 kHz frequencies and above. Because of the current
draw and the voltage that must be maintained on the VCC_PLL
pin, a low DC resistance inductor is required (less than 15 Ω).
The crystal should be located as close to the MPC92469
XTAL_IN and XTAL_OUT pins as possible to avoid any board
level parasitic.
Table 12 below specifies the performance requirements of
the crystals to be used with the MPC92469.
R
= 10-15 Ω
F
V
V
CC_PLL
Table 12. Recommended Crystal Specifications
CC
C
C
= 22 µF
Parameter
Value
Fundamental AT Cut
Parrallel Resonance
5–7 pF
2
F
MPC92469
Crystal Cut
Resonance
V
CC
C , C = 0.01...0.1 µF
Shunt Capacitance (C )
L
C
1
2
1
Load Capacitance (C )
10 pF
O
Equivalent Series Resistance (ESR)
20 to 60 Ω
Figure 4. VCC_PLL Power Supply Filter
Using the On-Board Crystal Oscillator
The MPC92469 features a fully integrated Pierce oscillator
to minimize system implementation costs. Other than the
addition of a crystal no external components are required.The
crystal selection should be 10 to 20 MHz, parallel resonant
type with a load specification of CL = 10 pF.
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
9
PACKAGE DIMENSIONS
PAGE 1 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
10
PACKAGE DIMENSIONS
PAGE 2 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC92469
11
Advanced Clock Drivers Devices
Freescale Semiconductor
PACKAGE DIMENSIONS
PAGE 3 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
12
NOTES
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
13
NOTES
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
14
NOTES
MPC92469
Advanced Clock Drivers Devices
Freescale Semiconductor
15
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MPC92469
Rev. 1
06/2005
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