N74ALS374N [PHILIPS]
D Flip-Flop, 8-Func, Positive Edge Triggered, TTL, PDIP20;
| 型号： | N74ALS374N |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | D Flip-Flop, 8-Func, Positive Edge Triggered, TTL, PDIP20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ALS373/74ALS374
Latch/flip–flop
Product specification
IC05 Data Handbook
1991 Feb 08
Philips
Semiconductors
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373/74ALS374
74ALS373 Octal transparent latch (3-State)
74ALS374 Octal D flip-flop (3-State)
FEATURES
• 8-bit transparent latch – 74ALS373
DESCRIPTION
The 74ALS373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
• 8-bit positive edge triggered register – 74ALS374
• 3-State output buffers
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
• Common 3-State output register
• Independent register and 3-State buffer operation
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
TYPICAL
TYPICAL
PROPAGATION DELAY
SUPPLY CURRENT
(TOTAL)
TYPE
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
74ALS373
6.0ns
14mA
When OE is High, the outputs are in High impedance “off” state,
which means they will neither drive nor load the bus.
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPICAL
TYPE
The 74ALS374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
f
MAX
74ALS374
50MHz
17mA
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
ORDERING INFORMATION
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
ORDER CODE
DRAWING
NUMBER
DESCRIPTION
COMMERCIAL RANGE
V
amb
= 5V ±10%,
= 0°C to +70°C
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in High impedance “off” state, which means they will neither
drive nor load the bus.
CC
T
20-pin plastic DIP
20-pin plastic SOL
74ALS373N, 74ALS374N
74ALS373D, 74ALS374D
SOT146-1
SOT163-1
20-pin plastic SSOP
Type II
74ALS373DB, 74ALS374DB SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
D0 – D7
E (74ALS373)
OE
Data inputs
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
130/240
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
2.6mA/24mA
Enable input (active-High)
Output enable inputs (active-Low)
Clock pulse input (active rising edge)
3-State outputs
CP (74ALS374)
Q0 – Q7
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
2
1991 Feb 08
853–1243 01670
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373/74ALS374
PIN CONFIGURATION – 74ALS373
PIN CONFIGURATION – 74ALS374
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20
V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
GND 10
GND 10
11 E
SF00250
SF00251
SF00252
SF00253
SF00254
SC00098
LOGIC SYMBOL – 74ALS373
LOGIC SYMBOL – 74ALS374
3
4
7
8
13 14 17 18
3
4
7
8
13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
11
E
11
CP
OE
OE
1
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
5
6
9 12 15 16 19
2
5
6
9 12 15 16 19
V
= Pin 20
CC
V
= Pin 20
CC
GND = Pin 10
GND = Pin 10
IEC/IEEE SYMBOL – 74ALS373
IEC/IEEE SYMBOL – 74ALS374
1
1
EN1
EN1
11
11
EN2
C1
3
2
3
2
2D
1
2D
1
5
6
9
5
6
9
4
4
7
7
8
8
13
12
15
16
19
13
12
15
16
19
14
17
18
14
17
18
3
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373/74ALS374
LOGIC DIAGRAM – 74ALS373
D0
D1
D2
D3
D4
13
D5
14
D6
17
D7
3
4
7
8
18
D
E
D
E
D
E
D
E
D
E
D
E
D
E
D
E
Q
Q
Q
Q
Q
Q
Q
Q
11
1
E
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
Q0
Q1
Q2
Q3
V
= Pin 20
CC
GND = Pin 10
SF00256
FUNCTION TABLE – 74ALS373
INPUTS
OUTPUTS
INTERNAL REGISTER
OPERATING MODE
OE
L
E
H
H
↓
Dn
L
Q0 – Q7
L
H
L
H
Enable and read register
L
H
l
L
L
L
Latch and read register
Hold
L
↓
h
H
H
L
L
X
NC
NC
Dn
NC
Z
H
H
L
X
Disable outputs
H
Dn
Z
H = High-voltage level
h
L
l
=
=
=
High state must be present one setup time before the High-to-Low enable transition
Low-voltage level
Low state must be present one setup time before the High-to-Low enable transition
NC= No change
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-Low enable transition
4
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373/74ALS374
LOGIC DIAGRAM – 74ALS374
D0
D1
D2
D3
D4
13
D5
14
D6
17
D7
3
4
7
8
18
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
Q
Q
Q
Q
Q
Q
Q
Q
11
1
CP
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
V
= Pin 20
CC
GND = Pin 10
Q0
Q1
Q2
Q3
SF00257
FUNCTION TABLE – 74ALS374
INPUTS
OUTPUTS
INTERNAL REGISTER
OPERATING MODE
OE
L
CP
↑
Dn
l
Q0 – Q7
L
L
H
Load and read register
Hold
L
↑
h
H
L
↑
X
NC
NC
Dn
NC
Z
H
H
↑
X
Disable outputs
↑
Dn
Z
H = High-voltage level
h
L
l
=
=
=
High state must be present one setup time before the Low-to-High clock transition
Low-voltage level
Low state must be present one setup time before the Low-to-High clock transition
NC= No change
X
Z
↑
=
=
=
=
Don’t care
High impedance “off” state
Low-to-High clock transition
Not Low-to-High clock transition
↑
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
Supply voltage
Input voltage
Input current
V
IN
V
I
IN
mA
V
V
OUT
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
48
CC
I
mA
°C
°C
OUT
T
amb
0 to +70
T
stg
–65 to +150
5
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373/74ALS374
RECOMMENDED OPERATING CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
4.5
NOM
MAX
V
CC
Supply voltage
5.0
5.5
V
V
V
IH
High-level input voltage
Low-level input voltage
Input clamp current
2.0
V
0.8
–18
–2.6
24
V
IL
IK
I
mA
mA
mA
°C
I
High-level output current
Low-level output current
Operating free-air temperature range
OH
I
OL
T
amb
0
+70
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
– 2
TYP
MAX
I
= –0.4mA
V
CC
V
V
OH
V
V
= ±10%, V = MAX,
IL
CC
IH
V
OH
High-level output voltage
= MIN
I
= MAX
= 12mA
= 24mA
2.4
3.2
0.25
0.35
–0.73
OH
I
0.40
0.50
–1.2
0.1
V
OL
OL
V
V
= MIN, V = MAX,
IL
CC
IH
V
OL
Low-level output voltage
= MIN
I
V
V
IK
Input clamp voltage
V
CC
V
CC
V
CC
= MIN, I = I
IK
V
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
mA
µA
mA
mA
I
I
IH
= MAX, V = 2.7V
20
I
74ALS373
–0.1
–0.2
Low-level input
I
IL
V
= MAX, V = 0.4V
I
CC
CC
current
74ALS374
Off-state output current,
High-level voltage applied
I
V
= MAX, V = 2.7V
20
µA
µA
OZH
I
Off-state output current,
Low-level voltage applied
I
V
V
= MAX, V = 0.4V
–20
OZL
CC
I
3
I
O
Output current
= MAX, V = 2.25V
–30
–112
16
mA
mA
mA
mA
mA
mA
mA
CC
O
I
I
7
CCH
I
14
17
11
19
20
25
74ALS373
74ALS374
V
CC
= MAX
= MAX
CCL
CCZ
CCH
27
I
Supply current (total)
CC
I
19
I
29
V
CC
CCL
I
31
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
6
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373/74ALS374
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
SYMBOL
PARAMETER
TEST CONDITION
UNIT
C = 50pF, R = 500Ω
L
L
MIN
MAX
t
t
Propagation delay
Dn to Qn
2.0
2.0
12.0
14.0
PLH
PHL
Waveform 3
Waveform 2
ns
ns
ns
t
t
Propagation delay
E to Qn
3.0
3.0
14.0
14.0
PLH
PHL
74ALS373
t
Output enable time
to High or Low level
Waveform 6
Waveform 7
2.0
3.0
14.0
14.0
PZH
t
PZL
t
t
Output disable time
from High or Low level
Waveform 6
Waveform 7
2.0
2.0
10.0
12.0
PHZ
PLZ
ns
MHz
ns
f
Maximum clock frequency
Waveform 1
Waveform 1
50
MAX
t
t
Propagation delay
CP to Qn
3.0
4.0
12.0
14.0
PLH
PHL
74ALS374
t
t
Output enable time
to High or Low level
Waveform 6
Waveform 7
3.0
3.0
9.0
11.0
PZH
PZL
ns
ns
t
Output disable time
from High or Low level
Waveform 6
Waveform 7
2.0
3.0
10.0
12.0
PHZ
t
PLZ
AC SETUP REQUIREMENTS
LIMITS
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
SYMBOL
PARAMETER
TEST CONDITION
UNIT
C = 50pF, R = 500Ω
L
L
MIN
MAX
t
t
(H)
Setup time, High or Low
Dn to E
6.0
6.0
su
Waveform 4
ns
(L)
su
74ALS373
74ALS374
t (H)
t (L)
h
Hold time, High or Low
Dn to E
6.0
6.0
h
Waveform 4
Waveform 2
Waveform 5
ns
ns
ns
t (H)
w
E Pulse width, High
10.0
t
t
(H)
Setup time, High or Low
Dn to CP
6.0
6.0
su
(L)
su
t (H)
Hold time, High or Low
Dn to CP
1.0
1.0
h
Waveform 5
Waveform 1
ns
ns
t (L)
h
t (H)
CP Pulse width,
High or Low
10.0
10.0
w
t (L)
w
7
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373/74ALS374
AC WAVEFORMS
For all waveforms, V = 1.3V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
max
t
(H)
w
CP
Qn
V
V
E
V
M
M
V
V
M
V
t
M
M
M
t
(H)
w
t
t
(L)
t
PHL
PLH
w
t
PHL
PLH
V
Qn
V
V
V
M
M
M
M
SF00258
SF00259
Waveform 1. Propagation Delay for Clock Input to Output,
Clock Pulse Widths, and Maximum Clock Frequency
Waveform 2. Propagation Delay for Enable to Output and
Enable Pulse Width
Dn
V
V
t
M
M
t
PHL
PLH
Qn
V
V
M
M
SF00260
Waveform 3. Propagation Delay for Data to Output
Dn
E
Dn
CP
V
V
V
V
V
V
V
V
M
M
M
M
M
M
M
M
t
(L)
t
(L)
t
(L)
t (L)
h
t
(H)
t
(H)
t
(H)
t (H)
h
su
h
su
su
h
su
V
M
V
V
M
V
M
M
SF00261
SF00262
Waveform 4. Data Setup Time and Hold Times
Waveform 5. Data Setup Time and Hold Times
OE
Qn
OE
Qn
V
V
V
V
M
M
t
M
t
M
t
V
-0.3V
OH
t
PZH
PHZ
PZL
PLZ
3.5V
V
V
M
M
0V
V
+0.3V
OL
SC00099
SC00100
Waveform 6. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 7. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
8
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS373/74ALS374
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
0.3V
V
CC
90%
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
R
R
IN
L
L
PULSE
GENERATOR
D.U.T.
t
t )
f
t
t )
THL ( f
TLH ( r
R
C
L
T
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0.3V
90%
90%
POSITIVE
PULSE
V
V
M
M
Test Circuit for 3-State Outputs
SWITCH POSITION
10%
10%
t
w
TEST
, t
SWITCH
closed
Input Pulse Definition
INPUT PULSE REQUIREMENTS
t
PLZ PZL
All other
open
Family
V
M
Rep.Rate
t
w
t
t
THL
Amplitude
DEFINITIONS:
TLH
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
2.0ns
2.0ns
74ALS
3.5V
1.3V
1MHz
500ns
of
OUT
SC00072
9
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip–flop
74ALS373/74ALS374
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
10
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip–flop
74ALS373/74ALS374
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
11
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip–flop
74ALS373/74ALS374
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
12
1991 Feb 08
Philips Semiconductors
Product specification
Latch/flip–flop
74ALS373/74ALS374
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips
Semiconductors
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