P87C550EBL_技术文档

INTEGRATED CIRCUITS

80C550/83C550/87C550

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

Product specification

IC20 Data Handbook

1994 Feb 11

Philips

Semiconductors

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

DESCRIPTION

PIN CONFIGURATIONS

The Philips 8XC550 is a high-performance microcontroller fabricated

with Philips high-density CMOS technology. This Philips CMOS

technology combines the high speed and density characteristics of

HMOS with the low power attributes of CMOS. Philips epitaxial

substrate minimizes latch-up sensitivity. The CMOS 8XC550 has the

same instruction set as the 80C51.

40

39

38

37

36

35

34

33

32

31

V

1

2

3

AV /Vref+

CC

AV /Vref–

SS

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

P1.0/ADC0

4

5

P1.1/ADC1

P1.2/ADC2

The 8XC550 contains a 4k × 8 EPROM (87C550)/ROM

(83C550)/ROMless (80C550 has no program memory on-chip), a

128 × 8 RAM, 8 channels of 8-bit A/D, four 8-bit ports (port 1 is input

only), a watchdog timer, two 16-bit counter/timers, a seven-source,

two-priority level nested interrupt structure, a serial I/O port for either

multi-processor communications, I/O expansion or full duplex UART,

and an on-chip oscillator and clock circuits.

6

7

P1.3/ADC3

P1.4/ADC4

P1.5/ADC5

8

9

RST

CERAMIC

AND

PLASTIC

DUAL

IN-LINE

PACKAGE

RxD/P3.0

EA/V

PP

10

11

12

13

In addition, the 8XC550 has two software selectable modes of

power reduction—idle mode and power-down mode. The idle mode

freezes the CPU while allowing the RAM, timers, serial port, and

interrupt system to continue functioning. The power-down mode

saves the RAM contents but freezes the oscillator, causing all other

chip functions to be inoperative.

TxD/P3.1

INT0/P3.2

30

29

28

27

26

25

24

23

22

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

INT1/P3.3

T0/P3.4

T1/P3.5

WR/P3.6

RD/P3.7

XTAL2

14

15

16

17

18

19

20

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

FEATURES

• 80C51 based architecture

– 4k × 8 EPROM (87C550)/ROM (83C550)

– 128 × 8 RAM

XTAL1

21

V

SS

– Eight channels of 8-bit A/D

– Two 16-bit counter/timers

– Watchdog timer

6

1

40

– Full duplex serial channel

– Boolean processor

7

39

29

CERAMIC

AND

PLASTIC

LEADED

CHIP CARRIER

• Memory addressing capability

– 64k ROM and 64k RAM

17

• Power control modes:

– Idle mode

18

28

– Power-down mode

• CMOS and TTL compatible

Pin Function

1

2

3

AV

Vref+

Vref–

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P3.2/INT0

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

EA/V

PP

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

CC

• One speed range at V = 5V ±10%

CC

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

V

SS

P2.0/A8

P2.1/A9

– 3.5 to 16MHz

4

AV

SS

• Four package styles

• Extended temperature ranges

• OTP package available

5

6

7

8

P1.0/ADC0

P1.1/ADC1

P1.2/ADC2

P1.3/ADC3

P1.4/ADC4

P1.5/ADC5

P1.6/ADC6

P1.7/ADC7

RST

9

10

11

12

13

14

15

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

V

CC

P3.0/RxD

P3.1/TxD

SU00196

2

1994 Feb 11

853–1568 12184

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

ORDERING INFORMATION

TEMPERATURE RANGE °C

FREQ

MHz

DRAWING

NUMBER

1

ROMless

ROM

EPROM

P87C550EBF FA

P87C550EBL KA

P87C550EBP N

P87C550EBA A

P87C550EFP N

P87C550EFA A

P87C550EFL KA

P87C550EFF FA

AND PACKAGE

UV

0 to +70, Ceramic Dual In-Line Package

0 to +70, Ceramic Leaded Chip Carrier

0 to +70, Plastic Dual In-Line Package

0 to +70, Plastic Leaded Chip Carrier

–40 to +85, Plastic Dual In-Line Package

–40 to +85, Plastic Leaded Chip Carrier

–40 to +85, Ceramic Leaded Chip Carrier

–40 to +85, Ceramic Dual In-Line Package

3.5 to 16

0590B

1472A

P80C550EBP N

P80C550EBA A

P80C550EFP N

P80C550EFA A

P83C550EBP N

P83C550EBA A

P83C550EFP N

P83C550EFA A

OTP

UV

SOT129-1

SOT187-2

SOT129-1

SOT187-2

1472A

UV

0590B

NOTES:

1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM.

3

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

BLOCK DIAGRAM

P0.0–P0.7

P2.0–P2.7

PORT 0

DRIVERS

PORT 2

DRIVERS

V

CC

V

SS

RAM ADDR

REGISTER

PORT 0

LATCH

PORT 2

LATCH

ROM/EPROM

RAM

B

STACK

POINTER

ACC

REGISTER

PROGRAM

ADDRESS

REGISTER

TMP1

TMP2

BUFFER

PCON SCON TMOD TCON

ALU

TH0

TL0

TH1

TL1

PC

INCRE-

MENTER

SBUF

IE

IP

PSW

INTERRUPT, SERIAL

PORT AND TIMER BLOCKS

PROGRAM

COUNTER

PSEN

ALE/PROG

TIMING

AND

CONTROL

DPTR

EA/V

PP

RST

PORT 1

LATCH

PORT 3

LATCH

PD

OSCILLATOR

PORT 1

DRIVERS

PORT 3

DRIVERS

XTAL1

XTAL2

P1.0–P1.7

P3.0–P3.7

SU00005

4

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

PIN DESCRIPTION

PIN NO.

MNEMONIC

DIP

20

40

1

LCC TYPE

NAME AND FUNCTION

V

24

44

1

I

Ground: 0V reference.

SS

CC

V

Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

Analog Power Supply: Analog supply voltage.

AV

CC

SS

2

4

Analog Ground: Analog 0V reference.

Vref+

Vref–

2

3

I

Vref: A/D converter reference level inputs. Note that these references are combined with AV and

CC

AV in the 40-pin DIP package.

SS

P0.0–0.7

39–32 43–36

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float

and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and

data bus during accesses to external program and data memory. In this application, it uses strong

internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in

the S87C550. External pull-ups are required during program verification.

P1.0–P1.7

ADC0–ADC7

P2.0–P2.7

3–8

5–12

I

Port 1: Port 1 is an 8-bit input only port (6-bit in the DIP package; bits P1.6 and P1.7 are not

implemented). Port 1 digital input can be read out any time.

ADCx: Inputs to the analog multiplexer input of the 8-bit A/D. There are only six A/D inputs in the

DIP package.

21–28 25–32

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written

to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that

are externally being pulled low will source current because of the internal pull-ups. (See DC

Electrical Characteristics: I ). Port 2 emits the high-order address byte during fetches from external

IL

program memory and during accesses to external data memory that use 16-bit addresses (MOVX

@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to

external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2

special function register.

P3.0–P3.7

10–17 14–21

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written

to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that

are externally being pulled low will source current because of the pull-ups. (See DC Electrical

Characteristics: I ). Port 3 also serves the special features of the SC80C51 family, as listed below:

IL

10

11

12

13

14

15

16

17

14

15

16

17

18

19

20

21

I

O

I

O

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

RST

9

13

I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.

An internal diffused resistor to V permits a power-on reset using only an external capacitor to

SS

V

CC

.

ALE/PROG

30

34

I/O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address

during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6

the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is

skipped during each access to external data memory. This pin is also the program pulse input

(PROG) during EPROM programming.

PSEN

29

31

33

35

O

I

Program Store Enable: The read strobe to external program memory. When the device is

executing code from the external program memory, PSEN is activated twice each machine cycle,

except that two PSEN activations are skipped during each access to external data memory. PSEN

is not activated during fetches from internal program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be externally held low to enable

the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held

high, the device executes from internal program memory unless the program counter contains an

address greater than 0FFFH. For the 80C550 ROMless part, EA must be held low for the part to

PP

operate properly. This pin also receives the 12.75V programming supply voltage (V ) during

PP

EPROM programming.

XTAL1

XTAL2

19

18

23

22

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

Crystal 2: Output from the inverting oscillator amplifier.

O

5

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

Table 1.

8XC550 Special Function Registers

DIRECT

DESCRIPTION

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

VALUE

SYMBOL

ADDRESS MSB

LSB

ACC*

Accumulator

A/D result

A/D control

B register

E0H

C6H

C5H

F0H

E7

E6

E5

E4

E3

E2

E1

E0

00H

xxH

ADCS AADR2 AADR1 AADR0 xxx00000B

ADAT#

ADCON#

B*

–

ADCI

F4

F7

F6

F5

F3

F2

F1

F0

00H

DPTR:

Data pointer

(2 bytes):

High byte

Low byte

DPH

DPL

83H

82H

00H

BF

–

BE

BD

BC

PS

BB

BA

B9

B8

IP*#

Interrupt priority

B8H

PWD

PAD

PT1

PX1

PT0

PX0

x0000000B

AF

EA

87

97

A7

B7

AE

EWD

86

AD

EAD

85

AC

ES

84

94

A4

B4

–

AB

ET1

83

AA

EX1

82

A9

ET0

81

A8

EX0

80

IE*#

P0*

Interrupt enable

Port 0

A8H

80H

90H

A0H

B0H

87H

00H

FFH

P1*

Port 1

96

95

93

92

91

90

FFH

P2*

Port 2

A6

A5

B5

–

A3

A2

A1

A0

FFH

P3*

Port 3

B6

B3

B2

B1

B 0

IDL

FFH

PCON#

Power control

SMOD SIDL

GF1

GF0

PD

00xx0000B

D7

CY

D6

AC

D5

F0

D4

D3

D2

D1

–

D0

P

PSW*

SBUF

Program status word

Serial data buffer

D0H

99H

RS1

RS0

OV

00H

xxH

9F

9E

9D

9C

9B

9A

99

TI

98

RI

SCON*

SP

Serial port control

Stack pointer

98H

81H

SM0

SM1

SM2

REN

TB8

RB8

00H

07H

00H

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer counter/control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TMOD

TH0

TH1

TL0

Timer/counter mode

Timer 0 high byte

Timer 1 high byte

Timer 0 low byte

Timer 1 low byte

89H

8CH

8DH

8AH

8BH

GATE

C/T

M1

M0

GATE

C/T

M1

M0

00H

TL1

C7

C6

C5

C4

–

C3

–

C2

C1

C0

WDMOD

WDRUN WDTOF

WDCON*# Watchdog timer

control

C0H

C1H

C2H

C3H

PRE2 PRE1

PRE0

000xx000B**

FFH**

xxH

WDL#

Watchdog timer

reload

WFEED1# Watchdog timer

feed 1

WFEED2# Watchdog timer

feed 2

xxH

* SFRs are bit addressable.

# SFRs are modified from or added to the 80C51 SFRs.

**This value is not valid for a masked ROM part (83C550) when running from internal memory (EA = 1). See data sheet for details.

6

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

MSB

LSB

SMOD SIDL

X

GF1

GF0

PD

IDL

BIT

PCON.7

SYMBOL

SMOD

SIDL

X

FUNCTION

Double baud rate

Serial port idle

Reserved for future use

General purpose flag bit

Power down bit

PCON.6

PCON.5

PCON.4

PCON.3

PCON.2

PCON.1

PCON.0

X

GF1

GF0

PD

IDL

Idle mode bit

NOTE:

The PCON register is at SFR byte address 87H. Its contents following a reset are 00XX0000.

SU00197

Figure 1. Power Control Register (PCON)

MSB

X

LSB

X

ADCI ADCS AADR2 AADR1 AADR0

INPUT CHANNEL SELECTION

ADDR2

ADDR1

ADDR0

INPUT PIN

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BIT

SYMBOL

FUNCTION

ADCON.7

ADCON.6

ADCON.5

—

Not used

ADCON.4 ADCI

ADC Interrupt flag.

This flag is set when an ADC conversion result is ready to be read.

An interrupt is invoked if the A/D interrupt is enabled. The flag must

be cleared by software. It cannot be set by software.

ADCON.3 ADCS

ADC Start and Status.

Setting this flag starts an A/D conversion. The ADC logic insures that

this signal is high while the ADC is busy. On completion of the

conversion, ADCS is reset at the same time the interrupt flag ADCI is

set. ADCS cannot be reset by software.

ADCON.2 ADDR2

ADCON.1 ADDR1

ADCON.0 ADDR0

Analog Input Select 2

Analog Input Select 1

Analog Input Select 0

SU00198

Figure 2. A/D Control Register (ADCON)

7

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

ADCON Register

MSB

A/D CONVERTER

LSB

The analog input circuitry consists of an 8-input analog multiplexer

and an analog-to-digital converter with 8-bit resolution. In the LCC

package, the analog reference voltage and analog power supplies

are connected via separate input pins; in the DIP package, Vref+ is

X

ADCI

SDCS

AADR2

AADR1

AADR0

ADCI

ADCS

Operation

combined with AV and Vref– is combined with AV . The analog

CC

SS

0

1

0

1

0

1

ADC not busy, a conversion can be started.

ADC busy, start of a new conversion is blocked.

Conversion completed, start of a new is blocked.

Not possible.

inputs are alternate functions to port 1, which is an input only port.

Digital input to port 1 can be read any time during an A/D

conversion. Care should be exercised in mixing analog and digital

signals on port 1, because cross talk from the digital input signals

can degrade the A/D conversion accuracy of the analog input. An

A/D conversion requires 40 machine cycles.

INPUT CHANNEL SELECTION

ADDR2

ADDR1

ADDR0

INPUT PIN

The A/D converter is controlled by the ADCON special function

register. The input channel to be converted is selected by the analog

multiplexer by setting ADCON register bits, ADDR2–ADDR0 (see

Figure 2). These bits can only be changed when ADCI and ADCS

are both low.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6*

P1.7*

The completion of the 8-bit ADC conversion is flagged by ADCI in

the ADCON register and the result is stored in the special function

register ADAT.

*Not present on 40-pin DIP versions.

An ADC conversion in progress is unaffected by a software ADC

start. The result of a completed conversion remains unaffected

provided ADCI remains at a logic 1. While ADCS is a logic 1 or

ADCI is a logic 1, a new ADC START will be blocked and

consequently lost. An A/D conversion in progress will be aborted

when the idle or power-down mode is entered. The result of a

completed conversion (ADCI = logic 1) remains unaffected when

entering the idle mode, but will be lost if power-down mode is

entered. See Figure 3 for the A/D input equivalent circuit.

Symbol Position Function

ADCI

ADCON.4 ADC interrupt flag. This flag is set when an

ADC conversion is complete. If IE.5 = 1, an

interrupt is requested when ADCI = 1. The

ADCI flag must be cleared by software after

A/D data is read, before the next conversion

can begin.

ADCS ADCON.3 ADC start and status. Setting this bit starts an

A/D conversion. Once set, ADCS remains high

throughout the conversion cycle. On

The analog input pins ADC0-ADC7 may still be used as digital

inputs. The analog input channel that is selected by the

ADDR2-ADDR0 bits in ADCON cannot be used as a digital input.

Reading the selected A/D channel as a digital input will always

return a 1. The unselected A/D inputs may always be used as digital

inputs.

completion of the conversion, it is reset at the

same time the ADCI interrupt flag is set. ADCS

cannot be reset by software.

AADR2 ADCON.2 Analog input selects.

AADR1 ADCON.1 Binary coded address

AADR0 ADCON.0 selects one of the five analog input port pins of

P1 to be input to the converter. It can only be

changed when ADCI and ADCS are both low.

AADR2 is the most significant bit.

On RESET the A/D port pins are set to the Digital mode and will

work as a normal port and need no further initialization. To use the

A/D converter a single byte should be written to ADCON which

selects the A/D mux and concurrently sets the ADCS bit to start the

A/D conversion. The 40 machine cycles of the A/D conversion

include time for signal settling after the mux is selected and before

the Sample and Hold procedure is completed.

The circuitry which disables the digital buffer from the port pin is

updated at the start of an A/D conversion by setting the ADCS bit in

ADCON. After powerup, problems will occur the first time that

ADCON is written to if ADCS is not set; in this case, the digital

signal disable registers contain random data and some o the 8 port

pins will have their digital buffers disabled. When read, these

disabled buffers will ignore their input and only return a 1. This

condition will be corrected by writing a 1 to ADCS in ADCON which

starts and A/D conversion.

Thus, there are two operating modes:

1. DIGITAL ONLY - No Analog inputs are used and ADCON is

never written to. In this case pins ADC0-ADC7 are configured as

digital inputs.

2. A/D CONVERTER USED - The input multiplexer select field

must be written to and ADCS must be set in ADCON. This allows

unselected A/D inputs to be used as digital inputs.

8

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

Sample A/D Routines

The routine StartAD will start a read of the A/D channel identified by

R7 and exit back to the calling program. When the conversion is

complete, the A/D interrupt occurs, calling the A/D interrupt service

routine. The result of the conversion is returned in register R6.

The following routines demonstrate two methods of operating the

A/D converter. The first method uses polling to determine when the

A/D conversion is complete. The second method uses the A/D

interrupt to flag the end of conversion.

StartAD: MOV A,#08h

;Basic A/D start command.

;Add channel # to be read.

;Start A/D.

The routine ReadAD will start a read of the A/D channel identified by

R7, and wait for the conversion to complete, polling the A/D interrupt

flag. The result is returned in the accumulator.

ORL A,R7

MOV ADCON,A

RET

.

ReadAD:MOV A,#08h

ORL A,R7

MOV ADCON,A;

ADLoop: MOV A,ADCON

;Basic A/D start command.

;Add channel # to be read.

;Start A/D.

ORG 2Bh

;A/D interrupt address.

;Get conversion result.

;Clear ADCI.

;Get A/D status.

ADInt: MOV R6,ADAT

MOV ADCON,#0

RETI

JNB ACC.4,ADLoop;Wait for ADCI (A/D ;finished).

MOV A,ADAT

MOV ADCON,#0

RET

;Get conversion result

;Clear ADCI.

Sm

Rm

N+1

I

N+1

N

To Comparator

I

N

+

Multiplexer

R

S

C

S

V

ANALOG

INPUT

Rm = 0.5 - 3 kΩ

CS + CC = 15pF maximum

RS = Recommended < 9.6 kΩ for 1 LSB @ 12MHz

NOTE:

Because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. When a conversion

is initiated, switch Sm closes for 8tcy (8µs @ 12MHz crystal frequency) during which time capacitance Cs + Cc is charged. It should

be noted that the sampling causes the analog input to present a varying load to an analog source.

SU00199

Figure 3. A/D Input: Equivalent Circuit

9

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

A/D CONVERTER PARAMETER DEFINITIONS

The following definitions are included to clarify some specifications

given and do not represent a complete set of A/D parameter

definitions.

WATCHDOG TIMER

The purpose of the watchdog timer is to reset the microcontroller

within a reasonable amount of time if it enters an erroneous state,

possibly due to a programming error, electrical noise, or RFI. When

enabled, the watchdog circuit will generate a system reset if the user

program fails to “feed” (or reload) the watchdog within a

predetermined amount of time.

Absolute Accuracy Error

Absolute accuracy error of a given output is the difference between

the theoretical analog input voltage to produce a given output and

the actual analog input voltage required to produce the same code.

Since the same output code is produced by a band of input voltages,

the “required input voltage” is defined as the midpoint of the band of

input voltage that will produce that code. Absolute accuracy error

not specified with a code is the maximum over all codes.

The watchdog timer implemented on the 8XC550 has a

programmable interval and can thus be fine tuned to a particular

application. If the watchdog function is not used, the timer may still

be used as a versatile general purpose timer.

The watchdog function consists of a programmable 13-bit prescaler,

and an 8-bit main timer. The main timer is clocked by a tap taken

from one of the top 8 bits of the prescaler. The prescaler is

incremented once every machine cycle, or 1/12 of the oscillator

frequency. Thus, the main counter can be clocked as often as once

every 64 machine cycles or as seldom as once every 8192 machine

cycles.

Nonlinearity

If a straight line is drawn between the end points of the actual

converter characteristics such that zero offset and full scale errors

are removed, then non-linearity is the maximum deviation of the

code transitions of the actual characteristics from that of the straight

line so constructed. This is also referred to as relative accuracy and

also integral non-linearity.

When clocked, the main counter decrements. If the main watchdog

counter reaches zero, a system reset will occur. To prevent the

watchdog timer from under-flowing, the watchdog must be fed

before it counts down to zero. When the watchdog is fed, the

contents of the WDL register are loaded into the main watchdog

counter and the prescaler is cleared.

Differential Non-Linearity

Differential non-linearity is the maximum difference between the

actual and ideal code widths fo the converter. The code widths are

the differences expressed in LSB between the code transition

points, as the input voltage is varied through the range for the

complete set of codes.

WDCON Register

MSB

LSB

PRE2

PRE1

PRE0

X

WDRUN

WDTOF

WDMOD

Gain Error

Gain error is the deviation between the ideal and actual analog input

voltage required to cause the final code transition to a full-scale

output code after the offset error has been removed. This may

sometimes be referred to as full scale error.

Symbol

WDCON.7 PRE2

Position

Function

Prescaler select (read/write).

WDCON.6 PRE1

WDCON.5 PRE0

These bits select theprescaler divide ratio

according to the following table:

Offset Error

PRE2

PRE1

PRE0

DIVISOR (FROM f

)

OSC

Offset error is the difference between the actual input voltage that

causes the first code transition and the ideal value to cause the first

0

1

0

1

0

1

0

1

0

1

0

1

0

1

12 × 64

code transition. This ideal value is 1/2 LSB above V

.

12 × 64 × 2

12 × 64 × 4

12 × 64 × 8

12 × 64 × 16

12 × 64 × 32

12 × 64 × 64

12 × 64 × 128

ref–

Channel to Channel Matching

Channel to channel matching is the maximum difference between

the corresponding code transitions of the actual characteristics

taken from different channels under the same temperature, voltage

and frequency conditions.

WDCON.4

WDCON.3

–

Not used

Crosstalk

WDCON.2 WDRUN Run control (read/write).

Crosstalk is the measured level of a signal at the output of the

converter resulting from a signal applied to one deselected channel.

This bit turns the timer on (WDRUN = 1) or off

(WDRUN = 0) if the timer mode has been

selected.

Total Error

WDCON.1 WDTOF Timeout flag (read/write).

Maximum deviation of any step point from a line connecting the ideal

first transition point to the ideal last transition point.

This bit is set when the watchdog timer

underflows. It is cleared by an external reset

and can be cleared by software.

Relative Accuracy

WDCON.0 WDMOD Mode selection (read/write).

Relative accuracy error is the deviation of the ADC’s actual code

transition points from the ideal code transition points on a straight

line which connects the ideal first code transition point and the final

code transition point, after nullifying offset error and gain error. It is

generally expressed in LSBs or in percent of FSR.

When WDMOD = 1, the watchdog is selected;

when WDMOD = 0, the timer is selected.

Selecting the watchdog mode automatically

disables power-down mode. WDMOD is

cleared by external reset. Once the watchdog

mode is selected, this bit can only be cleared

by writing a 0 to this bit and then performing a

feed operation.

10

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

A very specific sequence of events must take place to feed the

watchdog timer; it cannot be fed accidentally by a runaway program.

The following routines demonstrate setting up and feeding the

watchdog timer. These routines apply to all versions of the 8XC550

except the ROM part when running from internal program memory.

Watchdog Detailed Operation

EPROM Device (and ROMless Operation: EA = 0)

In the ROMless operation (ROM part, EA = 0) and in the EPROM

device, the watchdog operates in the following manner.

Whether the watchdog is in the watchdog or timer mode, when

external RESET is applied, the following takes place:

– Watchdog mode bit set to timer mode.

This routine sets up and starts the watchdog timer. This is not

necessary for internal ROM operation, because setup of the

watchdog timer on masked ROM parts is accomplished directly via

ROM mask options.

– Watchdog run control bit set to OFF.

– Autoload register set to FF (max count).

– Watchdog time-out flag cleared.

– Prescaler is cleared.

SetWD: MOV WDL,#0FFh ;Set watchdog reload value.

MOV WDCON,#0E5;Set up timer prescaler, mode, and

;run bits.

– Prescaler tap set to the highest divide.

– Autoload takes place.

ACALL FeedWD

;Start watchdog with a feed

;operation.

RET

The watchdog can be fed even though it is in the timer mode.

This routine executes a watchdog timer feed operation, causing the

timer to reload from WDL. Interrupts must be disabled during this

operation due to the fact that the two feed registers must be loaded

on consecutive instruction cycles, or a system reset will occur

immediately.

Note that the operational concept is for the watchdog mode of

operation, when coming out of a hardware reset, the software

should load the autoload registers, set the mode to watchdog, and

then feed the watchdog (cause an autoload). The watchdog will now

be starting at a known point.

FeedWD:CLR EA

;This sequence must not be

;interrupted.

If the watchdog is in the watchdog mode and running and happens

to underflow at the time the external RESET is applied, the

watchdog time-out flag will be cleared.

MOV WFEED1,#0A5h;First instruction of feed sequence.

MOV WFEED2,#05Ah;Second instruction of feed

;sequence.

SETB EA

RET

When the watchdog is in the watchdog mode and the watchdog

underflows, the following action takes place:

– Autoload takes place.

;Turn interrupts back on.

– Watchdog time-out flag is set

– Timer mode interrupt flag unchanged.

– Mode bit unchanged.

An interrupt is available to allow the watchdog timer to be used as a

general purpose timer in applications where the watchdog function is

not needed. The timer operates in the same manner when used as a

general purpose timer except that the timer interrupt is generated on

timer underflow instead of a chip reset. Refer to the 87C550 data

sheet for additional information on watchdog timer operation.

– Watchdog run bit unchanged.

– Autoload register unchanged.

– Prescaler tap unchanged.

Programming the Watchdog Timer

– All other device action same as external reset.

Both the EPROM and ROM devices have a set of SFRs for holding

the watchdog autoload values and the control bits. The watchdog

time-out flag is present in the watchdog control register and

operates the same in all versions. In the EPROM device, the

watchdog parameters (autoload value and control) are always taken

from the SFRs. In the ROM device, the watchdog parameters can

be mask programmed or taken from the SFRs. The selection to take

the watchdog parameters from the SFRs or from the mask

programmed values is controlled by EA (external access). When EA

is high (internal ROM access), the watchdog parameters are taken

from the mask programmed values. If the watchdog is masked

programmed to the timer mode, then the autoload values and the

pre-scaler taps are taken from the SFRs. When EA is low (external

access), the watchdog parameters are taken from the SFRs. The

user should be able to leave code in his program which initializes

the watchdog SFRs even though he has migrated to the mask ROM

part. This allows no code changes from EPROM prototyping to ROM

coded production parts.

Note that if the watchdog underflows, the program counter will start

from 00H as in the case of an external reset. The watchdog time-out

flag can be examined to determine if the watchdog has caused the

reset condition. The watchdog time-out flag bit can be cleared by

software.

When the watchdog is in the timer mode and the timer software

underflows, the following action takes place:

– Autoload takes place.

– Watchdog time-out flag is set

– Mode bit unchanged.

– Watchdog run bit unchanged.

– Autoload register unchanged.

– Prescaler tap unchanged.

The timer mode interrupt flag is cleared when the interrupt routine is

invoked. This bit can also be cleared directly by software without a

software feed operation.

Mask ROM Device (EA = 1)

In the mask ROM device, the watchdog mode bit (WDMOD) is mask

programmed and the bit in the watchdog command register is read

only and reflects the mask programmed selection. If the mask

programmed mode bit selects the timer mode, then the watchdog

run bit (WDRUN) operates as described under EPROM Device. If

the mask programmed bit selects the watchdog mode, then the

watchdog run bit has no effect on the timer operation.

11

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

Watchdog Function

Interrupt Enable Register

MSB

LSB

EX0

The watchdog consists of a programmable prescaler and the main

timer. The prescaler derives its clock from the on-chip oscillator. The

prescaler consists of a divide by 12 followed by a 13 stage counter

with taps from stage 6 through stage 13. The tap selection is

programmable. The watchdog main counter is a down counter

clocked (decremented) each time the programmable prescaler

underflows. The watchdog generates an underflow signal (and is

autoloaded) when the watchdog is at count 0 and the clock to

decrement the watchdog occurs. The watchdog is 8 bits long and

the autoload value can range from 0 to FFH. (The autoload value of

0 is permissible since the prescaler is cleared upon autoload).

EA

EWD

EAD

ES

ET1

EX1

ET0

Symbol Position

EA

Function

Global interrupt enable

Watchdog timer overflow

A/D conversion complete

Serial port transmit or receive

Timer 1 overflow

External interrupt 1

Timer 0 overflow

External interrupt 0

IE.7

IE.6

IE.5

IE.4

IE.3

IE.2

IE.1

IE.0

EWD

EAD

ES

ET1

EX1

ET0

EX0

This leads to the following user design equations. Definitions: t

OSC

is the oscillator period, N is the selected prescaler tap value, W is

Interrupt Priority Register

MSB

the main counter autoload value, t

is the minimum watchdog

MIN

LSB

PX0

time-out value (when the autoload value is 0), t

is the maximum

MAX

time-out value (when the autoload value is FFH), t is the design

–

PWD

PAD

PS

PT1

PX1

PT0

D

time-out value.

Symbol Position

Function

Watchdog timer

A/D conversion

Serial port interrupt

Timer 1 interrupt

External interrupt 1

Timer 0 interrupt

External interrupt 0

t

= t

× 12 × 64

OSC

MIN

PWD

PAD

PS

IP.6

IP.5

IP.4

IP.3

IP.2

IP.1

IP.0

= t

× 128 × 256

MIN

MAX

PRESCALER

= t

× 2

MIN

× W

D

(where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7)

PT1

PX1

PT0

PX0

Note that the design procedure is anticipated to be as follows. A

t

will be chosen either from equipment or operation

MAX

considerations and will most likely be the next convenient value

higher than t . (If the watchdog were inadvertently to start from FFH,

D

an overflow would be guaranteed, barring other anomalies, to occur

Power-Down and Idle Modes

within t

). Then the value for the prescaler would be chosen from:

The 8XC550 includes the standard 80C51 power-down and idle

modes of reduced power consumption. In addition, the 8XC550

includes an option to separately turn off the serial port for extra

power savings when it is not needed. Also, the individual functional

blocks such as the counter/timers are automatically disabled when

they are not running. This actually turns off the clocks to the block in

question, resulting in additional power savings. Note that when the

watchdog timer is operating, the processor is inhibited from entering

the power-down mode. This is due to the fact that the oscillator is

stopped in the power-down mode, which would effectively turn off

the watchdog timer. In keeping with the purpose of the watchdog

timer, the processor is prevented from accidentally entering

power-down due to some erroneous operation.

MAX

prescaler = log2 (t

/ (t

OSC

× 12 × 256)) – 6

MAX

This then also fixes t . An autoload value would then be chosen

from:

MIN

W = t / t

– 1

MIN

D

The software must be written so that a feed operation takes place

every t seconds from the last feed operation. Some tradeoffs may

D

need to be made. It is not advisable to include feed operations in

minor loops or in subroutines unless the feed operation is a specific

subroutine.

Interrupts

The 8XC550 interrupt structure is a seven-source, two-priority level

interrupt system similar to that of the standard 80C51

microcontroller. The interrupt sources are listed below in the order of

their internal polling sequence. This is the order in which

simultaneous interrupts of the same priority level would be serviced.

Power Control Register

MSB

LSB

IDL

SMOD

SIDL

–

GF1

GF0

PD

Symbol Position

Function

Interrupt Priorities

VECTOR

SMOD

PCON.7 Double baud rate bit. When set to a 1 and

Timer 1 is used to generate baud rate, and

the serial port is used in modes 1, 2, or 3.

PCON.6 Separately idles the serial port for additional

power savings.

PRIORITY SOURCE

FUNCTION

ADDRESS

SIDL

Highest

INT0

TF0

INT1

TF1

TI & RI

ADCI

0003H

000BH

0013H

001BH

0023H

002BH

External interrupt 0

Counter/timer 0 overflow

External interrupt 1

Counter/timer 1 overflow

Serial port transmit/receive

A/D converter conversion

complete

–

PCON.5 Reserved

–

PCON.4 Reserved

GF1

GF0

PD

PCON.3 General-purpose flag bit.

PCON.2 General-purpose flag bit.

PCON.1 Power-down bit. Starting this bit activates

power-down operation.

Lowest

WDTOF

0033H

Watchdog timer overflow

(only when not in

IDL

PCON.0 Idle mode bit. Setting this bit activates

idle mode operation.

watchdog mode)

If 1s are written to PD and IDL at the same time, PD takes

precedence.

Interrupt Control Registers

The standard 80C51 interrupt enable and priority registers have

been modified slightly to take into account the additional interrupt

sources of the 8XC550.

12

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

remain intact during this mode. The idle mode can be terminated

either by any enabled interrupt (at which time the process is picked

up at the interrupt service routine and continued), or by a hardware

reset which starts the processor in the same manner as a power-on

reset.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an on-chip

oscillator, as shown in the Block Diagram, page 4).

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. There are no requirements

on the duty cycle of the external clock signal, because the input to

the internal clock circuitry is through a divide-by-two flip-flop.

However, minimum and maximum high and low times specified in

the data sheet must be observed.

Programmable Idle Modes

The programmable idle modes have been dispersed throughout the

functional blocks. Each block has its own ability to be disabled. For

example, if timer 0 is not commanded to be running (TR = 0), then

the clock to the timer is disabled resulting in an idle mode power

saving. An additional idle control bit has been added to the serial

communications port.

IDLE MODE

A/D Operation in Idle Mode

In idle mode, the CPU puts itself to sleep while all of the on-chip

peripherals except the A/D stay active. the instruction to invoke the

idle mode is the last instruction executed in the normal operating

mode before the idle mode is activated. An A/D conversion in

progress will be aborted when idle mode is entered. The CPU

contents, the on-chip RAM, and all of the special function registers

When in the idle mode, the A/D converter will be disabled. However,

the current through the V

pins will be present and will not be

REF

reduced internally in either the idle or the power-down modes. It is

the responsibility of the user to disconnect V

supply current.

to reduce power

REF

MSB

LSB

PRE2 PRE1 PRE0

X

WDRUN WDTOF WDMOD

BIT

SYMBOL FUNCTION

WDCON.7 PRE2

WDCON.6 PRE1

WDCON.5 PRE0

Prescaler Select (Read/Write).

Thses bits select the prescaler divide ratio according to the following

table:

DIVISOR

PRE2

PRE1

PRE0

(from f

)

OSC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

12 X 64

12 X 64 X 2

12 X 64 X 4

12 X 64 X 8

12 X 64 X 16

12 X 64 X 32

12 X 64 X 64

12 X 64 X 128

WDCON.4

WDCON.3

—

Not used.

WDCON.2 WDRUN

WDCON.1 WDTOF

WDCON.0 WDMOD

Run Control (Read/Write).

This bit turns the timer on (WDRUN = 1) or off (WDRUN = 0) if the

timer mode has been selected.

Timeout Flag (Read/Write).

This bit is set when the watchdog timer underflows. It is cleared by an

external reset and can be cleared by software.

Mode Selection (Read/Write).

When WDMOD = 1, the watchdog mode is selected; when WDMOD

= 0, the timer mode is selected. Selecting the watchdog mode

automatically disables power-down mode. WDMOD is cleared by

external reset. Once the watchdog mode is selected, this bit can only

be cleared by writing a 0 to this bit and then performing a feed

operation.

SU00200

Figure 4. Watchdog Control Register (WDCON)

13

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

DESIGN CONSIDERATIONS

Security Bits

At power-on, the voltage on V and RST must come up at the

There are two security bits on the 83C550 and 87C550 that, when

set, prevent the program data memory from being read out or

programmed further.

CC

same time for a proper start-up.

When the idle mode is terminated by a hardware reset, the device

normally resumes program execution, from where it left off, up to

two machine cycles before the internal reset algorithm takes control.

On-chip hardware inhibits access to internal RAM in this event, but

access to the port pins is not inhibited. To eliminate the possibility of

an unexpected write when idle is terminated by reset, the instruction

following the one that invokes idle should not be one that writes to a

port pin or to external memory. Table 2 shows the state of I/O ports

during low current operating modes.

After the first security bit is programmed, the external MOVC

instruction is disabled, and for the 87C550, further programming of

the code memory or the encryption table is disabled. The other

security bit can of course still be programmed. With only security bit

one programmed, the memory can still be read out for program

verification. After the second security bit is programmed, it is no

longer possible to read out (verify) the program memory.

To program the security bits for the 87C550, repeat the

programming sequence using the “Pgm Security Bit” levels specified

in Table 4. For the masked ROM 83C550 the security bit information

is submitted with the ROM code as shown in Table 3.

Encryption Table

The encryption table is a feature of the 83C550 and 87C550 that

protects the code from being easily read by anyone other than the

programmer. The encryption table is 32 bytes of code that are

exclusive NORed with the program code data as it is read out. The

first byte is XNORed with the first location read, the second with the

second read, etc.

ROM Code Submission

When submitting a ROM code for the 83C550, the following must be

specified:

1. The 4k byte user ROM program.

After the encryption table has been programmed, the user has to

know its contents in order to correctly decode the program code

data. The encryption table itself cannot be read out.

2. The 32 byte ROM encryption key.

3. The ROM security bits.

For the EPROM (87C550) part, the encryption table is programmed

in the same manner as the program memory, but using the “Pgm

Encryption Table” levels specified in Table 4. After the encryption

table is programmed, verification cycles will produce only encrypted

information.

4. The watchdog timer parameters.

This information can be submitted in an EPROM (2764) or hex file

with the format specified in Table 3.

For the ROM part (83C550) the encryption table information is

submitted with the ROM code as shown in Table 3.

Table 2. External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM MEMORY

Internal

ALE

PSEN

PORT 0

Data

PORT 1

Data

PORT 2

Data

PORT 3

Data

Idle

1

0

1

0

External

Float

Data

Address

Data

Power-down

Internal

Data

External

Float

Data

Table 3. ROM Code Submittal Requirements

ADDRESS

0000H to 0FFFH

1000H to 101FH

1020H

CONTENT

BIT(s)

7:0

0

COMMENT

Data

Key

User ROM data

ROM encryption key; FFH = no encryption

ROM security bit 1

Security bit

1020H

1

ROM security bit 2

0 = enable security feature

1 = disable security feature

1

1030H

WDCON

7:5

4

3

2

1

PRE2:0

Not used

WDRUN = 0, not ROM coded

WDTOF = 0, not ROM coded

WDMOD

1

0

1031H

1032H

Not used

WD

7:0

Watchdog autoload value

(see specification)

NOTE:

1. See Watchdog Timer Specification for definition of WDL and WDCON bits.

14

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

Electrical Deviations from Commercial Specifications for Extended Temperature Range

DC and AC parameters not included here are the same as in the commercial temperature range table.

DC ELECTRICAL CHARACTERISTICS

T

amb

= –40°C to +85°C, V = 5V ±10% (87C550), V = 5V ±20% (80/83C550), V = 0V

CC CC SS

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

–0.5

0

MAX

0.2V –0.15

UNIT

V

Input low voltage, except EA

Input low voltage to EA

IL

CC

0.2V –0.35

V

IL1

IH

CC

Input high voltage, except XTAL1, RST

Input high voltage to XTAL1, RST

Logical 0 input current, ports 2, 3

0.2V +1

V

CC

V

CC

+0.5

V

CC

0.7V +0.1

V

IH1

CC

I

V

= 0.45V

= 2.0V

IN

–75

µA

IL

IN

Logical 1-to-0 transition current, ports 2, 3

V

–750

TL

Power supply current:

Active mode

Idle mode

CC

V

CC

= 4.5–5.5V,

35

6

50

mA

µA

Frequency range =

3.5 to 16MHz

Power down mode

ADC DC ELECTRICAL CHARACTERISTICS

AV = 5V ±10%, AV = 0V, T = –40°C to 85°C, unless otherwise specified

CC

SS

amb

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

AV

Analog supply

AV = V ± 0.2

4.5

5.5

V

CC

V

REF

Analog reference; AV

+ AV

AV – 0.2

AV + 0.2

REF

REF–

SS

CC

AI

Analog operating supply current

Analog input voltage

Analog input capacitance

Sampling time

See note 1

3.0

mA

V

CC

AV

AV – 0.2

AV + 0.2

IN

SS

CC

A

IC

, C

15

pF

IA

t

8t

CY

ADS

ADC

Conversion time

40t

CY

Ae

Absolute voltage error

Relative accuracy

Offset error

±1.5

±1

LSB

%

E

RA

OSe

Ge

See note 1

±1

Gain error

0.4

±1

M

CTC

Channel-to-channel matching

Crosstalk

LSB

dB

Ct

0 – 100kHz

–60

10.0

50

Rref

Resistance between AV

and AV

1.0

KΩ

µA

REF+

REF–

AI

ID

Idle mode supply current

See note 4

AI

PD

Power down supply current

50

µA

NOTES:

1. Conditions: V

= 4.99712V, V

= 0V. AI value does not include the resistor ladder current. For the 40-pin package, where the

CC

REF+

REF–

V

REF–

inputs are connected to AV and AV , the current AI will be increased by the register ladder current and may exceed the

CC SS CC

maximum shown here.

2. The resistor ladder network is not disconnected in the power-down or idle modes. Thus to conserve power, the user must remove AV and

CC

V

REF+

.

3. If the A/D function is not required, or if the A/D function is only needed periodically, AV can be removed without affecting the operation of

CC

the digital circuitry. Contents of ADCON and ADAT are not guaranteed to be valid. Digital inputs P1.0 to P1.7 will not function normally. No

digital outputs are present on these pins.

4. For this test, the Analog inputs must be at the supplies (either V or V ).

DD

SS

15

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

ABSOLUTE MAXIMUM RATINGS^{1, 2, 3}

PARAMETER

RATING

–40 to +85

–65 to +150

0 to +13.0

–0.5 to +6.5

±10

UNIT

°C

V

Operating temperature under bias

Storage temperature range

Voltage on EA/V pin to V (87C550 only)

PP

SS

Voltage on any other pin to V

V

SS

Input, output current on any two I/O pins

mA

W

Power dissipation (based on package heat transfer limitations, not device power consumption)

1.5

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

DC ELECTRICAL CHARACTERISTICS

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10% (87C550), V = 5V ±20% (80/83C550), V = 0V

CC CC SS

TEST

LIMITS

1

SYMBOL

PARAMETER

CONDITIONS

MIN

TYPICAL

MAX

0.2V –0.1

UNIT

V

7

V

Input low voltage, except EA

–0.5

0

IL

CC

7

Input low voltage to EA

0.2V –0.3

V

IL1

IH

CC

7

Input high voltage, except XTAL1, RST

0.2V +0.9

V

CC

V

CC

+0.5

V

CC

7

Input high voltage, XTAL1, RST

0.7V

V

IH1

OL

OL1

OH

CC

2

Output low voltage, ports 2, 3

I

= 1.6mA

= 3.2mA

0.45

V

OL

2

Output low voltage, port 0, ALE, PSEN

V

OL

3

Output high voltage, ports 2, 3, ALE, PSEN

I

= –60µA,

= –25µA

= –10µA

2.4

V

OH

0.75V

CC

0.9V

V

OH1

Output high voltage (port 0 in external bus mode)

I

= –800µA,

= –300µA

2.4

V

OH

I

0.75V

CC

= –80µA

0.9V

OH

7

I

Logical 0 input current, ports 1, 2, 3

V

= 0.45V

–50

–650

+10

µA

IL

IN

7

Logical 1-to-0 transition current, ports 1, 2, 3

See note 4

V = V or V

IN

TL

LI

Input leakage current, port 0

IL

IH

7

Power supply current (does not include AI ):

See note 6

CC

5

Active mode @ 16MHz

11.5

1.3

3

25

5

50

mA

µA

Idle mode @ 16MHz

Power down mode

R

C

Internal reset pull-down resistor

Pin capacitance (I/O pins only)

50

300

10

kΩ

RST

IO

pF

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the

OH

CC

address bits are stabilizing.

4. Pins of ports 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V is approximately 2V.

IN

5. I MAX at other frequencies is given by: Active mode; I MAX = 1.43 × FREQ + 1.90: Idle mode; I MAX = 0.14 × FREQ +2.31,

CC

where FREQ is the external oscillator frequency in MHz. I MAX is given in mA. See Figure 12.

6. See Figures 13 through 16 for I test conditions.

7. These values apply only to T

CC

= 0°C to +70°C. For T

= –40°C to +85°C. See table on previous page.

amb

16

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

AC ELECTRICAL CHARACTERISTICS

1, 2

T

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10% (87C550), V = 5V ±20% (80/83C550), V = 0V

amb

CC CC SS

16MHz CLOCK

MIN MAX

VARIABLE CLOCK

SYMBOL

1/t

FIGURE

PARAMETER

MIN

MAX

UNIT

5

Oscillator frequency: Speed Versions

CLCL

S8XC550 Exx

3.5

16

MHz

ns

t

5

ALE pulse width

85

7

2t

–40

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–55

AVLL

LLAX

LLIV

CLCL

27

t

–35

150

82

4t

3t

–100

CLCL

22

t

–40

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

PSEN pulse width

142

3t

–45

CLCL

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

–105

CLCL

0

37

207

10

t

–25

CLCL

5t

–105

CLCL

10

Data Memory

t

6, 7

RD pulse width

275

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

212

5t

–165

CLCL

0

Data float after RD

55

2t

–70

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

350

397

247

8t

CLCL

9t

CLCL

–150

–165

AVDV

LLWL

AVWL

QVWX

WHQX

RLAZ

WHLH

137

120

12

3t

–50

3t

+50

CLCL

4t

t

–130

–50

CLCL

12

t

–50

RD low to address float

RD or WR high to ALE high

0

22

102

t

–40

t

+40

CLCL

External Clock

t

9

High time

Low time

Rise time

Fall time

20

ns

CHCX

CLCX

CLCH

CHCL

20

Shift Register

t

8

Serial port clock cycle time

750

492

8

12t

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t

–133

QVXH

XHQX

XHDX

XHDV

CLCL

2t

CLCL

–117

0

492

10t

–133

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

17

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always

P – PSEN

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal. The

Q – Output data

R – RD signal

designations are:

A – Address

t – Time

V – Valid

C – Clock

W – WR signal

D – Input data

H – Logic level high

X – No longer a valid logic level

Z – Float

I

– Instruction (program memory contents)

Examples: t

= Time for address valid to ALE low.

= Time for ALE low to PSEN low.

AVLL

LLPL

L – Logic level low, or ALE

t

LHLL

ALE

t

LLPL

AVLL

t

PLPH

t

LLIV

t

PLIV

PSEN

t

LLAX

t

PXIZ

t

PLAZ

t

PXIX

A0–A7

INSTR IN

A0–A7

PORT 0

PORT 2

t

AVIV

A0–A15

A8–A15

SU00006

Figure 5. External Program Memory Read Cycle

ALE

PSEN

RD

t

WHLH

t

LLDV

t

LLWL

RLRH

t

RHDZ

t

LLAX

t

RLDV

AVLL

t

RLAZ

t

RHDX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA IN

A0–A7 FROM PCL

INSTR IN

t

AVWL

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00025

Figure 6. External Data Memory Read Cycle

18

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

ALE

t

WHLH

PSEN

t

WLWH

LLWL

WR

t

LLAX

t

WHQX

t

AVLL

QVWX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA OUT

A0–A7 FROM PCL

INSTR IN

t

AVWL

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00069

Figure 7. External Data Memory Write Cycle

INSTRUCTION

ALE

0

1

2

3

4

5

6

7

8

t

XLXL

CLOCK

t

XHQX

t

QVXH

OUTPUT DATA

0

1

2

3

4

5

6

7

WRITE TO SBUF

t

XHDX

t

SET TI

VALID

XHDV

INPUT DATA

CLEAR RI

VALID

SET RI

SU00027

Figure 8. Shift Register Mode Timing

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

t

CHCX

t

CHCL

CLCX

CLCH

t

CLCL

SU00009

Figure 9. External Clock Drive

19

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

V

–0.5

CC

V

+0.1V

LOAD

V

–0.1V

OH

TIMING

REFERENCE

POINTS

0.2V

+0.9

–0.1

CC

V

LOAD

V

–0.1V

+0.1V

OL

LOAD

CC

0.45V

NOTE:

For timing purposes, a port is no longer floating when a 100mV change from load

voltage occurs, and begins to float when a 100mV change from the loaded V /V

NOTE:

AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.

CC

OH OL

Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.

IH

IL

level occurs. I /I ≥ ±20mA.

OH OL

SU00717

SU00011

Figure 10. AC Testing Input/Output

Figure 11. Float Waveform

30

25

MAX ACTIVE MODE

I

mA

CC

20

15

10

5

TYP ACTIVE MODE

MAX IDLE MODE

TYP IDLE MODE

4MHz

8MHz

12MHz

16MHz

FREQ at XTAL1

SU00201

Figure 12. I vs. FREQ (Commercial Temp. Range)

CC

Valid only within frequency specifications of the device under test

20

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

V

CC

I

CC

V

CC

V

CC

V

CC

RST

V

CC

P0

EA

P1

RST

P0

EA

(NC)

XTAL2

XTAL1

(NC)

XTAL2

XTAL1

P1

CLOCK SIGNAL

V

SS

V

SS

SU00202

SU00203

Figure 13. I Test Condition, Active Mode

Figure 14. I Test Condition, Idle Mode

CC

All other pins are disconnected

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

t

CHCX

t

CLCH

CHCL

CLCX

t

CLCL

SU00009

Figure 15. Clock Signal Waveform for I Tests in Active and Idle Modes

CC

t

= t

= 5ns

CHCL

CLCH

V

CC

I

CC

V

CC

RST

V

P1

P0

EA

(NC)

XTAL2

XTAL1

V

SS

SU00204

Figure 16. I Test Condition, Power Down Mode

CC

All other pins are disconnected.

V

CC

= 2V to 5.5V.

21

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

Program Verification

EPROM CHARACTERISTICS

If security bit 2 has not been programmed, the on-chip program

memory can be read out for program verification. The address of the

program memory locations to be read is applied to ports 2 and 3 as

shown in Figure 19. The other pins are held at the ‘Verify Code Data’

levels indicated in Table 4. The contents of the address location will

be emitted on port 0. External pull-ups are required on port 0 for this

operation.

The 87C550 is programmed by using a modified Quick-Pulse

Programming algorithm. It differs from older methods in the value

used for V (programming supply voltage) and in the width and

PP

number of the ALE/PROG pulses.

The 87C550 contains two signature bytes that can be read and used

by an EPROM programming system to identify the device. The

signature bytes identify the device as an S87C550 manufactured by

Philips.

If the encryption table has been programmed, the data presented at

port 0 will be the exclusive NOR of the program byte with one of the

encryption bytes. The user will have to know the encryption table

contents in order to correctly decode the verification data. The

encryption table itself cannot be read out.

Table 4 shows the logic levels for reading the signature byte, and for

programming the program memory, the encryption table, and the

lock bits. The circuit configuration and waveforms for quick-pulse

programming are shown in Figures 17 and 18. Figure 19 shows the

circuit configuration for normal program memory verification.

Reading the Signature Bytes

The signature bytes are read by the same procedure as a normal

verification of locations 030H and 031H, except that P1.0 and P1.1

need to be pulled to a logic low. The values are:

(030H) = 15H indicates manufactured by Philips

(031H) = 96H indicates S87C550

Quick-Pulse Programming

The setup for microcontroller quick-pulse programming is shown in

Figure 17. Note that the 87C550 is running with a 4 to 6MHz

oscillator. The reason the oscillator needs to be running is that the

device is executing internal address and program data transfers.

Program/Verify Algorithms

Any algorithm in agreement with the conditions listed in Table 4, and

which satisfies the timing specifications, is suitable.

The address of the EPROM location to be programmed is applied to

ports 2 and 3, as shown in Figure 17. The code byte to be

programmed into that location is applied to port 0. RST, PSEN and

pins of ports 1 and 2 specified in Table 4 are held at the ‘Program

Code Data’ levels indicated in Table 4. The ALE/PROG is pulsed

low 25 times as shown in Figure 18.

Erasure Characteristics

Erasure of the EPROM begins to occur when the chip is exposed to

light with wavelengths shorter than approximately 4,000 angstroms.

Since sunlight and fluorescent lighting have wavelengths in this

range, exposure to these light sources over an extended time (about

1 week in sunlight, or 3 years in room level fluorescent lighting)

could cause inadvertent erasure. For this and secondary effects,

it is recommended that an opaque label be placed over the

window. For elevated temperature or environments where solvents

are being used, apply Kapton tape Fluorglas part number 2345–5, or

equivalent.

To program the encryption table, repeat the 25 pulse programming

sequence for addresses 0 through 1FH, using the ‘Pgm Encryption

Table’ levels. Do not forget that after the encryption table is

programmed, verification cycles will produce only encrypted data.

To program the security bits, repeat the 25 pulse programming

sequence using the ‘Pgm Security Bit’ levels. After one security bit is

programmed, further programming of the code memory and

encryption table is disabled. However, the other security bit can still

be programmed.

The recommended erasure procedure is exposure to ultraviolet light

(at 2537 angstroms) to an integrated dose of at least 15W-sec/cm .

Exposing the EPROM to an ultraviolet lamp of 12,000uW/cm rating

for 20 to 39 minutes, at a distance of about 1 inch, should be

sufficient.

2

Note that the EA/V pin must not be allowed to go above the

2

PP

maximum specified V level for any amount of time. Even a narrow

PP

glitch above that voltage can cause permanent damage to the

device. The V source should be well regulated and free of glitches

PP

Erasure leaves the array in an all 1s state.

and overshoot.

Table 4. EPROM Programming Modes

MODE

Read signature

RST

PSEN

ALE/PROG

EA/V

P2.7

P2.6

P1.1

P1.0

PP

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Program code data

Verify code data

Pgm encryption table

Pgm security bit 1

0*

1

V

PP

1

0*

V

PP

V

Pgm security bit 2

NOTES:

1. ’0’ = Valid low for that pin, ’1’ = valid high for that pin.

2. V = 12.75V ±0.25V.

PP

3. V = 5V±10% during programming and verification.

CC

*

ALE/PROG receives 25 programming pulses while V is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a

PP

minimum of 10µs.

Trademark phrase of Intel Corporation.

22

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

+5V

AV

V

CC

A0–A7

P3

P0

PGM DATA

+12.75V

1

RST

P1.0

EA/V

PP

25 100µs PULSES TO GROUND

ALE/PROG

PSEN

0

1

87C550

P1.1

XTAL2

P2.7

0

P2.6

4–6MHz

XTAL1

A8–A11

P2.0–P2.4

AV

SS

V

SS

SU00205

Figure 17. Programming Configuration

25 PULSES

1

0

ALE/PROG:

10µs MIN

100µs+10

1

0

SU00018

Figure 18. PROG Waveform

+5V

AV

V

CC

A0–A7

P3

P0

PGM Data

1

RST

P1.0

1

EA/V

PP

ALE/PROG

PSEN

0

87C550

P1.1

0 ENABLE

XTAL2

P2.7

0

P2.6

4–6MHz

XTAL1

A8–A11

P2.0–P2.4

AV

SS

V

SS

SU00206

Figure 19. Program Verification

23

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

T

amb

= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 20)

CC SS

SYMBOL

PARAMETER

MIN

MAX

13.0

50

UNIT

V

PP

Programming supply voltage

Programming supply current

Oscillator frequency

12.5

I

PP

mA

MHz

1/t

CLCL

4

6

t

Address setup to PROG low

Address hold after PROG

Data setup to PROG low

Data hold after PROG

48t

AVGL

CLCL

48t

GHAX

DVGL

GHDX

EHSH

SHGL

GHSL

GLGH

AVQV

ELQZ

EHQZ

GHGL

P2.7 (ENABLE) high to V

PP

V

PP

V

PP

setup to PROG low

hold after PROG

10

90

µs

PROG width

110

Address to data valid

48t

CLCL

ENABLE low to data valid

Data float after ENABLE

PROG high to PROG low

48t

0

10

µs

PROGRAMMING*

ADDRESS

VERIFICATION*

ADDRESS

P3.0–P3.7

P2.0–P2.4

t

AVQV

PORT 0

DATA IN

DATA OUT

t

GHDX

DVGL

t

GHAX

AVGL

ALE/PROG

t

GHGL

GLGH

t

GHSL

t

SHGL

LOGIC 1

EA/V

PP

LOGIC 0

t

EHSH

t

ELQV

EHQZ

P2.7

ENABLE

SU00207

NOTE:

*

FOR PROGRAMMING VERIFICATION, SEE FIGURE 17.

FOR VERIFICATION CONDITIONS, SEE FIGURE 19.

Figure 20. EPROM Programming and Verification

24

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

0590B

40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)

853–0590B 06688

25

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

1472A

44-PIN CERQUAD J-BEND (K) PACKAGE

853-1472A 05854

26

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

DIP40: plastic dual in-line package; 40 leads (600 mil)

SOT129-1

27

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

28

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

NOTES

29

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

NOTES

30

1994 Feb 11

Philips Semiconductors

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

NOTES

31

1994 Feb 11

Philips Semiconductors Microcontroller Products

Product specification

CMOS single-chip 8-bit microcontroller

with A/D and watchdog timer

80C550/83C550/87C550

DEFINITIONS

Data Sheet Identification

Product Status

Definition

This data sheet contains the design target or goal specifications for product development. Specifications

may change in any manner without notice.

Objective Specification

Formative or in Design

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips

Semiconductors reserves the right to make changes at any time without notice in order to improve design

and supply the best possible product.

Preliminary Specification

Product Specification

Preproduction Product

Full Production

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes

at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,

including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,

or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes

only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting

or modification.

LIFE SUPPORT APPLICATIONS

Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,

orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips

Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully

indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Sunnyvale, California 94088–3409

Philips Semiconductors and Philips Electronics North America Corporation

register eligible circuits under the Semiconductor Chip Protection Act.

Copyright Philips Electronics North America Corporation 1994

Telephone 800-234-7381


型号：	P87C550EBL
厂家：	PHILIPS SEMICONDUCTORS
描述：	Microcontroller, 8-Bit, UVPROM, 8051 CPU, 16MHz, CMOS, CQCC44 可编程只读存储器微控制器
文件：	总32页 (文件大小：310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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