PHP42N03LT [NXP]

TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管


型号：	PHP42N03LT
厂家：	NXP
描述：	TrenchMOS transistor Logic level FET 的TrenchMOS晶体管逻辑电平场效应管晶体晶体管
文件：	总8页 (文件大小：66K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP42N03LT, PHB42N03LT

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

• Fast switching

• Stable off-state characteristics

• High thermal cycling performance

• Low thermal resistance

V_DSS= 30 V

I_D= 42 A

_DS(ON)≤ 26 mΩ (V_GS= 5 V)

R_DS(ON)≤ 23 mΩ (V_GS= 10 V)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.

The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching

applications.

The PHP42N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB42N03LT is supplied in the SOT404 surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404

DESCRIPTION

tab

gate

drain ¹

source

drain

tab

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

I_D

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Continuous drain current

T_j= 25 ˚C to 175˚C

T_j= 25 ˚C to 175˚C; R_GS= 20 kΩ

± 15

168

˚C

T_mb= 25 ˚C; V_GS= 5 V

T_mb= 100 ˚C; V_GS= 5 V

T_mb= 25 ˚C

I_DM

P_D

T_j, T_stg

Pulsed drain current

Total power dissipation

Operating junction and

storage temperature

T_mb= 25 ˚C

- 55

175

November 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP42N03LT, PHB42N03LT

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

Thermal resistance junction

to mounting base

1.75 K/W

R_{th j-a}

Thermal resistance junction SOT78 package, in free air

to ambient SOT404 package, pcb mounted, minimum

footprint

K/W

ELECTRICAL CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

V_(BR)DSSDrain-source breakdown

CONDITIONS

MIN. TYP. MAX. UNIT

V_GS= 0 V; I_D= 0.25 mA;

V_DS= V_GS; I_D= 1 mA

0.5

mΩ

µA

voltage

Gate threshold voltage

T_j= -55˚C

V_GS(TO)

1.5

0.05

T_j= 175˚C

T_j= -55˚C

2.3

500

100

R_DS(ON)

Drain-source on-state

resistance

V_GS= 10 V; I_D= 25 A

V_GS= 5 V; I_D= 25 A

V_GS= 5 V; I_D= 25 A; T_j= 175˚C

g_fs

I_DSS

Forward transconductance

Zero gate voltage drain

current

V_DS= 25 V; I_D= 25 A

V_DS= 30 V; V_GS= 0 V;

T_j= 175˚C

I_GSS

Gate source leakage current V_GS= ±5 V; V_DS= 0 V

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 20 A; V_DD= 24 V; V_GS= 10 V

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 15 V; I_D= 25 A;

V_GS= 5 V; R_G= 5 Ω

Resistive load

130

L_d

Internal drain inductance

Measured tab to centre of die

Measured from drain lead to centre of die

(SOT78 package only)

3.5

4.5

L_s

Internal source inductance

Measured from source lead to source

bond pad

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

1050

270

140

November 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP42N03LT, PHB42N03LT

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

(body diode)

Pulsed source current (body

diode)

Diode forward voltage

I_SM

V_SD

180

I_F= 25 A; V_GS= 0 V

I_F= 40 A; V_GS= 0 V

0.95

1.0

1.2

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_F= 40 A; -dI_F/dt = 100 A/µs;

V_GS= -10 V; V_R= 25 V

0.08

µC

Normalised Power Derating

PD%

PHP42N03LT

ID, Drain current (Amps)

120

110

100

1000

100

tp = 10us

100 us

RDS(ON) = VDS/ID

1 ms

10 ms

100 ms

Tmb = 25 C

Tmb /

100 120 140 160 180

100

VDS, Drain-source voltage (Volts)

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.3. Safe operating area

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Normalised Current Derating

ID%

Zth j-mb / (K/W)

D =

7528-30

120

110

100

0.5

0.2

0.1

0.05

D =

0.02

0.01

100 120 140 160 180

1E-07

1E-05

1E-03

t / s

1E-01

1E+01

Tmb /

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); conditions: V_GS≥ 5 V

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

November 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP42N03LT, PHB42N03LT

ID, Drain current (Amps)

PHP45N03LT

4.5 V

Transconductance, gfs (S)

VDS = 25 V

15 V

Tj = 25 C

5 V

Tj = 25 C

10 V

4 V

175 C

3.5 V

3 V

VGS = 2.5 V

VDS, Drain-Source voltage (Volts)

Drain current, ID (A)

Fig.5. Typical output characteristics

I_D= f(V_DS); parameter V_GS

Fig.8. Typical transconductance

g_fs= f(I_D)

Drain-Source on resistance, RDS(on) (Ohms)

30V TrenchMOS

0.06

0.05

0.04

0.03

0.02

0.01

4.5 V

3.5 V

4 V

3 V

1.5

5 V

10 V

0.5

VGS = 15 V

Tj = 25 C

-100

100

200

-50

Tj / C

150

ID, Drain current (Amps)

PHP45N03LT

Fig.6. Typical on-state resistance

R_DS(ON)= f(I_D); parameter V_GS

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j)

BUK959-60

VGS(TO) / V

max.

PHP45N03LT

Drain current, ID (A)

VDS = 25 V

2.5

typ.

1.5

min.

0.5

Tj = 25 C

175 C

-100

-50

Tj / C

100

150

200

Gate-source voltage, VGS (V)

Fig.7. Typical transfer characteristics.

I_D= f(V_GS)

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= V_GS

November 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP42N03LT, PHB42N03LT

Sub-Threshold Conduction

PHP50N03LT

1E-01

1E-02

1E-03

1E-04

1E-05

VDD=24V

ID=20A

Tj = 25C

typ

98%

Qg, Gate charge (nC)

0.5

1.5

2.5

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); V_DS= V_GS

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G)

IF / A

C / pF

9528-30

10000

1000

100

Tj / C = 175

Ciss

Coss

Crss

0.1

100

0.5

1.5

VDS / V

VSDS / V

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); V_GS= 0 V; f = 1 MHz

Fig.14. Typical reverse diode current.

I_F= f(V_SDS

)

November 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP42N03LT, PHB42N03LT

MECHANICAL DATA

Dimensions in mm

Net Mass: 2 g

4,5

max

10,3

max

1,3

3,7

2,8

5,9

min

15,8

max

3,0 max

not tinned

3,0

13,5

min

1,3

1 2 3

max

(2x)

0,9 max (3x)

0,6

2,4

2,54 2,54

Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

November 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP42N03LT, PHB42N03LT

MECHANICAL DATA

Dimensions in mm

Net Mass: 1.4 g

4.5 max

1.4 max

10.3 max

11 max

15.4

2.5

0.85 max

(x2)

0.5

2.54 (x2)

Fig.16. SOT404 : centre pin connected to mounting base.

MOUNTING INSTRUCTIONS

Dimensions in mm

11.5

9.0

17.5

2.0

3.8

5.08

Fig.17. SOT404 : soldering pattern for surface mounting.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

November 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP42N03LT, PHB42N03LT

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

November 1998

Rev 1.400

PHP42N03LT [NXP]

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