PHX8ND50E [PHILIPS]

PowerMOS transistors FREDFET, Avalanche energy rated; 功率MOS晶体管FREDFET ,额定雪崩能量
PHX8ND50E
元器件型号: PHX8ND50E
生产厂家: NXP SEMICONDUCTORS    NXP SEMICONDUCTORS
描述和应用:

PowerMOS transistors FREDFET, Avalanche energy rated
功率MOS晶体管FREDFET ,额定雪崩能量

晶体晶体管
PDF文件: 总8页 (文件大小:63K)
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型号参数:PHX8ND50E参数
是否Rohs认证 不符合
生命周期Transferred
包装说明,
Reach Compliance Codeunknown
风险等级5.84
配置Single
最大漏极电流 (Abs) (ID)4.2 A
FET 技术METAL-OXIDE SEMICONDUCTOR
JESD-609代码e0
工作模式ENHANCEMENT MODE
最高工作温度150 °C
极性/信道类型N-CHANNEL
最大功率耗散 (Abs)37 W
子类别FET General Purpose Power
表面贴装NO
端子面层Tin/Lead (Sn/Pb)
Base Number Matches1
MAX34334CSE前5页PDF页面详情预览
Philips Semiconductors
Product specification
PowerMOS transistors
FREDFET, Avalanche energy rated
FEATURES
• Repetitive Avalanche Rated
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Isolated package
• Fast reverse recovery diode
PHX8ND50E
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 500 V
I
D
= 4.2 A
g
R
DS(ON)
0.85
s
t
rr
= 180 ns
SOT186A
GENERAL DESCRIPTION
N-channel, enhancement mode
field-effect
power
transistor,
incorporating a
Fast Recovery
Epitaxial Diode
(FRED). This gives
improved switching performance in
half bridge and full bridge
converters making this device
particularly suitable for inverters,
lighting ballasts and motor control
circuits.
The PHX8ND50E is supplied in the
SOT186A full pack, isolated
package.
PINNING
PIN
1
2
3
case
gate
drain
source
isolated
DESCRIPTION
case
1 2 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
1
Total dissipation
Operating junction and
storage temperature range
CONDITIONS
T
j
= 25 ˚C to 150˚C
T
j
= 25 ˚C to 150˚C; R
GS
= 20 kΩ
T
hs
= 25 ˚C; V
GS
= 10 V
T
hs
= 100 ˚C; V
GS
= 10 V
T
hs
= 25 ˚C
T
hs
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
500
500
±
30
4.2
2.7
34
37
150
UNIT
V
V
V
A
A
A
W
˚C
August 1998
1
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistors
FREDFET, Avalanche energy rated
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
CONDITIONS
MIN.
-
PHX8ND50E
MAX.
510
UNIT
mJ
E
AR
I
AS
, I
AR
Unclamped inductive load, I
AS
= 6.2 A;
t
p
= 0.18 ms; T
j
prior to avalanche = 25˚C;
V
DD
50 V; R
GS
= 50
Ω;
V
GS
= 10 V; refer
to fig:17
Repetitive avalanche energy
1
I
AR
= 8.5 A; t
p
= 1
µs;
T
j
prior to
avalanche = 25˚C; R
GS
= 50
Ω;
V
GS
= 10 V;
refer to fig:18
Repetitive and non-repetitive
avalanche current
-
-
19
8.5
mJ
A
ISOLATION LIMITING VALUE & CHARACTERISTIC
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
V
isol
PARAMETER
R.M.S. isolation voltage from all
three terminals to external
heatsink
CONDITIONS
f = 50-60 Hz; sinusoidal
waveform;
R.H.
65% ; clean and dustfree
MIN.
-
TYP.
MAX.
2500
UNIT
V
C
isol
Capacitance from T2 to external f = 1 MHz
heatsink
-
10
-
pF
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-hs
R
th j-a
Thermal resistance junction
to heatsink
Thermal resistance junction
to ambient
CONDITIONS
with heatsink compound
MIN.
-
-
TYP. MAX. UNIT
-
55
3.4
-
K/W
K/W
1
pulse width and repetition rate limited by T
j
max.
August 1998
2
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistors
FREDFET, Avalanche energy rated
ELECTRICAL CHARACTERISTICS
T
j
= 25 ˚C unless otherwise specified
SYMBOL PARAMETER
Drain-source breakdown
voltage
∆V
(BR)DSS
/ Drain-source breakdown
∆T
j
voltage temperature
coefficient
R
DS(ON)
Drain-source on resistance
V
GS(TO)
Gate threshold voltage
Forward transconductance
g
fs
I
DSS
Drain-source leakage current
I
GSS
Q
g(tot)
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
d
L
s
C
iss
C
oss
C
rss
V
(BR)DSS
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA
V
DS
= V
GS
; I
D
= 0.25 mA
MIN.
500
-
-
2.0
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PHX8ND50E
TYP. MAX. UNIT
-
0.1
0.7
3.0
6
1
40
10
88
6
47
18
50
104
60
4.5
7.5
1060
160
90
-
-
0.85
4.0
-
25
250
200
110
7
60
-
-
-
-
-
-
-
-
-
V
%/K
V
S
µA
µA
nA
nC
nC
nC
ns
ns
ns
ns
nH
nH
pF
pF
pF
V
GS
= 10 V; I
D
= 4.8 A
V
DS
= V
GS
; I
D
= 0.25 mA
V
DS
= 30 V; I
D
= 4.8 A
V
DS
= 500 V; V
GS
= 0 V
V
DS
= 400 V; V
GS
= 0 V; T
j
= 125 ˚C
Gate-source leakage current V
GS
=
±30
V; V
DS
= 0 V
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
I
D
= 8.5 A; V
DD
= 400 V; V
GS
= 10 V
V
DD
= 250 V; R
D
= 30
Ω;
R
G
= 9.1
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
T
j
= 25 ˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
I
rrm
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
Peak reverse recovery
current
CONDITIONS
T
hs
= 25˚C
T
hs
= 25˚C
I
S
= 8.5 A; V
GS
= 0 V
I
S
= 8.5 A; V
GS
= 0 V; dI/dt = 100 A/µs
I
S
= 8.5 A; V
GS
= 0 V; dI/dt = 100 A/µs;
125˚C
I
S
= 8.5 A; V
GS
= 0 V; dI/dt = 100 A/µs
I
S
= 8.5 A; V
GS
= 0 V; dI/dt = 100 A/µs;
125˚C
I
S
= 8.5 A; V
GS
= 0 V; dI/dt = 100 A/µs;
125˚C
MIN.
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
-
180
220
0.65
2.6
15
8.5
34
1.5
-
-
-
-
-
A
A
V
ns
ns
µC
µC
A
August 1998
3
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistors
FREDFET, Avalanche energy rated
PHX8ND50E
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
with heatsink compound
10
Zth j-hs, Transient thermal impedance (K/W)
D = 0.5
PHX4N60
1 0.2
0.1
0.05
0.1
0.02
0.01
single pulse
P
D
tp
t
D= p
T
t
100ms
1s
T
0
20
40
60
80
Ths / C
100
120
140
0.001
1us
10us
100us
1ms
10ms
tp, pulse width (s)
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 ˚C
= f(T
hs
)
ID%
Normalised Current Derating
30
with heatsink compound
Fig.4. Transient thermal impedance.
Z
th j-hs
= f(t); parameter D = t
p
/T
PHP8N50
10 V
7V
6.5 V
6V
5.5 V
10
5V
5
0
VGS = 4.5 V
120
110
100
90
80
70
60
50
40
30
20
10
0
ID, Drain current (Amps)
Tj = 25 C
25
20
15
0
20
40
60
80
Ths / C
100
120
140
0
5
10
15
20
25
VDS, Drain-Source voltage (Volts)
30
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 ˚C
= f(T
hs
); conditions: V
GS
10 V
ID, Drain current (Amps)
Fig.5. Typical output characteristics.
I
D
= f(V
DS
); parameter V
GS
PHP8N50
Tj = 25 C
100
PHX5N50
2
RDS(on), Drain-Source on resistance (Ohms)
4.5 V
5V
5.5 V
VGS = 6 V
10
R
1
(O
DS
=
N)
VD
ID
S/
tp = 10 us
1.5
100 us
1 ms
10 ms
DC
100 ms
0.5
1
6.5 V
7V
10 V
0.1
0.01
1
10
100
1000
VDS, Drain-source voltage (Volts)
10000
0
0
5
10
15
ID, Drain current (Amps)
20
25
Fig.3. Safe operating area. T
hs
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance.
R
DS(ON)
= f(I
D
); parameter V
GS
August 1998
4
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistors
FREDFET, Avalanche energy rated
PHX8ND50E
25
ID, Drain current (Amps)
VDS > ID x RDS(on)max
PHP8N50
4
VGS(TO) / V
max.
20
3
typ.
15
min.
2
10
1
5
Tj = 150 C
0
0
Tj = 25 C
0
2
4
6
VGS, Gate-Source voltage (Volts)
8
10
-60
-40
-20
0
20
40
60
Tj / C
80
100
120
140
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
gfs, Transconductance (S)
VDS > ID x RDS(on)max
Tj = 25 C
8
150 C
6
PHP8N50
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 0.25 mA; V
DS
= V
GS
ID / A
SUB-THRESHOLD CONDUCTION
10
1E-01
1E-02
1E-03
2%
typ
98 %
4
1E-04
2
1E-05
0
1E-06
0
5
10
15
ID, Drain current (A)
20
25
0
1
2
VGS / V
3
4
Fig.8. Typical transconductance.
g
fs
= f(I
D
); parameter T
j
a
Normalised RDS(ON) = f(Tj)
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
PHP8N50
10000
Junction capacitances (pF)
2
Ciss
1000
1
100
Coss
Crss
0
-60
-40
-20
0
20
40 60
Tj / C
80
100 120 140
10
1
10
100
VDS, Drain-Source voltage (Volts)
1000
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 4.25 A; V
GS
= 10 V
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
August 1998
5
Rev 1.100
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