PLUS153-10N [PHILIPS]
OT PLD, 10ns, PLA-Type, TTL, PDIP20,;
| 型号： | PLUS153-10N |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | OT PLD, 10ns, PLA-Type, TTL, PDIP20, 光电二极管 可编程逻辑 |
| 文件： | 总8页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(18 × 42 × 10)
PLUS153–10
DESCRIPTION
FEATURES
PIN CONFIGURATIONS
The PLUS153–10 PLD is a high speed,
combinatorial Programmable Logic Array.
The Philips Semiconductors state-of-the-art
Oxide Isolated Bipolar fabrication process is
employed to produce maximum propagation
delays of 10ns or less.
• I/O propagation delays (worst case)
– PLUS153–10 – 10ns max.
N Package
• Functional superset of 16L8 and most
I0
I1
1
2
3
4
5
6
7
8
9
20
V
CC
other 20-pin combinatorial PAL devices
19 B9
18 B8
17 B7
16 B6
15 B5
14 B4
13 B3
12 B2
11 B1
• Two programmable arrays
– Supports 32 input wide OR functions
I2
The 20-pin PLUS153 device has a
programmable AND array and a
I3
I4
• 8 inputs
programmable OR array. Unlike PAL
devices, 100% product term sharing is
supported. Any of the 32 logic product terms
can be connected to any or all of the 10
output OR gates. Most PAL ICs are limited to
7 AND terms per OR function; the
PLUS153–10 can support up to 32 input wide
OR functions.
I5
• 10 bi-directional I/O
I6
• 42 AND gates
– 32 logic product terms
I7
B0
– 10 direction control terms
GND 10
• Programmable output polarity
– Active-High or Active-Low
The polarity of each output is user-
programmable as either Active-High or
Active-Low, thus allowing AND-OR or
AND-NOR logic implementation. This feature
adds an element of design flexibility,
particularly when implementing complex
decoding functions.
N = Plastic DIP (300mil-wide)
• Security fuse
• 3-State outputs
A Package
• Power dissipation: 825mW (typ.)
• TTL Compatible
I2 I1 I0
B9
V
CC
20 19
3
2
1
18 B8
17 B7
16 B6
15 B5
14 B4
I3
I4
I5
I6
I7
4
5
6
7
8
The PLUS153–10 device is user-
programmable using one of several
commercially available, industry standard
PLD programmers.
APPLICATIONS
• Random logic
• Code converters
• Fault detectors
• Function generators
• Address mapping
• Multiplexing
9
10 11 12 13
B0 GND B1 B2 B3
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
t
(MAX)
ORDER CODE
PLUS153–10N
PLUS153–10A
DRAWING NUMBER
0408D
PD
20-Pin Plastic Dual-In-Line 300mil-wide
20-Pin Plastic Leaded Chip Carrier
10ns
10ns
0400E
PAL is a registered trademark of Advanced Micro Devices Corporation.
17
October 22, 1993
853–1508 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(18 × 42 × 10)
PLUS153–10
LOGIC DIAGRAM
(LOGIC TERMS–P)
(CONTROL TERMS)
1
2
3
4
5
6
7
8
I0
I1
I2
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
D
D
D
D
D
D
D
D
D
D
1 0
9
8
7
6
5
4
3
2
S
S
S
S
S
S
S
S
S
S
9
8
7
6
5
4
3
2
1
0
19
18
17
16
15
14
13
12
11
9
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
9
8
7
6
5
4
3
2
1
0
31
24 23
16 15
8
7
0
NOTES:
1. All programmed ‘AND’ gate locations are pulled to logic “1”.
2. All programmed ‘OR’ gate locations are pulled to logic “0”.
3.
Programmable connection.
18
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(18 × 42 × 10)
PLUS153–10
FUNCTIONAL DIAGRAM
P
P
D
D
9
31
0
0
I0
I7
B0
B9
S
9
B9
X
X
9
0
S
0
B0
1
ABSOLUTE MAXIMUM RATINGS
THERMAL RATINGS
TEMPERATURE
RATING
Maximum junction
Maximum ambient
150°C
SYMBOL
PARAMETER
Supply voltage
MIN
MAX
+7
UNIT
V
CC
V
DC
75°C
75°C
V
In
Input voltage
+5.5
+5.5
+30
V
DC
Allowable thermal rise
ambient to junction
V
OUT
Output voltage
V
DC
I
I
Input currents
–30
mA
mA
°C
IN
OUT
Output currents
+100
+75
T
amb
Operating free-air temperature range
Storage temperature range
0
T
stg
–65
+150
°C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device.
This is a stress rating only. Functional operation at these or any other condition above
those indicated in the operational and programming specification of the device is not
implied.
19
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(18 × 42 × 10)
PLUS153–10
DC ELECTRICAL CHARACTERISTICS
0°C ≤ T
≤ +75°C, 4.75 ≤ V ≤ 5.25V
amb
CC
LIMITS
1
SYMBOL
Input voltage
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.8
UNIT
2
V
V
V
Low
V
CC
= MIN
V
V
V
IL
High
V
CC
= MAX
2.0
IH
IC
Clamp
V
= MIN, I = –12mA
–0.8
–1.2
CC
IN
2
Output voltage
V
CC
= MIN
4
V
V
Low
I
= 15mA
= –2mA
0.4
2.9
0.5
V
V
OL
OL
5
High
I
2.4
OH
OH
9
Input current
V
CC
= MAX
I
I
Low
V
= 0.45V
–20
1
–100
40
µA
µA
IL
IN
High
V
= V
CC
IH
IN
Output current
V
= MAX
= 2.7V
= 0.45V
CC
8
I
Hi-Z state
V
OUT
0
80
–140
–70
200
µA
O(OFF)
V
OUT
–15
–30
165
3, 5, 6
I
I
Short circuit
V
= 0V
–15
mA
mA
OS
OUT
7
V
CC
supply current
V
CC
= MAX
CC
Capacitance
V
CC
= 5V
C
C
Input
I/O
V
= 2.0V
= 2.0V
8
pF
pF
IN
B
IN
V
15
B
NOTES:
1. All typical values are at V = 5V, T
= +25°C.
amb
CC
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with inputs I0 – I2 = 0V, inputs I3 – I5 = 4.5V, inputs I7 = 4.5V and I6 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the
same conditions except I7 = 0V.
5. Same conditions as Note 4 except I7 = +10V.
6. Duration of short circuit should not exceed 1 second.
7. I is measured with inputs I0 – I7 and B0 – B9 = 0V.
CC
8. Leakage values are a combination of input and output leakage.
9. I and I limits are for dedicated inputs only (I0 – I7).
IL
IH
20
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(18 × 42 × 10)
PLUS153–10
AC ELECTRICAL CHARACTERISTICS
0°C ≤ T
≤ +75°C, 4.75V ≤ V ≤ 5.25V, R = 300Ω, R = 390Ω
amb
CC 1 2
TEST
LIMITS
SYMBOL
PARAMETER
FROM
TO
CONDITION
MIN
TYP
MAX
10
UNIT
ns
2
t
Propagation Delay
Input +/–
Input +/–
Input +/–
Output +/–
Output –
Output +
C = 30pF
L
8
8
8
PD
OE
OD
1
t
Output Enable
C = 30pF
L
10
ns
1
t
Output Disable
C = 5pF
L
10
ns
NOTES:
1. For 3-State output; output enable times are tested with C = 30pF to the 1.5V level, and S is open for high-impedance to High tests and
L
1
closed for high-impedance to Low tests. Output disable times are tested with C = 5pF. High-to-High impedance tests are made to an output
L
voltage of V = (V – 0.5V) with S open, and Low-to-High impedance tests are made to the V = (V + 0.5V) level with S closed.
T
OH
1
T
OL
1
2. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORMS
TEST LOAD CIRCUIT
+3.0V
90%
+5V
V
S
CC
1
10%
90%
0V
C
C
2
R
1
1
t
t
F
5ns
5ns
R
B
Y
I0
I7
+3.0V
C
R
L
2
INPUTS
DUT
GND
B
W
10%
0V
B
Z
5ns
MEASUREMENTS:
5ns
B
X
OUTPUTS
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
NOTE:
and C are to bypass V to GND.
CC
C
1
2
Input Pulses
TIMING DEFINITIONS
TIMING DIAGRAM
SYMBOL
PARAMETER
+3V
0V
t
Propagation delay between
input and output.
I, B
1.5V
1.5V
1.5V
PD
OD
t
Delay between input change
and when output is off (Hi-Z
or High).
V
OH
B
1.5V
1.5V
V
T
t
Delay between input change
and when output reflects
specified output level.
V
OE
OL
t
t
t
PD
OD
OE
21
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(18 × 42 × 10)
PLUS153–10
LOGIC PROGRAMMING
PROGRAMMING AND
The PLUS153–10 is fully supported by
industry standard (JEDEC compatible) PLD
CAD tools, including Philips Semiconductors
SNAP design software package. ABEL and
CUPL design software packages also
support the PLUS153–10 architecture.
SOFTWARE SUPPORT
Refer to Section 9 (Development Software)
and Section 10 (Third-Party
Programmer/Software Support) of this data
handbook for additional information.
All packages allow Boolean and state
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.
OUTPUT POLARITY – (B)
PLUS153–10 logic designs can also be
generated using the program table entry
format, which is detailed on the following
page. This program table entry format is
supported by SNAP only.
S
B
X
S
B
X
To implement the desired logic functions, the
state of each logic variable from logic
equations (I, B, O, P, etc.) is assigned a
symbol. The symbols for TRUE,
ACTIVE LEVEL
CODE
H
ACTIVE LEVEL
CODE
L
1
HIGH
LOW
(INVERTING)
(NON-INVERTING)
COMPLEMENT, INACTIVE, PRESET, etc.,
are defined below.
AND ARRAY – (I, B)
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
P, D
P, D
P, D
P, D
STATE
CODE
O
STATE
I, B
CODE
H
STATE
I, B
CODE
L
STATE
DON’T CARE
CODE
–
1, 2
INACTIVE
OR ARRAY – (B)
VIRGIN STATE
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at “H” polarity.
P
P
2. All P terms are disabled.
n
S
S
3. All P terms are active on all outputs.
n
CODE
CODE
P
STATUS
1
P STATUS
n
INACTIVE
n
A
•
ACTIVE
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate P will be unconditionally inhibited if both the true and complement of an input (either
n
I or B) are left intact.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
22
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(18 × 42 × 10)
PLUS153–10
PROGRAM TABLE
POLARITY
AND
OR
T
E
R
B(I)
5
B(0)
I
M
7
6
5
4
3
2
1
0
9
8
7
6
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PIN
8
7
6
5
4
3
2
1
19 18 17 16 15 14 13 12 11
9
19 18 17 16 15 14 13 12 11
9
23
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic array
(18 × 42 × 10)
PLUS153–10
SNAP RESOURCE SUMMARY DESIGNATIONS
P
P
D
D
9
31
0
0
DIN153
I0
NIN153
I7
DIN153
NIN153
B0
B9
AND
CAND
TOUT153
S
9
B9
X
9
0
OR
S
0
B0
X
EXOR153
24
October 22, 1993
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