SC83C451CCA68-T [NXP]
IC 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC68, Microcontroller;
| 型号： | SC83C451CCA68-T |
| 厂家： | 
NXP |
| 描述： | IC 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC68, Microcontroller |
| 文件： | 总22页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
80C451/83C451/87C451
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
Product specification
1998 May 01
Supersedes data of 1998 Jan 19
IC20 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
DESCRIPTION
PIN CONFIGURATION
The Philips 8XC451 is an I/O expanded single-chip microcontroller
fabricated with Philips high-density CMOS technology. Philips
epitaxial substrate minimizes latch-up sensitivity.
9
1
61
10
26
60
44
The 8XC451 (includes the 80C451, 87C451 and 83C451) is a
functional extension of the 87C51 microcontroller with three
additional I/O ports and four I/O control lines for a total of 68 pins.
Four control lines associated with port 6 facilitate high-speed
asynchronous I/O functions.
LCC
The 8XC451 includes a 4k × 8 ROM (83C451) EPROM (87C451), a
128 × 8 RAM, 56 I/O, two 16-bit timer/counters, a five source, two
priority level, nested interrupt structure, a serial I/O port for either a
full duplex UART, I/O expansion, or multi-processor
communications, and on-chip oscillator and clock circuits. The
80C451 ROMless version includes all of the 83C451 features except
the on-board 4k × 8 ROM.
27
43
Pin
1
Function
Pin
Function
P4.2
Pin
Function
P5.3
EA/V
PP
P2.0/A8
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
2
P4.1
P5.4
3
P2.1/A9
P4.0
P5.5
4
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
P1.0
P5.6
5
P1.1
P5.7
The 87C451 has 4k of EPROM on-chip as program memory and is
otherwise identical to the 83C451.
6
P1.2
XTAL2
XTAL1
7
P1.3
The 8XC451 has two software selectable modes of reduced activity
for further power reduction; idle mode and power-down mode. Idle
mode freezes the CPU while allowing the RAM, timers, serial port,
and interrupt system to continue functioning. Power-down mode
freezes the oscillator, causing all other chip functions to be
inoperative while maintaining the RAM contents.
8
P1.4
V
SS
9
P1.5
ODS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
P1.6
IDS
P1.7
BFLAG
AFLAG
P6.0
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
P5.0
P6.1
P6.2
P6.3
FEATURES
• 80C51 based architecture
P6.4
V
P6.5
CC
P4.7
P4.6
P4.5
P4.4
P4.3
P6.6
P6.7
• Seven 8-bit I/O ports
PSEN
ALE/PROG
• Port 6 features:
– Eight data pins
P5.1
P5.2
SU00084A
– Four control pins
– Direct MPU bus interface
– Parallel printer interface
• On the microcontroller:
– 4k × 8 ROM (83C451)
4k × 8 EPROM (87C451)
ROMless version (80C451)
– 128 × 8 RAM
– Two 16-bit counter/timers
– Two external interrupts
• External memory addressing capability
– 64k ROM and 64k RAM
• Low power consumption:
– Normal operation: less than 24mA at 5V, 12MHz
– Idle mode
– Power-down mode
2
1998 May 01
853-0830 19327
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
BLOCK DIAGRAM
P2.0–P2.7
P0.0–P0.7
P4.0–P4.7
P5.0–5.7
PORT 2
DRIVERS
PORT 0
DRIVERS
PORT 4
DRIVERS
PORT 5
DRIVERS
V
V
CC
SS
4K x 8
ROM/EPROM
PORT 2
LATCH
RAM ADDR
REGISTER
PORT 0
LATCH
PORT 4
LATCH
PORT 5
LATCH
RAM
B
STACK
POINTER
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
PCON SCON TMOD TCON
ALU
TH0
TL0
TH1
TL1
PC
INCRE-
MENTER
SBUF
IE
IP
PSW
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
PROGRAM
COUNTER
PSEN
ALE/PROG
TIMING
AND
CONTROL
DPTR
EAV
PP
RST
PORT 1
LATCH
PORT 6
LATCH
PD
PORT 3
LATCH
OSCILLATOR
PORT 6
CONTROL/STATUS
PORT 1
DRIVERS
PORT 6
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
IDS ODS BFLAG
AFLAG
P1.0–P1.7
P6.0–P6.7
P3.0–P3.7
SU00086
3
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
ORDERING INFORMATION
TEMPERATURE RANGE °C
FREQ
MHz
DRAWING
NUMBER
1
ROMless
ROM
EPROM
AND PACKAGE
SC80C451CCA68
SC83C451CCA68
SC87C451CCA68 OTP
0 to +70, Plastic Leaded Chip Carrier,
0 to +70, Plastic Leaded Chip Carrier
3.5 to 12
3.5 to 16
SOT188-3
SOT188-3
SC80C451CGA68 SC83C451CGA68 SC87C451CGA68 OTP
NOTE:
1. OTP = One Time Programmable
LOGIC SYMBOL
V
V
SS
CC
XTAL1
ADDRESS AND
DATA BUS
XTAL2
RST
EA/V
PP
PSEN
ALE/PROG
RxD
TxD
INT0
INT1
T0
ADDRESS BUS
T1
WR
RD
ODS
IDS
PORT 6 CONTROL
BFLAG
AFLAG
SU00085
4
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
PIN DESCRIPTION
PIN
NO.
MNEMONIC
TYPE NAME AND FUNCTION
V
V
54
I
I
Ground: 0V reference.
SS
18
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
CC
P0.0–0.7
17-10
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order
address bus during accesses to external memory. External pull-ups are required during program
verification. Port 0 can sink/source eight LS TTL inputs.
P1.0–P1.7
P2.0–P2.7
27-34
2-9
I/O
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order
address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and
drive CMOS inputs without external pull-ups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address
bytes during access to external memory and receives the high-order address bits and control signals
during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without
external pull-ups.
P3.0–P3.7
36-43
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS
TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions
listed below:
36
37
38
39
40
41
42
43
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
P4.0–P4.7
P5.0–P5.7
P6.0–P6.7
26-19
44-51
59-66
I/O
I/O
I/O
Port 4: Port 4 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 4 can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups.
Port 5: Port 5 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 5 can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups.
Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can
sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in
a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that
serve the functions listed below:
ODS
55
56
57
58
35
I
I
ODS: Output data strobe
IDS
IDS: Input data strobe
BFLAG
AFLAG
RST
I/O
I/O
I
BFLAG: Bidirectional I/O pin with internal pull-ups
AFLAG: Bidirectional I/O pin with internal pull-ups
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal pull-down resistor permits a power-on reset using only an external capacitor connected to V
.
CC
ALE/PROG
68
I/O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during
an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except
during an external data memory access, at which time one ALE is skipped. ALE can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse
during EPROM programming.
PSEN
67
O
Program Store Enable: The read strobe to external program memory. PSEN is activated twice each
machine cycle during fetches from external program memory. However, when executing out of external
program memory, two activations of PSEN are skipped during each access to external program
memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source
eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low
during programming.
EA/V
1
I
Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU
executes out of internal program memory, unless the program counter exceeds 0FFFH. When EA is
held low, the CPU executes out of external program memory. EA must never be allowed to float. This
PP
pin also receives the 12.75V programming supply voltage (V ) during EPROM programming.
PP
XTAL1
XTAL2
53
52
I
Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the
external oscillator when an external oscillator is used.
O
Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when
an external oscillator is used.
5
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
I/O Port Structure
Processor Bus Interface
The 8XC451 has a total of seven parallel I/O ports. The first four
ports, P0 through P3, are identical in function to those present on
the 80C51 family. The added ports 4 and 5 are identical in function
to port 1; that is, they are standard quasi-bidirectional ports with no
alternate functions and the standard output drive characteristics.
Port 6 is a specialized 8-bit bidirectional I/O port with internal
pullups.
Port 6 allows the use of an 8XC451 as an element on a
microprocessor type bus. The host processor could be a general
purpose MPU or the data bus of a microcontroller like the 8XC451
itself. Setting up the 8XC451 as a processor bus interface allows
single or multiple microcontrollers to be used on a bus as flexible
peripheral processing elements. Applications can include: keyboard
scanners, serial I/O controllers, servo controllers, etc.
On reset, port 6 is programmed correctly (that is, Special Function
registers CSR and P6) for use as a bus interface. This prevents the
interface from disrupting data on the bus of a host processor during
power-up.
Ports 4 and 5
Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4
is an 8-bit port. Port 4 and port 5 pins with ones written to them, are
pulled high by the internal pull-ups, and in that state can be used as
inputs. Port 4 and 5 are addressed at the special function register
addresses shown in Table 1.
Standard Quasi-bidirectional I/O Port
To use port 6 as a common I/O port, all of the control pins should be
tied to ground. On hardware reset, bits 2-7 of the CSR are set to
one. With the control pins grounded, the port’s operation and
electrical characteristics will be identical to port 1 on the 80C51. No
further software initialization is required.
Port 6
Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups
(see Figure 1). This special port can sink/source three LS TTL
inputs and drive CMOS inputs without external pullups. The flexibility
of this port facilitates high-speed parallel data communications. This
port can be used as a standard I/O port, or in strobed modes of
operation in conjunction with four special control lines: ODS, IDS,
AFLAG, and BFLAG. Port 6 operating modes are controlled by the
port 6 control status register (CSR). Port 6 and the CSR are
addressed at the special function register addresses shown in Table
1. The following four control pins are used in conjunction with port 6:
Parallel Printer Port
The 8XC451 has the capacity to permit all of the intelligent features
of a common printer to be handled by a single chip. The features of
port 6 allow a parallel port to be designed with only line driving and
receiving chips required as additional hardware. The onboard UART
allows RS232 interfacing with only level shifting chips added. The
8-bit parallel ports 0 to 6 are ample to drive onboard control
functions, even when ports are used for external memory access,
interrupts, and other functions. The RAM addressing ability of ports
0 to 2 can be used to address up to 64k bytes of a hardware
buffer/spooler.
ODS – Output data strobe (Active Low) for port 6. ODS can be
programmed to control the port 6 output drivers and the output
buffer full flag (OBF), or to clear only the OBF flag bit in the CSR
(output-always mode). ODS is active low for output driver control.
the OBF flag can be programmed to be cleared on the negative or
positive edge of ODS.
In addition, either end of a parallel interface can be implemented
using port 6, and the interfaces can be interrupt driven or polled in
either case. For more detailed information on port 6 usage, refer to
the application notes entitled “80C451 Operation of Port 6” and
“256k Centronics Printer Buffer Using the SC87C451
Microcontroller.”
IDS – Input data strobe (Active Low) for port 6. IDS is used to
control the port 6 input latch and input buffer full flag (IBF) bit in the
CSR. The input data latch can be programmed to be transparent
when IDS is low and latched on the positive transition of IDS, or to
latch only on the positive transition of IDS. Correspondingly, the IBF
flag is set on the negative or positive transition of IDS.
CONTROL STATUS REGISTER
The control status register (CSR) establishes the mode of operation
for port 6 and indicates the current status of port 6 I/O registers. All
control status register bits can be read and written by the CPU,
except bits 0 and 1, which are read only. Reset writes ones to bits 2
through 7, and writes zeros to bits 0 and 1 (see Table 3).
BFLAG – BFLAG is a bidirectional I/O pin which can be
programmed to be an output, set high or low under program control,
or to output the state of the input buffer full flag. BFLAG can also be
programmed to input an enable signal for port 6. When BFLAG is
used as an enable input, port 6 output drivers are in the
high-impedance state, and the input latch does not respond to the
IDS strobe when BFLAG is high. Both features are enabled when
BFLAG is low. This feature facilitates the use of the SC8XC451 in
bused multiprocessor systems.
CSR.0 Input Buffer Full Flag (IBF) (Read Only) – The IBF bit is
set to a logic 1 when port 6 data is loaded into the input buffer under
control of IDS. This can occur on the negative or positive edge of
IDS, as determined by CSR.2 IBF is cleared when the CPU reads
the input buffer register.
AFLAG – AFLAG is a bidirectional I/O pin which can be
programmed to be an output set high or low under program control,
or to output the state of the output buffer full flag. AFLAG can also
be programmed to be an input which selects whether the contents of
the output buffer, or the contents of the port 6 control status register
will output on port 6. This feature grants complete port 6 status to
external devices.
CSR.1 Output Buffer Full Flag (OBF) (Read Only) – The OBF flag
is set to a logic 1 when the CPU writes to the port 6 output data
buffer. OBF is cleared by the positive or negative edge of ODS, as
determined by CSR.3.
CSR.2 IDS Mode Select (IDSM) – When CSR.2 = 0, a low-to-high
transition on the IDS pin sets the IBF flag. The Port 6 input buffer is
loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low
transition on the IDS pin sets the IBF flag. Port 6 input buffer is
transparent when IDS is low, and latched when IDS is high.
Port 6 can be used in a number of different ways to facilitate data
communication. It can be used as a processor bus interface, as a
standard quasi-bidirectional I/O port, or as a parallel printer port
(either polled or interrupt driven).
6
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
CSR.3 Output Buffer Full Flag Clear Mode (OBFC) – When
CSR.3 = 1, the positive edge of the ODS input clears the OBF flag.
When CSR.3 = 0, the negative edge of the ODS input clears the
OBF flag.
CSR.6, CSR.7 BFLAG Mode Select
(MB0, MB1) – Bits 6 and 7 select the mode operation as follows:
MB1 MB0
BFLAG Function
Logic 0 output
Logic 1 output
IBF flag output (CSR.0)
Port enable (PE)
0
0
1
1
0
1
0
1
CSR.4, CSR.5 AFLAG Mode Select
(MA0, MA1) – Bits 4 and 5 select the mode of operation for the
AFLAG pin as follows:
MA1 MA0
AFLAG Function
Logic 0 output
Logic 1 output
OBF flag output (CSR.1)
Select (SEL) input mode
In the port enable mode, IDS and ODS inputs are disabled when
BFLAG input is high. When the BFLAG input is low, the port is
enabled for I/O.
0
0
1
1
0
1
0
1
SPECIAL FUNCTION REGISTER ADDRESSES
The SFRs are identical to those of the standard 80C51 with the
exception of four registers that have been added to allow control of
the three additional I/O ports P4, P5, and P6. The additional
registers are P4, P5, P6, and CSR. Registers P4, P5, and P6
function as port latches for ports 4, 5, and 6, respectively. These
registers operate identically to those for ports 0 through 3 of the
80C51.
The select (SEL) input mode is used to determine whether the port 6
data register or the control status register is output on port 6. When
the select feature is enabled, the AFLAG input controls the source of
port 6 output data. A logic 0 on AFLAG input selects the port 6 data
register, and a logic 1 on AFLAG input selects the control status
register.
Table 1. Special Function Register Addresses
REGISTER ADDRESS
BIT ADDRESS
NAME
SYMBOL
ADDRESS
MSB
LSB
Port 4
Port 5
Port 6 data
Port 6 control status
P4
P5
P6
C0
C8
D8
E8
C7
CF
DF
EF
C6
CE
DE
EE
C5
CD
DD
ED
C4
CC
DC
EC
C3
CB
DB
EB
C2
CA
DA
EA
C1
C9
D9
E9
C0
C8
D8
E8
CSR
PORT 6
AFLAG
BFLAG ODS
IDS
BFLAG/ODS
MODE
(CSR.6/.7)
INPUT
BUFFER
(P6 READ)
IDS
MODE
OUTPUT
DRIVERS
INPUT BUFFER
FULL (CSR.0)
AFLAG
MODE
EDGE/LEVEL
SELECT (CSR.2)
MUX
(CSR.4/.5)
OUTPUT BUFFER
FULL (CSR.1)
CONTROL/STATUS
REGISTER (CSR)
OUTPUT BUFFER
(P6 WRITE)
INTERNAL BUS
SU00087
Figure 1. Port 6 Block Diagram
7
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
Table 2.
8XC451 Special Function Registers
DIRECT
DESCRIPTION
BIT NAMES AND ADDRESSES
RESET
VALUE
SYMBOL
ADDRESS MSB
LSB
E0
ACC*
B*
Accumulator
B register
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
EB
E2
F2
EA
E1
F1
00H
F0
00H
EF
EE
ED
EC
E9
E8
CSR*#
DPTR
DPH
Port 6 command/status
Data pointer (2 bytes)
Data pointer high
E8H
MB1
MB0
MA1
MA0
OBFC IDSM
OBF
IBF
FCH
83H
82H
00H
00H
DPL
Data pointer low
BF
–
BE
–
BD
–
BC
PS
BB
BA
B9
B8
IP*
Interrupt priority
B8H
PT1
PX1
PT0
PX0
xxx00000B
AF
EA
87
AE
–
AD
–
AC
ES
84
AB
ET1
83
AA
EX1
82
A9
ET0
81
A8
EX0
80
IE*
Interrupt enable
Port 0
A8H
80H
90H
A0H
B0H
C0H
C8H
D8H
0xx00000B
FFH
P0*
B6
96
A6
B6
C6
CE
DE
85
95
A5
B5
C5
CD
DD
P1*
Port 1
97
94
93
92
91
90
FFH
P2*
Port 2
A7
B7
C7
CF
DF
A4
B4
C4
CC
DC
A3
A2
A1
B1
C1
C9
D9
A0
B0
C0
C8
D8
FFH
P3*
Port 3
B3
B2
FFH
P4*#
P5*#
P6*#
Port 4
C3
CB
DB
C2
CA
DA
FFH
Port 5
FFH
Port 6
FFH
PCON
Power control
87H
SMOD
–
–
–
GF1
GF0
PD
IDL
0xxx0000B
D7
CY
D6
AC
D5
F0
D4
D3
D2
D1
–
D0
P
PSW*
SBUF
Program status word
Serial data buffer
D0H
99H
RS1
RS0
OV
00H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SCON*
SP
Serial port control
Stack pointer
98H
81H
SM0
SM1
SM2
REN
TB8
RB8
00H
07H
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer/counter control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
TMOD
TH0
TH1
TL0
Timer/counter mode
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
89H
8CH
8DH
8AH
8BH
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
00H
00H
00H
00H
TL1
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
8
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
Table 3. Control Status Register (CSR)
Bit 7
Bit 6
Bit 5
Bit 4
MA0
Bit 3
Bit 2
Bit 1
OBF
Bit 0
IBF
MB1
MB0
MA1
OBFC
IDSM
BFLAG Mode Select
AFLAG Mode Select
Output Buffer
Flag Clear
Mode
Input Data
Strobe Mode
Output Buffer
Flag Full
Input Buffer
Flag Full
0/0 = Logic 0 output*
0/1 = Logic 1 output*
1/0 = IBF output
1/1 = PE input
0/0 = Logic 0 output*
0/1 = Logic 1 output*
1/0 = OBF output
1/1 = SEL input
0 = Negative
edge of ODS
1 = Positive
edge o ODS
0 = Positive
edge of IDS
1 = Low level
of IDS
0 = Output
data buffer
empty
1 = Output
data buffer full
0 = Input data
buffer empty
1 = Input data
buffer full
(0 = Select)
(0 = Select)
(1 = Disable I/O)
(1 = Control/status)
NOTE:
*
Output-always mode: MB1 = 0, MA1 = 1, and MA0 = 0. In this mode, port 6 is always enabled for output. ODS only clears the OBF flag.
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
0 to +70
UNIT
°C
Operating temperature under bias
Storage temperature range
–65 to +150
–0.5 to +6.5
1.5
°C
Voltage on any other pin to V
V
SS
Power dissipation (based on package heat transfer limitations, not device power consumption)
W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
9
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
1
DC ELECTRICAL CHARACTERISTICS
amb
T
= 0°C to +70°C, V = 5V ±10%, V = 0V (87C451, 83C451, 80C451)
CC SS
TEST
LIMITS
1
SYMBOL
PARAMETER
CONDITIONS
MIN
–0.5
0
TYPICAL
MAX
0.2V –0.1
UNIT
V
V
V
V
V
V
V
V
Input low voltage; except EA
IL
CC
Input low voltage to EA
0.2V –0.3
V
IL1
IH
CC
Input high voltage; except XTAL1, RST
Input high voltage; XTAL1, RST
Output low voltage; ports 1, 2, 3, 4, 5, 6
Output low voltage; port 0, ALE, PSEN
Output high voltage; ports 1, 2, 3, 4, 5, 6
0.2V +0.9
V
+0.5
+0.5
V
CC
CC
CC
0.7V
V
V
IH1
OL
OL1
OH
CC
2
I
I
I
= 1.6mA
0.45
0.45
V
OL
OL
OH
2
= 3.2mA
V
= –60µA,
= –25µA
= –10µA
2.4
V
V
V
I
I
0.75V
OH
OH
CC
CC
0.9V
V
OH1
Output high voltage (port 0 in external bus mode, ALE,
PSEN)
I
I
= –800µA,
= –300µA
2.4
V
V
V
OH
OH
I
3
0.75V
CC
CC
= –80µA
0.9V
OH
I
I
I
I
Logical 0 input current,; ports 1, 2, 3, 4, 5, 6
Logical 1-to-0 transition current; ports 1, 2, 3, 4, 5, 6
Input leakage current; port 0
V
= 0.45V
–50
–650
+10
µA
µA
µA
IL
IN
See note 4
= V or V
IH
TL
LI
V
IN
IL
Power supply current:
See note 6
CC
5
Active mode @ 12MHz
11.5
1.3
3
25
4
50
mA
mA
µA
5
Idle mode @ 12MHz
Power down mode
R
C
Internal reset pull-down resistor
50
300
10
kΩ
RST
IO
7
Pin capacitance
pF
NOTES:
1. Typical ratings are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The values listed are
at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2V.
IN
5. I
at other frequencies is given by:
CCMAX
Active mode: I
= 0.94 X FREQ + 13.71
= 0.14 X FREQ +2.31
CCMAX
Idle mode: I
CCMAX
where FREQ is the external oscillator frequency in MHz. I
is given in mA. See Figure 13.
CCMAX
6. See Figures 14 through 17 for I test conditions.
CC
7. C applies to ports 1 through 6, AFLAG, BFLAG, XTAL1, XTAL2.
IO
10
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
1
AC ELECTRICAL CHARACTERISTICS
2
T
= 0°C to +70°C, V = 5V ±10%, V = 0V (87C451, 83C451, 80C451)
amb
CC SS
12MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency: Speed Versions
MIN
MAX
MIN
MAX
UNIT
CLCL
SC8XC451
SC8XC451
C
G
3.5
3.5
12
16
MHz
MHz
t
t
t
t
t
t
t
t
t
t
t
2
2
2
2
2
2
2
2
2
2
2
ALE pulse width
127
28
2t
–40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
t
t
–55
AVLL
LLAX
LLIV
CLCL
CLCL
48
–35
234
145
4t
3t
–100
CLCL
43
t
–40
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
205
3t
CLCL
–45
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
CLCL
0
0
59
312
10
t
–25
CLCL
5t
CLCL
–105
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
3, 4
RD pulse width
400
400
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
252
5t
–165
CLCL
0
0
Data float after RD
97
2t
–70
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
517
585
300
8t
–150
–165
CLCL
CLCL
9t
AVDV
LLWL
AVWL
QVWX
WHQX
RLAZ
WHLH
200
203
23
3t
–50
3t
+50
CLCL
CLCL
4t
t
–130
–60
CLCL
CLCL
CLCL
33
t
–50
RD low to address float
RD or WR high to ALE high
0
0
43
123
t
–40
t
+40
CLCL
CLCL
Shift Register
t
t
t
t
t
5
5
5
5
5
Serial port clock cycle time
1.0
700
50
0
12t
µs
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
–117
0
700
10t
–133
CLCL
NOTES: SEE NEXT PAGE
11
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
1
AC ELECTRICAL CHARACTERISTICS (continued)
2
T
= 0°C to +70°C, V = 5V ±10%, V = 0V (87C451, 83C451, 80C451)
amb
CC SS
12MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
Port 6 input (input rise and fall times = 5ns)
t
t
t
t
t
8
8
8
8
9
PE width
270
270
0
3t
3t
+20
ns
ns
ns
ns
ns
FLFH
CLCL
IDS width
+20
ILIH
CLCL
Data setup to IDS high or PE high
Data hold after IDS high or PE high
IDS to BFLAG (IBF) delay
0
DVIH
IHDX
IVFV
30
30
130
130
Port 6 output
t
t
t
t
t
t
t
6
7
6
6
6
6
7
ODS width
270
3t
CLCL
+20
ns
ns
ns
ns
ns
ns
ns
OLOH
FVDV
OLDV
OHDZ
OVFV
FLDV
OHFH
SEL to data out delay
ODS to data out delay
ODS to data float delay
ODS to AFLAG (OBF) delay
PE to data out delay
ODS to AFLAG (SEL) delay
85
80
85
80
35
35
100
120
100
120
100
100
External Clock
t
t
t
t
10
10
10
10
High time
Low time
Rise time
Fall time
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
20
20
20
20
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
12
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
P – PSEN
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
Q – Output data
R – RD signal
designations are:
A – Address
t – Time
V – Valid
C – Clock
W – WR signal
D – Input data
H – Logic level high
X – No longer a valid logic level
Z – Float
I
– Instruction (program memory contents)
Examples: t
= Time for address valid to ALE low.
= Time for ALE low to PSEN low.
AVLL
LLPL
L – Logic level low, or ALE
t
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 2. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00007
Figure 3. External Data Memory Read Cycle
13
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
A0–A15 FROM PCH
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPH
SU00008
Figure 4. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 5. Shift Register Mode Timing
14
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
OBF (AFLAG)
t
OVFV
t
OVFV
PE (BFLAG)
t
OLOH
ODS
t
t
OHDZ
OLDV
PORT 6
t
FLDV
SU00088
Figure 6. Port 6 Output
ODS
t
OHFH
SEL (AFLAG)
t
t
FVDV
FVDV
PORT 6
DATA
CSR
DATA
SU00089
Figure 7. Port 6 Select Mode
t
FLFH
PE (BFLAG)
t
ILIH
IDS
t
IHDZ
t
DVIH
PORT 6
SU00090
Figure 8. Port 6 Input
IBF (BFLAG)
t
t
IVFV
IVFV
IDS
SU00091A
Figure 9. IBF Flag Output
15
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
V
–0.5
CC
0.7V
CC
–0.1
0.45V
0.2V
CC
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 10. External Clock Drive
V
–0.5
CC
0.2V
0.2V
+0.9
–0.1
CC
CC
0.45V
NOTE:
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
CC
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
IH
IL
SU00010
Figure 11. AC Testing Input/Output
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
V
LOAD
–0.1V
LOAD
+0.1V
OL
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V /V level occurs. I /I ≥ ±20mA.
OH OL
OH OL
SU00011
Figure 12. Float Waveform
30
25
20
15
10
5
MAX ACTIVE MODE
TYP ACTIVE MODE
I
mA
CC
MAX IDLE MODE
TYP IDLE MODE
4MHz
8MHz
12MHz
16MHz
FREQ AT XTAL1
VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF THE DEVICE UNDER TEST.
SU00092
Figure 13.
I
vs. FREQ
CC
16
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
V
V
CC
CC
I
I
CC
CC
V
V
CC
CC
V
V
V
RST
CC
CC
CC
P0
P0
EA
RST
EA
V
(NC)
XTAL2
XTAL1
CC
(NC)
XTAL2
V
CC
CLOCK SIGNAL
CLOCK SIGNAL
XTAL1
V
IDS
V
SS
IDS
SS
ODS
ODS
SU00093
SU00094
Figure 14.
I
Test Condition, Active Mode
Figure 15.
I
Test Condition, Idle Mode
CC
CC
All other pins are disconnected
All other pins are disconnected
V
–0.5
CC
0.7V
CC
–0.1
0.45V
0.2V
CC
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 16. Clock Signal Waveform for I Tests in Active and Idle Modes
CC
t
= t
= 5ns
CHCL
CLCH
V
CC
CC
I
CC
V
CC
RST
V
V
P0
EA
(NC)
XTAL2
XTAL1
CC
V
IDS
SS
ODS
SU00095
Figure 17.
I
Test Condition, Power Down Mode
CC
All other pins are disconnected. V = 2V to 5.5V
CC
17
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.
EPROM CHARACTERISTICS
The 87C451 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for V (programming supply voltage) and in the width and
number of the ALE/PROG pulses.
PP
Note that the EA/V pin must not be allowed to go above the
PP
maximum specified V level for any amount of time. Even a narrow
PP
glitch above that voltage can cause permanent damage to the
The 87C451 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C451 manufactured by
Philips Semiconductors.
device. The V source should be well regulated and free of glitches
PP
and overshoot.
Program Verification
Table 4 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 18 and 19. Figure 20 shows the
circuit configuration for normal program memory verification.
If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be read is applied to ports 1 and 2 as shown in
Figure 20. The other pins are held at the ‘Verify Code Data’ levels
indicated in Table 4. The contents of the address location will be
emitted on port 0. External pull-ups are required on port 0 for this
operation.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 18. Note that the 87C451 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 18. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 4 are held at the ‘Program
Code Data’ levels indicated in Table 4. The ALE/PROG is pulsed
low 25 times as shown in Figure 19.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = 90H indicates 87C451
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 1FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 4, and
which satisfies the timing specifications, is suitable.
To program the lock bits, repeat the 25 pulse programming
sequence using the ‘Pgm Lock Bit’ levels. After one lock bit is
Table 4. EPROM Programming Modes
MODE
RST
PSEN
ALE/PROG
EA/V
P2.7
P2.6
P3.7
P3.6
PP
Read signature
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
Program code data
Verify code data
Pgm encryption table
Pgm lock bit 1
0*
1
V
PP
1
0*
0*
0*
V
PP
PP
PP
V
V
Pgm lock bit 2
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. V = 12.75V ±0.25V.
PP
3. V = 5V ±10% during programming and verification.
CC
*
ALE/PROG receives 25 programming pulses while V is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a
PP
minimum of 10µs.
Trademark phrase of Intel Corporation.
18
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
+5V
V
CC
P0
A0–A7
PGM DATA
P1
1
1
1
RST
P3.6
+12.75V
EA/V
PP
25 100µs PULSES TO GROUND
ALE/PROG
PSEN
0
1
87C451
P3.7
XTAL2
P2.7
0
P2.6
4–6MHz
XTAL1
A8–A12
P2.0–P2.4
V
SS
SU00096
Figure 18. Programming Configuration
25 PULSES
1
0
ALE/PROG:
ALE/PROG:
10µs MIN
100µs+10
1
0
SU00018
Figure 19. PROG Waveform
+5V
V
CC
P0
A0–A7
PGM DATA
P1
1
1
1
RST
P3.6
1
1
EA/V
PP
ALE/PROG
PSEN
0
87C451
P3.7
0 ENABLE
XTAL2
P2.7
0
P2.6
4–6MHz
XTAL1
A8–A12
P2.0–P2.4
V
SS
SU00097
Figure 20. Program Verification
19
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
T
amb
= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 21)
CC SS
SYMBOL
PARAMETER
MIN
MAX
13.0
50
UNIT
V
V
PP
Programming supply voltage
Programming supply current
Oscillator frequency
12.5
I
PP
mA
MHz
1/t
CLCL
4
6
t
t
t
t
t
t
t
t
t
t
t
t
Address setup to PROG low
Address hold after PROG
Data setup to PROG low
Data hold after PROG
48t
AVGL
CLCL
CLCL
CLCL
CLCL
CLCL
48t
48t
48t
48t
GHAX
DVGL
GHDX
EHSH
SHGL
GHSL
GLGH
AVQV
ELQZ
EHQZ
GHGL
P2.7 (ENABLE) high to V
PP
V
PP
V
PP
setup to PROG low
hold after PROG
10
10
90
µs
µs
µs
PROG width
110
Address to data valid
48t
CLCL
CLCL
CLCL
ENABLE low to data valid
Data float after ENABLE
PROG high to PROG low
48t
48t
0
10
µs
PROGRAMMING*
ADDRESS
VERIFICATION*
ADDRESS
P1.0–P1.7
P2.0–P2.4
t
AVQV
PORT 0
DATA IN
DATA OUT
t
t
t
DVGL
GHDX
GHAX
t
AVGL
ALE/PROG
t
t
GLGH
GHGL
t
t
SHGL
GHSL
LOGIC 1
LOGIC 1
EA/V
PP
LOGIC 0
t
t
t
EHSH
ELQV
EHQZ
P2.7
ENABLE
SU00020
NOTE:
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 18.
FOR VERIFICATION CONDITIONS SEE FIGURE 20.
Figure 21. EPROM Programming and Verification
20
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
21
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 05-98
Document order number:
9397 75003857
Philips
Semiconductors
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