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PAC407BCA

更新时间：2025-07-09 10:39:59
品牌：PIXART
描述：CMOS VGA DIGITAL IMAGE SENSOR

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PAC407BCA 概述

CMOS VGA DIGITAL IMAGE SENSOR VGA CMOS数字图像传感器

PAC407BCA 数据手册

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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
PAC407 CMOS VGA DIGITAL IMAGE SENSOR  
General Description:  
The PAC407 is a highly integrated CMOS active-pixel image sensor that has a VGA resolution (644H x 484V or  
640H x 480V). The PAC407 outputs 8-bit data with wide range of formats include RGB Raw Data, RGB565 and  
YCbCr422 through an 8-bit parallel data bus. It is available in 32-pin LCC and 22-pin CSP.  
To have an excellent image quality, the PAC407 supports all require image processing functions, includes  
Automatic Exposure Control, Automatic White Balance, Gamma Correction, Color Saturation Correction, Edge  
Enhancement, Lens Shading Compensation and Defect Compensation. These functions are all programmable via  
I2CTM serial control bus.  
Features:  
ƒ <25mA(~15 fps) power dissipation  
ƒ I2CTM Serial Interface  
ƒ VGA, QVGA, QQVGA (Sub-sampling) and  
Window Of Interest (WOI) outputs with 8-bit  
parallel data mode, the formats include:  
ƒ Pin-to-pin compatible to OV7648  
oRaw Data  
(Except for the polarity of RESET pin)  
oRGB565  
Key Specification:  
oYCbCr422  
ƒ VGA resolution, ~1/4” Lens  
o644 x 484 pixels (Raw Data)  
o640 x 480 pixels (YUV/RGB)  
ƒ Bayer-RGB color filter array  
ƒ Continuous variable frame time(1/2sec~1/30sec)  
ƒ On-chip 10-bit pipelined A/D converter  
ƒ On-chip programmable gain amplifier  
o4-bit color gain amplifier (x1~x2)  
o4-bit global gain amplifier (x1~x2)  
ƒ Automatic image control functions:  
oAEC: Automatic Exposure Control  
oAWB: Automatic White Balance  
ƒ Image quality control:  
Supply Voltage  
2.8V to 3.3V  
Resolution  
640x480(YUV) or 644x484(Raw)  
4.5mm (~1/4”Optic)  
5.6µmx5.6µm  
Array diagonal  
Pixel Size  
Frame rate  
~30 fps  
System clock  
Max. pixel rate (YUV)  
Up to 26 MHz  
26 MHz  
BCA  
Sensitivity  
BCW  
1.4 V/Lux-Sec  
1.2 V/Lux-Sec  
Color filter  
Exposure Time  
Scan Mode  
S/N Ratio  
RGB Bayer Pattern  
~ 4us to 0.1412s  
oColor Saturation  
oGamma Correction  
Progressive  
> 45 dB  
oSharpness (Edge Enhancement)  
oSmooth filter for skin  
ƒ Defect Compensation  
BCA  
Package  
32-pin LCC  
22-pin CSP  
BCW  
ƒ Lens Shading Compensation  
ƒ X Flip Function for mirrored image  
ƒ Digital Zoom (x2, x4)  
Note1: Only 2 decouple-capacitors needed.  
Note2: Excellent sensitivity.  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
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E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
1. Pin Assignment  
1.1. PAC407BCW pin assignment  
PXD5  
RESET#  
PXD7  
VDDMA/MD HSYNC  
15  
13  
11  
9
7
PXD6  
VSSD  
SYSCLK  
PXCK  
VSYNC  
14  
12  
10  
8
6
PXD4  
VCC  
PAC407 BCW  
16  
5
-- Top View --  
PXD1  
SCL  
PXD3  
VDDA  
VREF  
17  
19  
21  
2
4
PXD2  
SDA  
PXD0  
VSSA  
CSB  
18  
20  
22  
1
3
Figure 1.1. PAC407BCW pin assignment  
Pin No.  
Name  
Type  
Description  
1
2
VSSA  
VDDA  
PWDN  
VREF  
GND  
PWR  
IN  
Analog ground.  
Connected with a 0.1uF capacitor  
3
Power Down (chip power down when high).  
Internal voltage reference.  
N.C.  
4
IN  
5
VCC  
PWR  
OUT  
OUT  
OUT  
PWR  
IN  
6
VSYNC  
HSYNC  
PXCK  
VDDMA/MD  
SYSCLK  
RESET#  
VSSD  
Vertical synchronization signal.  
Horizontal synchronization signal.  
Pixel clock output.  
7
8
9
Main Power (include IO pad power), 2.8V to 3.3V.  
Master clock input.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
IN  
Resets all registers to their default values (chip reset when low).  
Digital ground.  
GND  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
IN  
PXD7  
Digital data out.  
PXD6  
Digital data out.  
PXD5  
Digital data out.  
PXD4  
Digital data out.  
PXD3  
Digital data out.  
PXD2  
Digital data out.  
PXD1  
Digital data out.  
PXD0  
Digital data out.  
I2CTM clock.  
I2CTM data. Internal pull high resister is 10KΩ.  
SCL  
SDA  
I/O  
Version 1.7, 13 Sep 2004  
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PAC407BCA/PAC407BCW  
1.2. PAC407BCA  
CMOS Image Sensor IC  
10  
9
8
7
6
5
11  
12  
13  
14  
4
3
VHRST  
VLRST  
PX6  
HSYNC  
VPN  
15  
2
1
VPP  
PAC407 BCA  
VDDMA  
VRT  
16  
17  
VCC  
PX4  
32  
-- Top View --  
31  
30  
29  
18  
19  
VREF  
VDDA  
PWDN  
PX3  
NC  
20  
NC  
21  
22  
23  
24  
25  
26  
27  
28  
Figure 1.2. PAC407BCA pin assignment  
Pin No.  
Name  
Type  
Description  
1
2
VDDMA  
VPP  
PWR  
Main analog power, 2.8V to 3.3V.  
BYPASS Analog test output P  
BYPASS Analog test output N  
3
VPN  
4
HSYNC  
VSYNC  
VDDMD  
PXCK  
RESET#  
SCLK  
PX7  
OUT  
OUT  
PWR  
OUT  
IN  
Horizontal synchronization signal.  
Vertical synchronization signal.  
5
6
Main digital power (include IO pad power), 2.8V to 3.3V.  
7
Pixel clock output.  
8
Resets all registers to their default values (chip reset when low).  
9
IN  
Master clock input.  
Digital data out.  
Digital ground.  
Digital data out.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
OUT  
GND  
OUT  
VSSD  
PX5  
VHRST  
VLRST  
PX6  
BYPASS Test pin  
BYPASS Test pin  
OUT  
PWR  
OUT  
OUT  
-
Digital data out.  
VCC  
N.C.  
PX4  
Digital data out.  
Digital data out.  
-
PX3  
NC  
NC  
-
-
PX2  
OUT  
OUT  
OUT  
IN  
Digital data out.  
Digital data out.  
Digital data out.  
I2CTM clock.  
PX1  
PX0  
SCL  
Version 1.7, 13 Sep 2004  
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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
25  
26  
27  
28  
29  
30  
31  
32  
SDA  
VCM  
VSSA  
VRB  
I/O  
BYPASS Voltage common mode  
GND Analog ground.  
BYPASS Voltage reference bottom  
I2CTM data. Internal pull high resister is 10KΩ.  
PWDN  
VDDA  
VREF  
VRT  
IN  
PWR  
IN  
Power Down (chip power down if high).  
Connected with a 0.1uF capacitor  
Internal voltage reference.  
BYPASS Voltage reference top  
Note: The pin-out difference between PAC407BCA and PAS302BCA are pin1 and pin32.  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
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PAC407BCA/PAC407BCW  
2. Block Diagram  
VGA  
CMOS Image Sensor IC  
Timing  
Generator  
Serial  
Interface  
Image  
Core  
AFE  
Sensor Interface  
Data Flow  
Control Flow  
Register  
Bank  
AE  
AWB  
Pipelined  
Image  
Flow  
Processor  
Output Formatter  
YUV data  
Figure 2.1. PAC407 block diagram  
The PAC407 is a 1/4” CMOS imaging sensor with 644x488 physical pixels. The active region of sensor  
array is 644x484. The sensor array is cover with Bayer pattern color filters and micro-lens. The first pixel  
location <0,0> is programmable in 2 direction (X and Y) and the default value is at the left-down side of  
sensor array.  
After a programmable exposure time, the signals of image are sampled first with CDS (Correlated Double  
Sampling) block to improve S/N ratio and reduce fixed pattern noise (FPN).  
Three analog gain stages are implemented before signals are transferred to 10-Bit ADC. The front gain  
stage (FG) can be programmed to fit the saturation level of sensor to the full-range input of ADC. The  
programmable color gain stage (CG) is used to balance the luminance response difference between B, G  
and R color. The global gain stage (GG) is programmed to adapt the gain to the image luminance.  
After three gain stages, the signals will be digitized by the on-chip 10-Bit ADC. After the image data have  
been digitized, further adjustment to the signal can be applied before the data is output to next stage.  
Version 1.7, 13 Sep 2004  
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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
3. Function Description  
„ Defect Compensation  
The Defect Compensation block can detect the possible defect pixel and replace it with average output of  
like-colored pixels from near side of defect pixel. This function can be programmed to enable/disable by  
user.  
„ Hardware Windowing  
Users are allowed to define window size and window location in PAC407. The location of window can be  
anywhere in the sensor array. Window location and size are determined by different register settings.  
„ Sub-Sampling  
PAC407 can be programmed to output image in QVGA, QQVGA and CIF size. In QVGA sub-sampling  
mode, both vertical and horizontal pixels are sub-sampling at 1/2, while in QQVGA sub-sampling mode,  
both vertical and horizontal pixels are sub-sampling at 1/4.  
„ Digital Zoom  
By programming Hardware Windowing registers and Sub-sampling registers, PAC407supports 2X and  
4X digital zoom.  
„ Automatic White Balance  
In digital image applications, color balance is typically achieved by automatic white balance (AWB).  
PAC407 can adjust its color spectrum sensitivity to the scene such that the resulting image on the average  
has an equal amount of all color components. The AWB mechanism can be set and adjusted by registers.  
„ Color Saturation  
If one color is more saturated than others, it will dominate the image. If the colors aren't saturated enough,  
the image might appear lifeless. Hence, PAC407 can enable color saturation function by setting registers  
to provide a more vivid image for user.  
„ Lens Shading Compensation  
In order to compensate the effect of the attenuation due to poorly optic component, PAC407 has a series  
of registers to eliminate the shading effect.  
„ Gamma Correction  
To realize a more brilliant image quality, PAC407 includes gamma correction function. Gamma correction  
performs on the luminance element of the image and allows compensating for non-linear dependence of  
the display device output against driving signal (ex. monitor brightness against CRT voltage). Gamma  
correction curve is shown as below, and some dedicated registers can adjust it.  
Version 1.7, 13 Sep 2004  
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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
Y9  
Y8  
Y7  
Y6  
Y5  
Y4  
Y3  
Y2  
Y1  
X
Y0  
64  
128  
192  
255  
8 16 32 48  
4
Input Luminance  
Figure 4.1 Gamma Correction curve  
„ Power Down Mode  
Because PAC407 is divided by two portions: Sensor and ASIC (ISP), software power down procedure  
should be performed on both portions. The PAC407 supports 2 power-down modes:  
ƒ Software power down  
Setting register “ISP_EnH”=0 in ASIC and register “Sw_PwrDn”=1 in Sensor.  
ƒ Hardware power down  
Pull PWDN pin to high to power down the chip. The chip will go into standby state.  
„ Reset Mode  
The PAC407 can be reseted by setting registers or by pulling low RESET# pin. PAC407 supports 2 reset  
modes:  
ƒ Software reset  
Setting register “Sw_Reset”=1 in Sensor and register “Software_Reset”=1 in ASIC to reset all the  
I2CTM registers.  
ƒ Hardware reset  
Pulling RESET# pin to low to reset the entire chip.  
Version 1.7, 13 Sep 2004  
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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
4. Output Format  
4.1. Sensor Output Format  
644 - Column  
. . . .  
. . . .  
G
B
R
G
G
B
R
G
G
B
R
G
G
B
R
G
644 X 484  
pixels  
. . . .  
. . . .  
G
B
R
G
G
B
R
G
G
B
R
G
G
B
R
G
Figure 4.1 RAW data output  
640 - Column  
RGB RGB RGB RGB  
565 565 565 565  
RGB RGB RGB RGB  
565 565 565 565  
. . . .  
. . . .  
RGB RGB RGB RGB  
565 565 565 565  
RGB RGB RGB RGB  
565 565 565 565  
640 X 480  
pixels  
RGB RGB RGB RGB  
565 565 565 565  
RGB RGB RGB RGB  
565 565 565 565  
. . . .  
. . . .  
RGB RGB RGB RGB  
565 565 565 565  
RGB RGB RGB RGB  
565 565 565 565  
Figure 4.2 RGB565 output  
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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
640 - Column  
. . . .  
. . . .  
YCb YCr YCb YCr  
YCb YCr YCb YCr  
YCb YCr YCb YCr  
YCb YCr YCb YCr  
640 X 480  
pixels  
. . . .  
. . . .  
YCb YCr YCb YCr  
YCb YCr YCb YCr  
YCb YCr YCb YCr  
YCb YCr YCb YCr  
Figure 4.3 YCbCr422 Output  
4.2. Output Timing  
V/HSYNC  
G R G R  
B G B G  
B G B G  
G R G R  
PX[7:0]  
PXCK  
Figure 4.4 Inter-Line Timing  
VSYNC  
HSYNC  
PX[7:0]  
Last Row  
Last Row  
Row 0  
Row 1  
Row 2  
Row 3  
Row 4  
Row 5  
Row 0  
Figure 4.5 Inter-Frame Timing  
Version 1.7, 13 Sep 2004  
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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
PXCK  
HSYNC  
Invalid  
PX[7:0]  
Data  
B
G
B
G
Figure 4.6 RAW Data Output Timing  
PXCK  
HSYNC  
Invalid  
PX[7:0]  
Data  
Y1H  
Y1L Y2H  
Y2L  
First Byte  
Second Byte  
PX[7] R4  
PX[6] R3  
PX[5] R2  
PX[4] R1  
PX[3] R0  
PX[2] G5  
PX[1] G4  
PX[0] G3  
G2 PX[7]  
G1 PX[6]  
G0 PX[5]  
B4 PX[4]  
B3 PX[3]  
B2 PX[2]  
B1 PX[1]  
B0 PX[0]  
Figure 4.7 RGB565 Output Timing  
PXCK  
HSYNC  
Invalid  
PX[7:0]  
Data  
Y
Cb  
Y
Cr  
Figure 4.8 YCbCr422 Output Timing  
Since the output stream of YCbCr422 or RGB565 format is two times then sensor raw data output, we  
should double the pixel clock rate while data format is in YCbCr422 or RGB565 mode.  
The minimum of Np=1 in sensor timing generator that means the pixel clock rate is the same as system  
clock rate. Noticed that Np=1 can only be used in sensor raw data mode. When PAC407 is operated in  
YCbCr422 or RGB565 mode, the minimum of Np should be 2. Besides, when Np is odd number, the duty  
cycle of PXCK will not be 50%.  
Note: The detail timing description for raw data output format could be found in PAS302 spec.  
Version 1.7, 13 Sep 2004  
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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
5. I2CTM Bus  
PAC407 supports I2CTM bus transfer protocol and acts as slave device. The 7 bits unique slave address  
is 1000000 and the bus supports receiving / transmitting speed up to 400kHz.  
5.1. I2CTM Bus Overview  
There are only two lines SDA (serial data) and SCL (serial clock) carry information between the  
devices which are connected by I2CTM bus. Normally both SDA and SCL lines are open collector  
structure and pulled high by external pull-up resistors.  
Only the master can initiate a transfer (start), generate clock signals, and terminate a transfer (stop).  
Start Condition :  
A high to low transition of the SDA line while SCL is high defines a start condition.  
Stop Condition :  
A low to high transition of the SDA line while SCL is high defines a stop condition.  
Valid Data:  
The data on the SDA line must be stable during the high period of the SCL clock. Within each byte,  
MSB is always transferred first. Read/write control bit is the LSB of the first byte.  
Both the master and slave can transmit and receive data from the bus.  
Acknowledge :  
The receiving device should pull down the SDA line during high period of the SCL clock line when a  
byte was transferred completely by transmitter. When in the case of that a master received data from a  
slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master  
read cycle.  
SDA  
SCL  
S
P
Start  
Condition  
Stop  
Condition  
Figure 5-1: Start and Stop Conditions  
SDA  
DATA  
DATA  
STABLE  
CHANGE  
ALLOWED  
SCL  
Figure 5-2: Valid Data  
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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
5.2. Data Transfer Format  
5.2.1. Master transmits data to slave (write cycle)  
„
„
„
„
S: Start  
A: Acknowledge by slave  
P: Stop  
RW: The LSB of 1ST byte to decide whether current cycle is read or write cycle.  
If RW=1 that means read cycle, if RW=0 that means write cycle.  
„
SUBADDRESS: The address values of PAC407 internal control registers  
(Please refer to PAC407 register description)  
1ST BYTE  
2ND BYTE  
n BYTEs + A  
S
SLAVE ID (7 BIT)  
RW  
A
SUBADDRESS (8 BIT)  
A
DATA  
A
DATA  
A
P
MSB  
LSB=0  
1ST BYTE  
2ND BYTE  
n BYTEs + A  
S
SLAVE ID (7 BIT)  
RW  
A
SUBADDRESS (8 BIT)  
A
DATA  
A
DATA  
A
P
MSB  
LSB=0  
During the write cycle, the master generates start condition and then places the 1st byte data that  
combined slave address (7 bits) with a read/write control bit on SDA line. After slave(PAC407) issues  
acknowledgment, the master places 2nd byte (sub-address) data on SDA line. And then following the  
slave’s( PAC407) acknowledgment, the master places the 8 bits data on SDA line and transmit to PAC407  
control register (address was assigned by 2nd byte). After PAC407 issue acknowledgment, the master can  
generate a stop condition to end this write cycle. In the condition of multi-byte write, the PAC407  
sub-address will be increased automatically after each DATA byte has been transferred. The Data and A  
cycles are repeated until last byte write. Every control registers value inside PAC407 can be programming  
via this way. (Please refer to Figure 5.3.)  
5.2.2. Slave transmits data to master (read cycle)  
„
„
„
„
The sub-address was assigned by previous write cycle  
The sub-address is automatically increased after each byte read  
Am : Acknowledged by master  
Note there is no acknowledgment from master after last byte read  
1ST BYTE  
2ND BYTE  
n BYTE  
Am  
SLAVE ADDRESS  
(7 BITS)  
S
RW  
A
DATA (8 BIT)  
Am DATA  
DATA  
1
P
NO ACK IN LAST  
BYTE  
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PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
During read cycle, the master generates start condition and then place the 1st byte data that combine slave  
address (7 bits) with a read/write control bit to SDA line. After slave issue acknowledgment, 8 bits DATA  
was placed on SDA line by PAC407. The 8 bit data was read from PAC407 internal control register that  
address was assigned by previous write cycle. Following the master acknowledgment, the PAC407 place  
the next 8 bits data (address is increased automatically) on SDA line and then transfer to master serially.  
The DATA and Am cycles are repeated until the last byte read. After last byte read, Am is no longer  
generated by master but instead of keeping SDA line as high. The slave (PAC407) must releases SDA line  
back to master to generate STOP condition. (Please refer to Figure 5.3.)  
SDA  
SCL  
1-7  
8
9
1-7  
8
9
1-7  
8
9
P
S
ACK  
from  
Receiver  
ACK  
from  
Receiver  
Stop  
Condition  
ACK  
from  
Receiver  
Address  
R/W  
Data  
Data  
Start  
Condition  
Figure 5.3 Data Transfer Format  
5.3. I2CTM Bus Timing  
SDA  
t
BUF  
t
HD;STA  
tr  
t
f
t
t
SP  
t
f
t
r
tSU;DAT  
t
LOW  
SCL  
SU;STO  
P
S
S
Sr  
t
HD;STA  
t
SU;STA  
t
HD;DAT  
t
HIGH  
Figure 5.4 I2CTM Bus Timing  
5.4. I2CTM Bus Timing Specification  
STANDARD-MODE  
UNIT  
PARAMETER  
SYMBOL  
MIN.  
MAX.  
SCL clock frequency  
10  
400  
-
kHz  
µs  
fscl  
Hold time (repeated) START condition.  
After this period, the first clock pulse is generated.  
Low period of the SCL clock  
4.0  
tHD:STA  
4.7  
0.75  
4.7  
0
-
µs  
µs  
µs  
µs  
ns  
ns  
ns  
µs  
µs  
tLOW  
tHIGH  
tSU;STA  
tHD;DAT  
tSU;DAT  
tr  
HIGH period of the SCL clock  
-
Set-up time for a repeated START condition  
Data hold time. For I2CTM bus device  
Data set-up time  
-
3.45  
-
250  
30  
Rise time of both SDA and SCL signals  
Fall time of both SDA and SCL signals  
Set-up time for STOP condition  
N.D. (note)  
30  
N.D. (note)  
tf  
4.0  
4.7  
-
-
tSU;STO  
tBUF  
Bus free time between a STOP and START  
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E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
Capacitive load for each bus line  
1
15  
-
pF  
V
Cb  
Noise margin at LOW level for each connected  
device (including hysteresis)  
0.1 VDD  
VnL  
Noise margin at HIGH level for each connected  
device (including hysteresis)  
0.2 VDD  
-
V
VnH  
Note: It depends on the "high" period time of SCL.  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
14  
E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
6. Electrical Characteristics  
„ Absolute Maximum Ratings  
Ambient Storage Temperature  
-40℃ ~ +125℃  
VCC  
3V  
VDDA  
3V  
Supply Voltages ( with respect to Ground )  
VDDMA  
VDDMD  
4V  
4V  
All Input / Output Voltages (with respect to Ground)  
Lead Temperature, Surface-mount process  
ESD Rating, Human Body model  
-0.3V to VDDMD + 1V  
+230℃  
2000V  
„ DC Electrical Characteristics (Ta =0℃ ~ 70℃ )  
Symbol  
Type: PWR  
VDDA  
Parameter  
Min.  
Typ.  
Max.  
Unit  
DC Supply voltage – Analog Power  
DC Supply voltage – Digital Power  
2.4  
2.4  
2.8  
2.5  
2.5  
-
2.6  
2.6  
3.3  
V
V
V
VCC  
VDDMA/MD DC Supply voltage – Main Analog/Digital  
Operating  
Current  
IDD  
15 fps  
-
-
24.4  
35  
-
-
mA  
µA  
VDDMA/MD = 3.3V  
Power Down  
Current  
IPWDN  
VDDMA/MD = 3.3V 15 fps  
Type: IN & I/O Reset and SYSCLK  
0.7 x  
VDDMD  
VIH  
Input voltage HIGH  
V
0.3 x  
VDDMD  
VIL  
CIN  
Input voltage LOW  
Input capacitor  
V
10  
pF  
Type: OUT & I/O for PXD0:7, PXCK, H/VSYNC & SDA, load 10pf, 1.2kΩ,2.5volts  
0.9 x  
VDDMD  
VOH  
VOL  
Output voltage HIGH  
Output voltage LOW  
V
V
0.1 x  
VDDMD  
„ AC Operating Condition  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
26  
Unit  
MHz  
MHz  
SYSCLK Master clock frequency  
PXCK  
Pixel clock output frequency (when YUV out)  
26  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
15  
E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
„ Sensor Characteristics  
Typ.  
Parameter  
Unit  
Note  
BCA  
BCW  
Sensitivity  
1.4  
1.2  
V/Lux-Sec  
Signal to Noise Ratio  
Dynamic Range  
> 45  
dB  
dB  
60  
Operation  
Stable Image  
-10 ~ 70  
Temperature  
Range  
℃
0 ~ 50  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
16  
E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
7. Reference Circuit Schematic  
7.1. PAC407BCW  
E F V R  
P X 0  
P X 1  
P X 2  
P X 3  
P X 4  
P X 5  
E F V R  
4
5
6
7
8
9
2 0  
1 9  
1 8  
1 7  
1 6  
1 5  
P X 2  
P X 3  
P X 4  
P X 5  
P X 6  
P X 7  
C V C  
C Y N V S  
C N Y H S  
L K P X C  
M D V D  
C Y N V S  
C N Y H S  
K L C P X  
M D V D  
Version 1.7, 13 Sep 2004  
E-mail: fae_service@pixart.com.tw  
PixArt Imaging Inc.  
17  
PAC407BCA/PAC407BCW  
7.2. PAC407BCA  
CMOS Image Sensor IC  
C
D
Y N V S  
D V D M  
B V R  
C
Y N V S  
5
6
7
8
9
2 8  
2 7  
2 6  
2 5  
2 4  
2 3  
2 2  
2 1  
S A V S  
M V C  
D M D V D  
K L C P X  
S A V S  
K L C P X  
T # E S R E  
L K S C S Y  
A
L
0
1
2
S D  
S C  
P X  
P X  
P X  
# T E S R E  
L K S C S Y  
A
L
0
1
2
S D  
S C  
P X  
P X  
P X  
7
P X  
S D V S  
P X  
9
P X 1 0  
S D V S 1 1  
P X 1 2  
5
7
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
18  
E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
8. Package Specification  
8.1. PAC407BCW  
Dimensions  
Package Body Dimension X  
Package Body Dimension Y  
Package Height  
Symbol  
A
Nominal  
4340  
4755  
800  
160  
640  
415  
300  
22  
5
5
800  
800  
570  
777.5  
2254.16  
1832.84  
Min.  
4315  
4730  
740  
130  
605  
395  
270  
-
-
-
-
-
Max.  
4365  
4780  
860  
190  
675  
435  
330  
-
-
-
-
-
Unit  
µm  
µm  
µm  
µm  
µm  
µm  
µm  
Ball  
µm  
µm  
µm  
µm  
µm  
µm  
µm  
µm  
B
C
C1  
C2  
C3  
D
Ball Height  
Package Body Thickness  
Thickness of Glass surface to wafer  
Ball Diameter  
Total Pin Count  
Pin Count X axis  
Pin Count Y axis  
Pin Pitch X axis  
Pin Pitch Y axis  
Edge to Pin Center Distance along X  
Edge to Pin Center Distance along Y  
Edge to Optical Center Distance along X  
Edge to Optical Center Distance along Y  
N
N1  
N1  
J1  
J2  
S1  
S2  
E
540  
747.5  
2229.16  
1807.84  
600  
807.5  
2279.16  
1857.84  
F
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
19  
E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
8.2. PAC407BCA  
CMOS Image Sensor IC  
Unit:mm  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
20  
E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
9. Recommended Lens and Holder  
9.1. Genius Lens（2P1G）  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
21  
E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
22  
E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
9.2. Asia-optical Lens（2P）  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
23  
E-mail: fae_service@pixart.com.tw  
PAC407BCA/PAC407BCW  
CMOS Image Sensor IC  
9.3. MaxEmil Lens（3P）  
Version 1.7, 13 Sep 2004  
PixArt Imaging Inc.  
24  
E-mail: fae_service@pixart.com.tw  

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