PAS005B [PIXART]
SXGA Color/Mono Digital CMOS Image Sensor; SXGA彩色/黑白数码CMOS图像传感器
| 型号： | PAS005B |
| 厂家： | 
PIXART IMAGING INC. |
| 描述： | SXGA Color/Mono Digital CMOS Image Sensor |
| 文件： | 总41页 (文件大小：1907K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PAS005B
PAS005B SXGA Color/Mono Digital CMOS Image Sensor
General Description
The PAS005B is a highly integrated CMOS active-pixel image sensor that has a SXGA resolution of 1280(H) x
1024(V). To have an excellent image quality, the PAS005B outputs 10-bit RGB raw data through a parallel data
bus. It is available in color or monochrome in 48-pin LCC.
The PAS005B can be programmed to set the exposure time for different luminance conditions via I2CTM serial
control bus. By programming the internal register sets, it performs on-chip frame rate adjustment, offset correction
DAC, programmable gain control, 10-bits ADC, 8-bits output companding, interpolated sub-sampling and defect
compensation.
Features
Key Specification
Supply voltage
Array formate
Optical format
Pixel size
SXGA(1280x1024 pixels) resolution, 1/2” Lens
Bayer-RGB color filter array
On-chip 10-bit pipelined A/D converter
User selectable digital output formats:
3.3V + 10%
1280(H) x 1024(V)
1/2 ”
10-bit parallel RGB raw data
Formatted data output
On-chip 9-bit background compensation DAC
On-chip programmable gain amplifier
5.4µmX5.4µm
~10 fps @ full video
Up to 48 MHz
16 MHz
Frame rate
4-bit color gain amplifier (x3 )
5-bit global gain amplifier (x4 )
System clock
Max. pixel rate
FPN
Continuous variable frame time(1/2sec~1/30sec)
Continuous variable exposure time
I2CTM Interface
7.05 level
External synchronization support
Single 3.3V supply voltage
Sensitivity
553 level/Lux*sec
26dB(Max.)
150 mW low power dissipation(<100mW@VGA,
30fps)
PGA gain
200 uW low power down dissipation
Support flash light timing
Mirror readout (vertical & horizontal)
Windowing
Color filter
RGB Bayer Pattern
~ Frame time to 1 pixel CLK
Exposure time
Scan mode
S/N Ratio
Power
Progressive
45dB
Interpolated Sub-sampling: 1/2, 1/4, 1/8
< 150 mW @ 10fps
48-pin LCC
Package
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
10/1/03 V1.0,
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
1. Pin Assignment
Pin#
1
Name
CSB
Type
I
Description
Chip Select Bar
2
VDDD
P
Digital Power
3
VSSD
P
Digital Ground
4
5
VSS_ESD
VDDA
P
P
ESD Ground
Analog Power
6
7
8
9
X_VDDD
VLRST
I_PXON
I_PXOP
I_PXIN
I_PXIP
I/O
I/O
I/O
I/O
I/O
I/O
P
P
O
O
O
Internal digital power
VLRST
Analog test output N
Analog test output P
Analog test input N
Analog test input P
Regulator Ground
Regulator Power
Voltage Reference Bottom
Voltage Reference Top
Voltage Common Mode
Regulator Ground
Voltage Common Mode
External R N_node
External R P_node
10
11
12
13
14
15
16
17
18
19
20
VSSX
VDDX
X_VRB
X_VRT
X_VCM
VSSX
X_VCM
EXTRESN
EXTRESP
P
O
I
I
21
X_VREF
O
Voltage Reference testpoint
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VSSA
VDDA
NC
X_VDDAY
VSSAY
VSSD
VDDD
SCL
SDA
PX0
PX1
PX2
PX3
PX4
VDDQ
VSSQ
PX5
PX6
PX7
PX8
PX9
P
P
-
I/O
P
P
Analog Ground
Analog Power
Not connected
Array Power
Array Ground
Digital Ground
Digital Power
I2C Serial Clock
I2C Serial Data
Dataout bit 0
Dataout bit 1
Dataout bit 2
Dataout bit 3
Dataout bit 4
I/O Driver Power
I/O Driver Ground
Dataout bit 5
Dataout bit 6
Dataout bit 7
Dataout bit 8
Dataout bit 9
System Clock
Horizontal Sync
P
I
I/O
O
O
O
O
O
P
P
O
O
O
O
O
I
SYSCLK
HSYNC
O
45
PXCLK
O
Pixel Clock
46
47
48
SYNC
NC
VSYNC
I
-
O
External Sync
Not connected
Vertical Sync
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
2. Block Diagram
Averaged
Sub-sampling
function
Color DAC
R:G1:G2:B 8b: magnitude
1b: sign
9b D/A
Image Array
1308x1040
Color Gain
R:G1:G2:B
Global Gain
Front Gain
Frame
ABC-A
CDS
FG
CG
GG
10b A/D
Column decoder
x2~x3.5
(2b)
X1~x2.875
(4b)
X1~x4.1
(5b)
Timing generator
& control logic
Companding
Defect
Compensation
Line
ABC-D
Frame
ABC-D
ABC : Auto-Background Compensation.
Frame ABC-A : Frame based ABC-Analog domain.
Frame ABC-D : Frame based ABC-Digital domain.
Line ABC-D : Line based ABC-Digital domain.
Figure 2.1. Shows the PAS005 sensor block diagram
The PAS005 is a 1/2 –inch CMOS imaging sensor with 1308x1040 physical pixels. The active region of
sensor array is 1288x1028 as shown in Fig. 2.1. The sensor array is cover with Bayer pattern color filters and
U-lens. The first pixel location <0,0> is programmable in 2 direction (X and Y) and the default value is at the
left-down side of sensor array.
After a programmable exposure time, the image is sampled first with CDS (Correlated Double Sampling)
block to improve S/N ration and reduce fixed pattern noise. The optional XY-averaged function is
implemented to improve the sub-samapling image quality. It can reduce the sawtooth edge in VGA and CIF
format output.
Three analog gain stages are implemented before signal transferred by the 10b ADC. The front gain stage (FG)
can be programmed to fit the saturation level of sensor to the full-range input of ADC. The programmable
color gain stage (CG) is used to balance the luminance response difference between B/G/R. The global gain
stage (GG) is programmed to adapt the gain to the image luminance.
The fine gained signal will be digitized by the on-chip 10b ADC. After the image data has been digitized,
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
further alteration to the signal can be applied before the data is output:
2.2 Automatic Background Compensation (ABC)
The ABC function is implemented by 3 steps : ABC-A, Frame-based ABC-D, and Line-based ABC-D. The
ABC-A is implemented in analog domain with an on-chip 9b DAC. The Frame-based ABC-D is implemented
in digital domain to automatically compensate the leakage current with 2 dark reference lines on top of sensor
array. The Line-based ABC-D is implemented in digital domain to automatically compensate the leakage with
4 dark reference columns surround the sensor array. These three blocks can be enable/disable separately by
user.
2.3 Defect Compensation
The Defect Compensation block can detect the possible defect pixel and replace it with average output of like-
colored pixels on either side of defective pixel. There is no limitation in the capability of defect number. This
function is also enable/disable by user.
2.4 Companding
The companding function is used to simulate the gamma curve and do non-linear transformation before the
data is output. There are 8 curves selected by setting register comp_crv[2:0] as shown in Fig. 2.4. The default
value [00] is a linear curve.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
Figure 2.4 Companding curves program by comp_crv[2:0]
O/P(10b)
1111111111
5
4
3
7
6
withoutcompanding
2
1
0
000xxxxxxx 001xxxxxxx
010
011
10xxxxxxxx
11xxxxxxxx I/P(10b)
3. Register and Function
3.1. Register list
Default
(Decimal)
R/W
Register
Register
Description
I2C sampling frequency = frequency of I_sysclk /
Np_i2c
Reg_2[3:0]
Np_i2c[3:0]
R/W
1
Programming range of Np_i2c: 1~15
Pixel rate = frequency of I_sysclk / Np
Programming range of Np: 1~63
Analog signal processing single or double path
0: double path, 1: single path
Color mode or Mono mode(used only in sub-
sampling mode)
Reg_3[5:0]
Reg_4[7]
Np[5:0]
R/W
R/W
2
0
single_path
Reg_4[6]
cm
R/W
1
0: Mono mode, 1: color mode
reverse read column
0: forward readout, 1: reverse readout
reverse read row
Reg_4[5]
Reg_4[4]
rrc
rrr
R/W
R/W
0
0
0: forward readout, 1: reverse readout
column frequency
00: Normal readout without sub-sampling,
01: 1/2 sub-sampling
10: 1/4 sub-sampling,
11: 1/8 sub-sampling
row frequency
Reg_4[3:2]
Reg_4[1:0]
cf[1:0]
rf[1:0]
R/W
R/W
0
0
00: Normal readout without sub-sampling,
01: 1/2 sub-sampling
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
10: 1/4 sub-sampling,
11: 1/8 sub-sampling
Reg_5[2:0]
Reg_6[7:0]
Reg_7[2:0]
Reg_8[7:0]
Reg_9[2:0]
Reg_10[7:0]
Reg_11[2:0]
Reg_12[7:0]
wcp_in[10:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1287
1287
0
0
1027
1027
window column pointer
window column pointer
window column width
window column width
window row pointer
window row pointer
window row depth
window row depth
wcp_in[7:0]
wcw_in[10:8]
wcw_in[7:0]
wrp[10:8]
wrp[7:0]
wrd
wrd
CDS timing extension to 2 times of normal CDS
timing for 48M pixel rate
row average for row sub-sampling
direction of average
Reg_13[5]
Reg_13[4]
CDS_ext2_in
row_ave
R/W
R/W
0
0
Reg_13[3]
Reg_13[2]
dir_ave
R/W
R/W
0
0
0: the same direction of rrc
1: reverse direction of rrc
used for mono color filter
0: row<i> & row<i+2> average
1: row<i> & row<i+1> average
mono_ave
Reg_13[1]
Reg_13[0]
Reg_14[2:0]
Reg_15[7:0]
Seq_exp
Snap_ena
cov[10:8]
cov[7:0]
R/W
R/W
R/W
R/W
1
0
0
0
column overhead: used to increase line time
column overhead: used to increase line time
It is used to reset the full sensor array and exposure
address when critical operation mode is
changed(useful only that register “flag” is set to 1
and reset of the full sensor array and exposure
address will start till the first new frame is readout
after register “flag” is set to 1) .
Reg_16[0]
mode_chg_reg
R/W
0
It will be reset by the same mechanism that flag
register be reset.
Reg_17[5:0]
Reg_18[7:0]
Reg_19[5:0]
Reg_20[7:0]
Reg_21[2:0]
Reg_22[7:0]
Reg_23[6:5]
Reg_23[4:0]
Reg_24[3]
LPF[13:8]
LPF[7:0]
ny[13:8]
ny[7:0]
Ne[10:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1027
1027
Line per frame: total frame time = (LPF+1)+2 lines
Line per frame: total frame time = (LPF+1)+2 lines
Exposure time start point offset in line resolution
Exposure time start point offset in line resolution
Exposure time start point offset in pixel resolution
Exposure time start point offset in pixel resolution
Front gain
Global gain
The Dac sign of color B
The Dac sign of color G1
The Dac sign of color G0
0
0
0
0
0
0
1
1
1
1
ne[7:0]
Frnt_gain[1:0]
Global_gain[4:0]
Dac_B_sign
Dac_G1_sign
Dac_G0_sign
Dac_R_sign
Reg_24[2]
Reg_24[1]
Reg_24[0]
The Dac sign of color R
The Dac value of color B
(Dac setting is done by signed-magnitude)
Reg_25[7:0]
Dac_B[7:0]
R/W
0
Reg_26[7:0]
Reg_27[7:0]
Reg_28[7:0]
Reg_29[3:0]
Dac_G1[7:0]
Dac_G0[7:0]
Dac_R[7:0]
Cg_B[3:0]
R/W
R/W
R/W
R/W
0
0
0
0
The Dac value of color G1
The Dac value of color G0
The Dac value of color R
Color gain of color B
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PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
Reg_30[3:0]
Reg_31[3:0]
Reg_32[3:0]
Cg_G1[3:0]
Cg_G0[3:0]
Cg_R[3:0]
R/W
R/W
R/W
0
0
0
Color gain of color G1
Color gain of color G0
Color gain of color R
2’s complement value for digital calibration of color
B
2’s complement value for digital calibration of color
G1
2’s complement value for digital calibration of color
G1
2’s complement value for digital calibration of color
G1
2’s complement value for digital calibration of color
G0
2’s complement value for digital calibration of color
G0
2’s complement value for digital calibration of color
R
2’s complement value for digital calibration of color
R
Reg_33[2:0]
Reg_34[7:0]
Reg_35[2:0]
Reg_36[7:0]
Reg_37[2:0]
Reg_38[7:0]
Reg_39[2:0]
Reg_40[7:0]
acc1_B[10:8]
acc1_B[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
acc1_G1[10:8]
acc1_G1[7:0]
acc1_G0[10:8]
acc1_G0[7:0]
acc1_R[10:8]
acc1_R[7:0]
used to synchronize register update by frame when
fast_i2c is set 0
It will be reset to 0 till the first new frame is readout
after it is set to 1
Reg_41[0]
flag
R/W
0
when it is set to 1, the mode related registers will be
updated only after mode_chg is set to 1
DAC & PGA update delay 1 frame automatically
fast update of synchronized i2c registers
source follower reset enable
Reg_42[2]
mode_chg_ena
R/W
1
Reg_42[1]
Reg_42[0]
Reg_43[7]
dac_pg_lag
fast_i2c
sfrst_ena
R/W
R/W
R/W
0
0
0
SHR extension CDS_rst1:
Reg_43[6:5]
shr_ext[1:0]
R/W
1
00: 9 ck12 01: 14 ck12
10: 19 ck12 11: 24 ck12
Reg_43[4:2]
Reg_43[1]
Reg_43[0]
comp_crv[2:0]
Vsync_p
R/W
R/W
R/W
0
0
0
companding curve
Vsync polarity
Hsync polarity
Hsync_p
DAC output range
Reg_44[7:6]
dacor[1:0]
R/W
0
00: x1/8 01: x1/4
10: x1/2 11: x1
Reg_44[5:0]
offset[5:0]
R/W
1
offset value for ABC
Reg_45[7:0] Threshold_1_by4[7:0] R/W
Reg_46[7:0] Threshold_2_by4[7:0] R/W
25
13
Threshold_1 divided by 4 for defect compensation
Threshold_2 divided by 4 for defect compensation
0: Defect compensation disable
1: Defect compensation enable
ABC enable high
Line based digital calibration enable high
Frame based digital calibration enable high
Number of pixels for Frame based digital calibration
00: 4 pixels 01: 8 pixels
Reg_47[5]
Defect_EnH
R/W
0
Reg_47[4]
Reg_47[3]
Reg_47[2]
ABC_EnH
Line_Avg_EnH
Frm_Avg_EnH
R/W
R/W
R/W
0
0
0
Reg_47[1:0] Avg_num_index[1:0] R/W
Reg_48[6] DSC_pd
R/W
1
0
10: 16 pixels 11: 32 pixels
Digital timing(column address, CDS timing) disable
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PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
in redundancy rows
Reg_48[5]
Reg_48[4]
CDS_pd
ASP_pd
R/W
R/W
0
0
Analog CDS disable in redundancy rows
Analog signal path disable in redundancy rows
Combination of (single_path, path_chg):
00: even pixels processed by even signal path, odd
pixels processed by odd signal path
01: even pixels processed by odd signal path, odd
pixels processed by even signal path
10: all pixels are processed by the even signal path
11: all pixels are processed by the odd signal path
Useful only when mono mode and double path
readout, even pixels and odd pixels are all processed,
but just only either even or odd pixels are readout
0: for readout even path
Reg_48[3]
path_chg
R/W
0
Reg_48[2]
even_path
R/W
0
1: for readout odd path
Reg_48[1]
Reg_48[0]
Reg_49[5]
Reg_49[4]
Reg_49[3]
Reg_49[2]
Reg_49[1]
Reg_49[0]
Reg_50[5]
Reg_50[4]
Reg_50[3]
Reg_50[2]
Reg_50[1]
Reg_50[0]
Reg_51[7]
Reg_51[6]
Reg_51[5]
Reg_51[4]
Reg_51[3]
Reg_51[2]
Reg_51[1]
Reg_51[0]
Reg_52[5:4]
Reg_52[3:2]
Reg_52[1:0]
Reg_53[6]
Reg_53[5:4]
Reg_53[3:2]
csbE
csbO
Test_EnH
dqio_EnL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1 for closing the even analog signal path
1 for closing the odd analog signal path
Test enable high
dqio enable low
scan_Dac
scan DAC(useful only when Test_EnH=1)
scan Color Gain(useful only when Test_EnH=1)
scan Global Gain(useful only when Test_EnH=1)
pga test enable high
Source follower dynamic switch enable high
Analog signal path offset enable low
Zeroing switch delay plus enable high
Zeroing switch in CDS enable high
VGA resolution averaged out enable high
CIF resolution averaged out enable high
CDS block fast enable high
DAC block fast enable high
PGA block fast enable high
ADC block fast enable high
CDS block enable low
DAC block enable low
PGA block enable low
ADC block enable low
CDS bias current option
VLRST voltage level option
VDDAY voltage level option
Regulator block enable low
Regulator current level option
Reference voltage (VRT-VRB) range option
Internal regulated digital power X_VDDD voltage
level option
0: CDS clock = even path clock
1: CDS clock = odd path clock
scan_Color
scan_Global
pga_test_EnH
sfswt_EnH
offset_EnL
zdly_plus
cds_zero_EnH
vga_ave_EnH
cif_ave_EnH
cds_fast_EnH
dac_fast_EnH
pga_fast_EnH
adc_fast_EnH
cds_EnL
dac_EnL
pga_EnL
adc_EnL
cdsbias[1:0]
vlrst[1:0]
vdday[1:0]
reg_EnL
regfast[1:0]
vrefLG[1:0]
Reg_53[1:0]
Reg_54[7]
Reg_54[6]
vddd[1:0]
T_gp1
R/W
R/W
R/W
0
0
0
0: X_VDDD switch ON diode connect from VDDD
1: X_VDDD switch OFF diode connect from VDDD
External VDDAY enable high
T_gp2
Reg_54[5]
Reg_54[4]
extvdy_EnH
vayNdrv_EnH
R/W
R/W
0
0
VDDAY with NMOS drive enable high
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
Bias current generated by external resistor enable
high
Reg_54[3]
extR_EnH
R/W
0
Reg_54[2]
Reg_54[1]
Reg_54[0]
bgp_EnH
ext2p5v_EnH
2p5vNdrv_EnH
R/W
R/W
R/W
0
0
0
Bandgap reference enable high
External 2.5V digital power enable high
X_VDDD with NMOS drive enable high
software power down:
Reg_55[0]
sfpd
R/W
0
Sensor core will be powered down if it is set to 1 but
I2C interface will be live.
software reset:
It is used to reset the full registers to default value.
The converge sign of color B when ABC is enable
Reg_56[0]
Reg_57[3]
Reg_57[2]
Reg_57[1]
soft_rst
R/W
R
0
0
0
0
Dac_B_sign_
ABC
Dac_G1_sign_
ABC
Dac_G0_sign_
ABC
Dac_R_sign_
ABC
The converge sign of color G1 when ABC is enable
The converge sign of color G0 when ABC is enable
The converge sign of color R when ABC is enable
R
R
Reg_57[0]
R
R
R
0
0
0
Reg_58[7:0]
Dac_B_ABC[7:0]
The converge value of color B when ABC is enabled
The converge value of color G1 when ABC is
enabled
The converge value of color G0 when ABC is
enabled
The converge value of color R when ABC is enabled
The converge value of color B when frame based
digital calibration is enabled.
The converge value of color B when frame based
digital calibration is enabled.
The converge value of color G1 when frame based
digital calibration is enabled.
The converge value of color G1 when frame based
digital calibration is enabled.
The converge value of color G0 when frame based
digital calibration is enabled.
The converge value of color G0 when frame based
digital calibration is enabled.
Reg_59[7:0] Dac_G1_ABC[7:0]
Reg_60[7:0] Dac_G0_ABC[7:0]
R
R
R
0
0
0
Reg_61[7:0]
Dac_R_ABC[7:0]
Reg_62[4:0] acc1_B_FrmAvg[12:8]
Reg_63[7:0] acc1_B_FrmAvg[7:0]
R
R
R
R
R
R
R
0
0
0
0
0
0
0
acc1_G1_FrmAvg[12:8
Reg_64[4:0]
]
Reg_65[7:0] acc1_G1_FrmAvg[7:0]
acc1_G0_FrmAvg[12:8
Reg_66[4:0]
]
Reg_67[7:0] acc1_G0_FrmAvg[7:0]
Reg_68[4:0] acc1_R_FrmAvg[12:8]
Reg_69[7:0] acc1_R_FrmAvg[7:0]
The converge value of color R when frame based
digital calibration is enabled.
The converge value of color R when frame based
digital calibration is enabled.
Part_ID[11:4]
R
0
Part_ID[3:0]
rrc
VerID
R
1
2
3
Np_i2c[3:0]
R/W
R/W
R/W
Np[5:0]
cf[1:0]
single_
path
cm
rrr
rf[1:0]
wcp_in[10:8]
4
5
R/W
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PAS005B
CMOS Image Sensor IC
wcp_in[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
7
wcw_in[10:8]
wrp[10:8]
wcw_in[7:0]
wrp[7:0]
8
9
10
11
12
wrd[10:8]
wrd[7:0]
CDS_
ext2_in
row_
ave
dir_
ave
mono_
ave
seq_
exp
snap_
ena
13
cov[10:8]
R/W
R/W
R/W
14
15
cov[7:0]
mode_
chg_
reg
16
LPF[13:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
17
18
19
20
21
22
23
LPF[7:0]
ny[7:0]
ne[7:0]
ny[13:8]
ne[10:8]
Frnt_gain[1:0]
Global_gain[4:0]
Dac_B_ Dac_G1_ Dac_G0_ Dac_R_ R/W
sign sign sign sign
Dac_B[7:0]
24
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
25
26
27
28
29
30
31
32
33
34
35
36
Dac_G1[7:0]
Dac_G0[7:0]
Dac_R[7:0]
Cg_B[3:0]
Cg_G1[3:0]
Cg_G0[3:0]
Cg_R[3:0]
acc1_B[10:8]
acc1_B[7:0]
acc1_G1[10:8]
acc1_G1[7:0]
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PAS005B
CMOS Image Sensor IC
acc1_G0[10:8]
acc1_R[10:8]
R/W
R/W
R/W
R/W
R/W
R/W
37
38
39
40
41
acc1_G0[7:0]
acc1_R[7:0]
flag
mode_ dac_pg_ fast_
chg_ena lag i2c
comp_crv[2:0] Vsync Hsync
_p _p
42
sfrst_
ena
shr_ext[1:0]
R/W
43
dacor[1:0]
offset[5:0]
R/W
R/W
R/W
R/W
44
45
46
Threshold_1_by4
Threshold_2_by4
ABC_ Line_
Frm_
Avg_
EnH
Avg_num
_index[1:0]
Defect_
EnH
47
48
49
EnH
Avg_
EnH
CDS_
pd
ASP_ path_ even_
R/W
R/W
DS_
pd
csbE
scan_
csbO
pd
chg
path
Test_
EnH
dqio_
EnL
scan_
Dac
scan_
Color Global
pga_
test_
EnH
cif_
ave_
EnH
offset
_EnL
cds_
zero_
EnH
vga_
ave_
EnH
sfswt_
EnH
zdly_
plus
50
51
R/W
R/W
cds_
fast_
EnH
dac_
fast_
EnH
pga_
fast_
EnH
adc_
fast_
EnH
cds_
EnL
dac_
EnL
pga_
EnL
adc_
EnL
52
53
cdsbias[1:0]
vlrst[1:0]
vrefLG[1:0]
vdday[1:0]
vddd[1:0]
2p5v
R/W
R/W
reg_
EnL
regfast[1:0]
extvdy_ vayNdrv extR_
EnH _EnH EnH
bgp_ ext2p5v
EnH
54
Ndrv_
EnH
sfpd
R/W
_EnH
R/W
R/W
55
56
soft_
rst
Dac_B_ Dac_G1_ Dac_G0_ Dac_R_
R
57
sign_
ABC
sign_
ABC
sign_
ABC
sign_
ABC
Dac_B_ABC[7:0]
Dac_G1_ABC[7:0]
Dac_G0_ABC[7:0]
Dac_R_ABC[7:0]
R
R
R
R
R
58
59
60
61
62
acc1_B_FrmAvg[12:8]
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PAS005B
CMOS Image Sensor IC
acc1_B_FrmAvg[7:0]
R
R
R
R
R
R
R
63
64
65
66
67
68
69
acc1_G1_FrmAvg[12:8]
acc1_G1_FrmAvg[7:0]
acc1_G0_FrmAvg[12:8]
acc1_G0_FrmAvg[7:0]
acc1_R_FrmAvg[12:8]
acc1_R_FrmAvg[7:0]
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CMOS Image Sensor IC
4. Function description
4.1 Pixel array
6 dummy lines
G R G R G R
1288 Active lines
6 dummy lines
dummy
dummy
dark
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
G
B
R
G
G
B
R
G R
G
R
G
G
B
R
G
G
B
R
G
G
B
R
G
G R
G
B
G
B
G
B
G
B
G
B
B G
2047
2046
G R
dark
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
G R G R G R
G R
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
G R
B
G
B
G
B
G
B
G
B G
G R G R G R
G R
G R
B
G
B
G
B
G
B
G
B G
G R G R G R
G R
G R
B
G
B
G
B
G
B
G
B G
1028
1027
G R G R G R
G R
G R
B
G
B
G
B
G
B
G
B G
1288x1028
Active region
1
0
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G R G R G R
G R
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G R
B
G
B
G
B
G
B
G
B G
dummy
G R
dummy
B G
G R G R G R
G R
B
G
B
G
B
G
B
G
Column Address
4.1.1 Output Timing
1.3M(1280 X 1024)-pixel readout: (with 8 column and 4 row for color interpolation)
cf[1:0] = 0, rf[1:0]=0, cm =1, single_path = 0, row_ave= 0, CDS_ext2_in =1.
wcp[10:0]=0, wcw_in[10:0]=1287,wrp[10:0]=0,wrd[10:0]=1027,
linetime= 480+4(x)+4(D)+1288+4(x)= 1780pixclks
Hsync.
480pixclks
x x x
x x x x
1288pixels0ut x x x x
x x x x
D D D D
1288pixelsout
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"dark.
Pixclk_a
Fig 4.1.1-1 Inter-line timing (default)
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PAS005B
CMOS Image Sensor IC
linetime= cov[10:0]+480+4(x)+4(D)+1288+4(x) pixclks
Hsync.
cov[10:0]+480
x x x
x x x x
1288pixels0ut x x x x
x x x x
1288pixelsout
D D D D
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"indicatesdark.
Pixclk_a
Fig 4.1.1-2 Inter-line timing (programmable)
Frametime(min)(=1030lines)
Vsync.
Hsync.
480
Pixclks
480
Pixclks
Dark
Dark
Dark
Dark
B,G,B,G...
G,R,G,R...
B,G,B,G...
Validframedata(1028lines)
Fig 4.1.1-3 Inter-frame timing (default)
Frametime=lpf[14:0]+3lines
Vsync.
Hsync.
Pixclks
1
Dark
1
Dark
0
Dark
0
Dark
Validframedata
(1028lines)
Validframedata
(1028lines)
Fig 4.1.1-4 Inter-frame timing (programmable)
4.2 Windowing
Users are allowed to define window size as well as window location in PAS005B. Window size can range from
1x8 to 1288x1028 . The location of window can be anywhere in the pixel array. Window size and window
location is defined by register wcp_in, wcw_in, wrp and wrd: the wcp_in defines the starting column while wrp
defines the starting row of the window;. the wcw_in define the column width of the window and wrd define the
row depth of the window.
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PAS005B
CMOS Image Sensor IC
2046
2047
0
1
(wcp,wrp)
wrd
wcw
1026
1027
Fig. 4.2-1
4.2.1 Output timing of windowing
Hardware windowing VGA(640 X 480) pixels readout:
(with 4 column and 2 row for color interpolation)
cf[1:0] = 0, rf[1:0]=0, cm =1, single_path = 0, row_ave= 0, CDS_ext2_in =1.
wcp[10:0]=0, wcw_in[10:0]=643,
wrp[10:0]=0,wrd[10:0]=481,
linetime= 480+4(x)+4(D)+644+4(x)= 1136pixclks
Hsync.
480pixclks
x x x
x x x x
644pixels0ut x x x x
x x x x
D D D D
644pixelsout
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"dark.
Pixclk_a
Fig 4.2.1-1 Inter-line timing (default)
linetime= cov[10:0]+480+4(x)+4(D)+644+4(x) pixclks
Hsync.
cov[10:0]+480
x x x
x x x x
644pixels0ut x x x x
x x x x
D D D D
644pixelsout
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"indicatesdark.
Pixclk_a
Fig 4.2.1-2 Inter-line timing (programmable)
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CMOS Image Sensor IC
Frametime(min)(=484lines)
Vsync.
480
Pixclks
480
Pixclks
Dark
Dark
Dark
Dark
Hsync.
B,G,B,G...
G,R,G,R...
B,G,B,G...
Validframedata(482lines)
Fig 4.2.1-3 Inter-frame timing (default)
Frametime=lpf[14:0]+3lines
Vsync.
Pixclks
1
Dark
1
Dark
0
Dark
0
Dark
Hsync.
Validframedata
(482lines)
Validframedata
(482lines)
Fig 4.2.1-4 Inter-frame timing (programmable)
Hardware windowing CIF(352 X 288) pixels readout:(with 4 column and 2 row for color interpolation)
cf[1:0] = 0, rf[1:0]=0, cm = 1, single_path = 0, row_ave= 0, CDS_ext2_in = 1.
wcp[10:0]=0, wcw_in[10:0]=355,
wrp[10:0]=0,wrd[10:0]=289,
linetime= 480+4(x)+4(D)+356+4(x)= 848pixclks
Hsync.
480pixclks
x x x
x x x x
356pixels0ut x x x x
x x x x
D D D D
356pixelsout
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"dark.
Pixclk_a
Fig 4.2.1-5 Inter-line timing (default)
linetime= cov[10:0]+480+4(x)+4(D)+356+4(x) pixclks
Hsync.
cov[10:0]+480
x x x
x x x x
356pixels0ut x x x x
x x x x
D D D D
356pixelsout
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"indicatesdark.
Pixclk_a
Fig 4.2.1-6 Inter-line timing (programmable)
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PAS005B
CMOS Image Sensor IC
Frametime(min)(=292lines)
Vsync.
480
Pixclks
480
Pixclks
Dark
Dark
Dark
Dark
Hsync.
B,G,B,G...
G,R,G,R...
B,G,B,G...
Validframedata(290lines)
Fig 4.2.1-7. Inter-frame timing (default)
Frametime=lpf[14:0]+3lines
Vsync.
Pixclks
1
Dark
1
Dark
0
Dark
0
Dark
Hsync.
Validframedata
(290lines)
Validframedata
(290lines)
Fig 4.2.1-8 Inter-frame timing (programmable)
4.2.2 Y Programming
cov
(w cp,w rp)
W O I
w cw
wrd
LPF
Fram e tim e: (LPF+1) + 2 Line tim e
Fig 4.2.2-1
The Blue circle indicate the maximum 1288 X 1028 active pixels, Red circle the window of interest, and Pink
circle the Virtual Frame. Virtual Frame represents the frame time and the size of it indicates that the frame
time is the time to readout all the pixels in this Virtual Frame.
The readout row and column is programmed by WOI(wcp, wrp, wcw, wrd), Sub-sampling(cf, rf) and readout
direction(rrc, rrr). The readout rows and columns are shown in the following figures.
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PAS005B
CMOS Image Sensor IC
4.3 Sub-sampling
4.3.1 Sub-sampling—in color mode
PAS005B can be programmed to output in VGA and CIF size. In VGA sub-sampling mode, both vertical and
horizontal pixels are sub-sampled at 1/2, while in CIF sub-sampling mode, sub-sampled at 1/4. By programming
row frequency(rf), column frequency(cf) and color mode(cm), PAS005B performs sub-sampling. The maximum
sub-sampling rate is 1/8. As shown in Fig. 4.3, by setting cm=1, rf=01 and cf=01, PAS005B outputs in VGA sub-
sampling mode.
**In color mode PAS005B outputs in Bayer pattern while mono mode outputs mono data.
2046
2047
0
1
1026
1027
Fig 4.3.1
4.3.2 Sub-sampling—in mono mode
PAS005B can also be programmed to output in VGA and CIF size in mono mode. In VGA sub-sampling mode,
both vertical and horizontal pixels are sub-sampled at 1/2, while in CIF sub-sampling mode sub-sampled at 1/4.
By programming row frequency(rf), column frequency(cf) and color mode(cm), PAS005B performs sub-
sampling. The maximum sub-sampling rate is 1/8.
2046
2047
0
1026
Fig 4.3.2
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CMOS Image Sensor IC
**Windowing and sub-sampling can be used independently.
4.3.3 Sub-sampling with average--in color mode
PAS005B supports average data output in sub-sampling mode in color mode. In this mode, the PAS005B
averages the pixel data with surrounding pixels that are with the same color. For example, in VGA-sub-
sampling, in which both vertical and horizontal pixels are sub-sampled at 1/2, the sub-sampled pixel data are
[i,j]′= ( [i,j] + [i,j+2] + [i+2,j] + [i+2,j+2] ) / 4,
while in CIF-sub-sampling, the sub-sampled pixel date are
[i,j]′= ( [i,j] + [i,j+2] + [i,j+4] + [i,j+6] + [i+2,j] + [i+2,j+2] + [i+2,j+4] + [i+2,j+6]) / 8.
CFA :colormode
10 11 12 13 14 15
12 13
0
1
2
3
4
5
6
7
8
9
0
1
4
5
8
9
0
1
0
1
0
1
0
1
2
2
2
2
3
3
3
3
4
4
4
4
rf=0,cf=1
vga_ave_Ena=1
rf=0,cf=0
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
11
12
13
14
15
10
11
12
13
14
15
10
11
12
13
14
15
10
11
12
13
14
15
10 11 12 13 14 15
12 13
12 13
0
0
1
1
2
3
4
5
6
7
8
8
9
9
0
0
1
1
4
4
5
5
8
8
9
9
0
1
0
1
0
1
0
1
4
5
4
5
VGA
8
9
8
9
8
9
8
9
CIF
12
13
12
13
12 13
0
1
8
9
0
1
4
5
8
9
Fig 4.3.3
4.3.4 Sub-sampling with average—in mono mode
PAS005B supports average data output in sub-sampling mode in mono mode. In this mode, the PAS005B
averages the pixel data with surrounding pixels that are with the same color. For example, in VGA-sub-
sampling, in which both vertical and horizontal pixels are sub-sampled at 1/2, the sub-sampled pixel data are
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PAS005B
CMOS Image Sensor IC
[i,j]′= ( [i,j] + [i+1,j] ) / 2,
while in CIF-sub-sampling, the sub-sampled pixel date are
[i,j]′= ( [i,j] + [i,j+2] + [i+2,j] + [i+2,j+2] ) / 4,
M FA :M onoM ode
10 11 12 13 14 15
10
12
14
0
1
2
3
4
5
6
7
8
9
0
2
4
6
8
0
1
0
1
0
1
0
1
2
2
2
2
3
3
3
3
4
4
4
4
rf=0,cf=0
rf=0,cf=1
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
10
11
12
13
14
15
10
11
12
13
14
15
10
11
12
13
14
15
10
11
12
13
14
15
10 11 12 13 14 15
10
10
12
12
14
14
0
0
1
2
3
4
4
5
6
7
8
8
9
0
0
2
2
4
4
6
6
8
8
12
0
4
0
4
0
2
0
2
rf=2,cf=2
vga_ave_Ena=1
row_ave_Ena=1
4
4
rf=1,cf=1
VGA
6
6
CIF
8
8
8
8
10
12
14
10
12
14
12
12
0
4
8
12
0
2
4
6
8
10
12
14
Fig 4.3.4
4.3.5 Output timing of sub-sampling
4.3.5.1 Sub-sampling VGA(640X480) from (1288 X 968 ) windowing:
(with 4 column and 2 row for color interpolation)
cf[1:0] = 1, rf[1:0]=1, sub-sampling rate (1/2,1/2),
wcp[10:0]=0, wcw_in[10:0]=1287, column pixels 644=(1287+1)/2,
wrp[10:0]=0,wrd[10:0]=963, row pixel 484=(963+1)/2,
cm =1, single_path = 1, row_ave= 1, CDS_ext2_in =1.
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PAS005B
CMOS Image Sensor IC
linetime= 480+4(x)+4(D)+644+4(x)= 1136pixclks
Hsync.
480pixclks
x x x
x x x x
644pixels0ut x x x x
x x x x
D D D D
644pixelsout
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"dark.
Pixclk_a
Fig 4.3.5.1-1 Inter-line timing (default)
linetime= cov[10:0]+480+4(x)+4(D)+644+4(x) pixclks
Hsync.
cov[10:0]+480
x x x
x x x x
644pixels0ut x x x x
x x x x
D D D D
644pixelsout
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"indicatesdark.
Pixclk_a
Fig .4.3.5.1-2 Inter-line timing (programmable)
Frametime(min)(=484lines)
Vsync.
480
Pixclks
480
Pixclks
Dark
Dark
Dark
Dark
Hsync.
B,G,B,G...
G,R,G,R...
B,G,B,G...
Validframedata(482lines)
Fig 4.3.5.1-3 Inter-frame timing (default)
Frametime=lpf[14:0]+3lines
Vsync.
Hsync.
Pixclks
1
Dark
1
Dark
0
Dark
0
Dark
Validframedata
(480lines)
Validframedata
(480lines)
Fig 4.3.5.1-4 Inter-frame timing (programmable)
4.3.5.2. Sub-sampling QVGA(318X240) from (1288 X 968 ) windowing:
(with 4 column and 2 row for color interpolation)
cf[1:0] = 2, rf[1:0]=2, sub-sampling rate (1/4,1/4),cm =1, single_path = 1, row_ave= 1, CDS_ext2_in =1.
wcp[10:0]=0, wcw_in[10:0]=1287, column pixels 322=(1287+1)/4,
wrp[10:0]=0,wrd[10:0]=967, row pixel 242=(967+1)/4,
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linetime= 480+4(x)+4(D)+322+4(x)= 848pixclks
Hsync.
480pixclks
x x x
x x x x
322pixels0ut x x x x
x x x x
D D D D
322pixelsout
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"dark.
Pixclk_a
Fig .4.3.5.2-1. Inter-line timing (default)
linetime= cov[10:0]+480+4(x)+4(D)+322+4(x) pixclks
Hsync.
cov[10:0]
+480
x x x
x x x x
322pixels0ut x x x x
x x x x
D D D D
322pixelsout
x
D D D D
Note:"x"indicatesdon'tcarePXD[9:0],"D"indicatesdark.
Pixclk_a
Fig 4.3.5.2-2 Inter-line timing (programmable)
Frametime(min)(=242lines)
Vsync.
Hsync.
480
Pixclks
480
Pixclks
Dark
Dark
Dark
Dark
B,G,B,G...
G,R,G,R...
B,G,B,G...
Validframedata(242lines)
Fig 4.3.5.2-3 Inter-frame timing (default)
Frametime=lpf[14:0]+3lines
Vsync.
Hsync.
Pixclks
1
Dark
1
Dark
0
Dark
0
Dark
Validframedata
(242lines)
Validframedata
(242lines)
Fig .4.3.5.2-4 Inter-frame timing (programmable)
4.4 Snapshot mode
Typically, the snapshot mode must work with the aid of an external mechnical shutter. PAS005 support two
types of snapshot mode to fit the different exposure time request.
Snapshot mode 1: register seq_exp=1
When the exposure time is longer than the mechanical shutter speed limitation, snapshot mode 1 is chosen.
The exposure period is now controlled by the mechanisms of shutter opening and close as shown in Fig. 4.
The mechanical shutter can be trigger by the clock edge of output signal Vsync and all pixels will be exposure
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concurrently. The shutter closing edge must be earlier than the Vsync edge by programming proper register
value LPF (Line-per-Frame). The suggested setting of ny (ne) in this mode is 0 to guarantee simultaneous
exposure in the shutter opening period. However, different setting is accptable depend on application.
Snapshot mode 2: register seq_exp=0
When the exposure time is less than the mechanical shutter speed limitation, snapshot mode 2 is chosen. The
exposure period is now controlled by exposure start point and shutter closing edge as shown in Fig. 5. The
exposure starting point is setted by register ny and ne, and the sensor array will be started to exposure
simultaneously. Again, the shutter closing edge must be earlier than the Vsync edge.
All these two snapshot modes can be external triggered by pin “Sync” as shown in Fig. 4.4-1 and 4.4-2.
Mechanical shutter
opening period
Mechanical
shutter
ny=0, ne=0
start point
end point
Active Exposure time
Array
leakage
Image exposure and
readout timing
Array
leakage
Vsync extension
programmed by LPF
Non-Valid
Data
Valid
Data
Vsync
External Sync
Fig. 4.4-1 Snapshot mode one – Exposure time controlled by shutter.
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Mechanical shutter
opening period
Mechanical
shutter
Exposure start point
programmed by ny, ne
start point
end point
Active exposure time
Image exposure and
readout timing
Array
reset
Array
leakage
Vsync extension
programmed by LPF
Non-Valid
Data
Valid
Data
Vsync
External Sync
Fig. 4.4-2 Snapshot mode two – Exposure time smaller than shutter speed limitation.
4.5 External synchronization control
The sensor core timing can be reset by external “Sync” pin. The internal counter will start from initial point at
the rising edge of trigger signal “Sync”. Meanwhile, Vsync signal is reset to zero. Waiting the coming of
Vsync pulse, a valid frame will be output after the pulse with the programmed ny, ne and gain code, as shown
in Figs. 4.4-1 and 4.4-2.
4.6 Frame rate
1
Frame rate =
(LPF +1+ 2) ⋅t _ line
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X:
Int:8
Dk:4
Dummy: 2
Y:
Novtime
linetime
10us(240ck@ 24M )
t_line=1534ck
Int:4
Dk:2
frametime
t_frame=1030*1534ck
=24M/(1030*1534)
=15.2fps
Megaframerate
VGA(average)
VGA(Non_average)
2path:
=24M/((654+240*2)*486)
=43.5fps
t_line=x+8+4+2
=x+14
LPF=y+4+2
=y+6
=24M/((654+240*1)*486)
=55.2fps
Pixelclock=16.5M
when30fps
VGA(average)
Double_path
VGA(average)
(single_path)
=24M/((1306+480)*486)
=27.6fps
1path:
t_line=(x+8+4+1)*2
=2*x+26
LPF=y+4+2
=y+6
VGA(non-average) =24M/((1306+240)*486)
(single_path)
=32fps
Single_path
Nov
row_addr
New frame, Row<2046>
last
reg_upd
ny_ena_clk ny_clk
exp_frame_rst
exposure Frame N+1
exposureFrameN
read Frame N-1
readFrameN fail
In normal operating condition, register 3 ~ 40 are synchronized by frame. The programming method is
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writing the registers followed by setting “flag” register to 1. Registers 4 ~ 15 are some critical registers that
influent the sensor cell array. If the readout pixels aare changed, register 16(mode_chg_reg) should be set to 1
to reset the full array. So the programming sequence is writing the registers, set mode_chg, than set flag. If
mode_chg_ena register is 1, these registers will be protected unchanged till setting mode_chg followed by
setting flag.
4.7 Exposure Programming
The Exposure Time calculation of PAS005 is based on the following sequence:
1. System clk
2. Pxclk
3. Frame rate
4. Exposure time
5. Equivalent exposure line and pixel number
6. Register (Ny)offset_ny,(Ne) offset_ne
For a given Sysclk, pxclk and EX-time:
Np = Sysclk / pxclk.
The Exposure Time calculation of PAS005 is based on the following Register:
Default
(Decimal)
R/W
R/W
R/W
Register
Register
Np[5:0]
Description
Pixel rate = frequency of I_Sysclk / Np
Programming range of Np: 1~63
Analog signal processing single or double path
0: double path, 1: single path
Color mode or Mono mode(used only in sub-
sampling mode)
Reg_3[5:0]
2
Reg_4[7]
Reg_4[6]
single_path
cm
0
1
R/W
R/W
0: Mono mode, 1: color mode
column frequency
00: Normal readout without sub-sampling,
01: 1/2 sub-sampling
10: 1/4 sub-sampling,
Reg_4[3:2]
Reg_4[1:0]
cf[1:0]
rf[1:0]
0
0
11: 1/8 sub-sampling
row frequency
00: Normal readout without sub-sampling,
01: 1/2 sub-sampling
R/W
10: 1/4 sub-sampling,
11: 1/8 sub-sampling
Reg_5[2:0]
Reg_6[7:0]
Reg_7[2:0]
Reg_8[7:0]
Reg_9[2:0]
wcp_in[10:8]
wcp_in[7:0]
wcw_in[10:8]
wcw_in[7:0]
wrp[10:8]
R/W
R/W
R/W
R/W
R/W
0
0
1287
1287
0
window column pointer
window column pointer
window column width
window column width
window row pointer
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Reg_10[7:0]
Reg_11[2:0]
Reg_12[7:0]
wrp[7:0]
R/W
R/W
R/W
0
1027
1027
window row pointer
window row depth
window row depth
wrd
wrd
CDS timing extension to 2 times of normal CDS
timing for 48M pixel rate
Reg_13[5]
CDS_ext2_in
R/W
0
Reg_13[4]
Reg_13[0]
row_ave
Snap_ena
Cov[10:8]
Cov[7:0]
LPF[13:8]
LPF[7:0]
ny[13:8]
ny[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1027
1027
0
0
0
row average for row sub-sampling
Reg_14[2:0]
Reg_15[7:0]
Reg_17[5:0]
Reg_18[7:0]
Reg_19[5:0]
Reg_20[7:0]
Reg_21[5:0]
Reg_22[7:0]
column overhead: used to increase line time
column overhead: used to increase line time
Line per frame: total frame time = (LPF+1)+2 lines
Line per frame: total frame time = (LPF+1)+2 lines
Exposure time start point offset in line resolution
Exposure time start point offset in line resolution
Exposure time start point offset in pixel resolution
Exposure time start point offset in pixel resolution
ne[13:8]
ne[7:0]
0
EXAMPLE_1: MEGA Exposure time setting
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when
system clock 48M hz
pxclk
24M hz
exposure time
8/120 sec
Please keep L_P_F = 1027
And Calculate Ny = ? and Ne = ? ,
Application
System_clk
48
Np
2
Pixel_clk(MHz)
24
Power frequency EX_time (x/120)
60HZ
8
cov
0
L_P_F
frame_rate<10
1027
Register setting
CM
1
row_average
CDSx2
single_path
0
1
0
Wcw
1287
Wrd
1027
cf
0
rf
0
Key in Register
L_P_F
Ny
131
Ne
159
t_line
1780
1027
1. ExposureTim ={[(LPF+1+2)-Ny]*t_line- Ne'}/Pxclk
2. t_line = (active_line_pixel + t_nov + 12) = 1300 + 480 + 12 = 1780 Pxclk
t_nov = 480 + Cov Pxclk
3. Ny = INT[(L_P_F+3) - (( EX_Time * Pxclk ) / t_line)]
131 = INT [(1027+3 ) - (( 8/120
* 24 M ) / 1780 )]
4.Ne = Res[(L_P_F + 3) - (( EX_Time * Pixel_clk ) / t_line)] * active_line_pixel
159 = Res[(1027 +3) - (( 8/120
*24 M
) / 1780 )] * 1300
1
5. Frame rate =
= 1/(1027+3)* 1780 = 13 (per/sec)
(LPF +1+ 2)⋅t _ line
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EXAMPLE_2: VGA Exposure time setting
when system clock 48M hz
pxclk
16M hz
4/120 sec
exposure time
Please keep L_P_F = 483
and Calculate Ny = ? and Ne = ? ,
Application
System_clk
48
Np
3
Pixel_clk
16
Power frequency EX_time (x/120)
60HZ
4
C_nov
0
L_P_F
frame_rate<30
28.98046717
3
483
Register setting
CM
1
row_average
CDSx2
single_path
1
1
1
Wcw
1287
Wrd
967
Cf
1
rf
1
Key in Register
L_P_F
Ny
16
Ne
332
t_line
1136
483
1.ExposureTim ={[(LPF+1+2)-Ny]*t_line- Ne}/Pxclk
2. t_line = (active_line_pixel + t_nov + 12) = 644 + 480 + 12 = 1136 Pxclk
t_nov = 480 + Cov Pxclk
3. Ny = INT[(L_P_F+3) - (( EX_Time * Pxclk ) / t_line)]
16 = INT [(483+3 ) - (( 4 /120
* 16 M ) / 1136 )]
4.Ne = Res[(L_P_F + 3) - (( EX_Time * Pixel_clk ) / t_line)] * active_line_pixel
332 = Res[( 483 + 3 ) - (( 4/120
* 16 M
) / 1136 )] * 644
1
5. Frame rate =
= 1/(483+3)* 1136 = 29
(LPF +1+ 2)⋅t _ line
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EXAMPLE_3: QVGA Exposure time setting
when system clock 48M hz
pxclk
12M hz
2/120 sec
exposure time
Please keep L_P_F = 241
and Calculate Ny = ? and Ne = ? ,
Application
System_clk
48
Np
4
Pixel_clk
12
Power frequency EX_time (x/120)
60HZ
2
C_nov
6
L_P_F
frame_rate<60
59.9760096
241
Register setting
CM
1
row_average
CDSx2
single_path
1
1
1
Wcw
1287
Wrd
967
cf
2
rf
2
Key in Register
L_P_F
Ny
0
Ne
31
t_line
820
241
1.ExposureTim ={[(LPF+1+2)-Ny]*t_line- Ne}/Pxclk
2. t_line = (active_line_pixel + t_nov + 12) = 322 + 486 + 12 = 820 Pxclk
t_nov = 480 +Cov Pxclk = 486 Pxclk
3. Ny = INT[(L_P_F+3) - (( EX_Time * Pxclk ) / t_line)]
0 = INT [(241 + 3 ) - (( 2/120
* 12 M ) / 820 )]
4.Ne = Res[(L_P_F + 3) - (( EX_Time * Pixel_clk ) / t_line)] * active_line_pixel
31 = Res[(241 +3) - (( 2/120
*12 M
) / 820 )] * 322
1
5. Frame rate =
= 1/(241+3)* 820 = 60
(LPF +1+ 2)⋅t _ line
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EXAMPLE_4: Sunlight mode Exposure time setting
MEGA setting
when
system clock 48M hz
pxclk
12M hz
< one line pxclk (sec)
exposure time
Please keep L_P_F = 1027
And Calculate Ny = ? and Ne = ? ,
Application
System_clk
48
Np
4
Pixel_clk(MHz)
12
Power frequency EX_time (x/120)
60HZ
X_t
cov
0
L_P_F
1027
Register setting
CM
1
row_average
CDSx2
single_path
0
1
0
Wcw
1287
Wrd
1027
Cf
0
rf
0
Key in Register
L_P_F
Ny
1029
Ne<1300
X_Ne
t_line
1780
1027
1. ExposureTim (X_t)=[1030– Ne(X_Ne)]/Pxclk (sec)
1
2. Frame rate =
= 1 / (1027+3) * 1780 = 13
(LPF +1+ 2)⋅t _ line
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4.8 DAC & PGA lagging
DAC PGA lagoneframe
Vsync
new DAC,Gg,Cg
operate
ny,ne
DAC
new ny,neoperate
Gg,Cg
update
Normally the readout of current frame will be exposed in the readout of the previous frame. To
easily program the sensor, one can send exposure registers(ny, ne), dac and gain registers(Gg, Cg)
followed by setting the “flag” register, the new updated DAC, Gg, Cg will operate 1 frame after new
updated ny, ne automatically by programming the “dac_pg_lag” register.
4.9 Power down
snap
Nov
lastrow
lastrow +1
lastrow readout
LPF
New frameDk0
row_addr
ny_ena_clk
reg_upd
Concurrent exposure:
ny:last_row+3~LPF+3
Sequential exposure:
ny:0~LPF+3
exp_frame_rst
ny_clk
CDSPowerdown
ASPPowerdown
Power down is classified as DSC_pd, CDS_pd and ASP_pd.
DSC_pd is to disable the digital timing(column address, CDS timing) in redundant rows.
CDS_pd pulls T_cds_EnL to 1 in redundant rows.
ASP_pd is to close DAC, PGA, and ADC in redundant rows.
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4.10 Reset management
There are five kinds of reset: “pu”, “csb”, “sfpd”, “sfrst”, “sync”. “pu” is the most strong reset. It reset full chip.
“csb” reset the full chip, but retain the register setting. “sfpd” reset the sensor core, but I2C interface is live.
“sfrst” is an register signal. Every time it is programmed to “1”, all the I2C registers are reset. After that, it will
be reset to zero. “sync” reset the sensor core timing. To avoid the recovering time problem, clock oscillating is
designed to start a little time after “pu”, “csb” and “sfpd” reset is released.
Reset
Analog
I2C Registers
DigitalCore
I2C control
sfrst
sfpd
(levelsignal)
D
CSB
PU
A
B
C =A |sfpd
ClockReset::
Processing
I2C_sam :PU,CSB
ck12,pxck:PU,CSB,sfpd
Sync
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5. I2C Bus
PAS005B supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is
1000000 and supports receiving / transmitting speed up to 400kHz.
5.1 I2C bus overview
Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected
to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external
pull-up resistors.
Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop).
Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start
condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please
refer to Fig 5.1.
Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each
byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to
Fig 5.2.
Both the master and slave can transmit and receive data from the bus.
Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock
line when a complete byte was transferred by transmitter. In the case of a master received data from a
slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master
read cycle.
SDA
SCL
S
P
Start
Condition
Stop
Condition
Fig 5.1 Start and Stop Conditions
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SDA
SCL
DATA
CHANGE
ALLOWED
DATA
STABLE
Fig 5.2 Valid Data
5.2 Data Transfer Format
5.2.1 Master transmits data to slave (write cycle)
S : Start
A : Acknowledge by slave
P : Stop
RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle.
RW=1 read cycle, RW=0 write cycle.
SUBADDRESS : The address values of PAS005B internal control registers
(Please refer to PAS005B register description)
1ST BYTE
2ND BYTE
n BYTEs + A
S
SLAVE ID (7 BIT)
RW
A
SUBADDRESS (8 BIT)
A
DATA
A
DATA
A
P
MSB
LSB=0
During write cycle, the master generates start condition and then places the 1st byte data that are combined
slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS005B) issues acknowledgment,
the master places 2nd byte (sub-address) data on SDA line. Again follow the PAS005B acknowledgment, the
master places the 8 bits data on SDA line and transmit to PAS005B control register (address was assigned by
2nd byte). After PAS005B issue acknowledgment, the master can generate a stop condition to end of this write
cycle. In the condition of multi-byte write, the PAS005B sub-address is automatically increment after each
DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value
inside PAS005B can be programming via this way. (Please refer to Fig 5.3.)
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5.2.2 Slave transmits data to master (read cycle)
The sub-address was taken from previous write cycle
The sub-address is automatically increment after each byte read
Am : Acknowledge by master
Note there is no acknowledgment from master after last byte read
1ST BYTE
2ND BYTE
n BYTE
Am
SLAVE ADDRESS
(7 BITS)
S
RW
A
DATA (8 BIT)
Am DATA
DATA
1
P
NO ACK IN LAST
BYTE
During read cycle, the master generates start condition and then place the 1st byte data that are combined
slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was
also placed on SDA line by PAS005B. The 8 bit data was read from PAS005B internal control register that
address was assigned by previous write cycle. Follow the master acknowledgment, the PAS005B place the next 8
bits data (address is increment automatically) on SDA line and then transmit to master serially. The DATA and
Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead
by keep SDA line high. The slave (PAS005B) must releases SDA line to master to generate STOP condition.
(Please refer to Fig 5.3.)
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
P
S
ACK
from
Receiver
ACK
from
Receiver
Stop
Condition
ACK
from
Receiver
Address
R/W
Data
Data
Start
Condition
Fig 5.3 Data Transfer Format
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E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
5.3 I2C Bus Timing
SDA
tBUF
tHD;STA
tr
tf
tSP
tf
tr
tSU;DAT
tLOW
SCL
tSU;STO
P
S
S
Sr
tHD;STA
tSU;STA
tHD;DAT
tHIGH
Fig 5.4 I2C Bus Timing
5.4 I2C Bus Timing Specification
STANDARD-MODE
UNIT
PARAMETER
SYMBOL
MIN.
10
MAX.
400
-
SCL clock frequency
kHz
us
f
scl
Hold time (repeated) START condition.
After this period, the first clock pulse is generated.
4.0
t
HD:STA
Low period of the SCL clock
4.7
0.75
4.7
0
-
us
us
us
us
ns
t
t
t
t
t
t
t
t
t
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
HIGH period of the SCL clock
-
Set-up time for a repeated START condition
Data hold time. For I2C-bus device
Data set-up time
-
3.45
250
30
-
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START
Capacitive load for each bus line
N.D.
ns(note1)
30
N.D.
ns(note1)
f
4.0
4.7
1
-
-
us
us
pF
V
SU;STO
BUF
15
-
C
V
b
Noise margin at LOW level for each connected
device (including hysteresis)
Noise margin at HIGH level for each connected
device (including hysteresis)
nL
nH
0.1 VDD
0.2 VDD
-
V
V
Note: It depends on the "high" period time of SCL.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
6. Specifications
Absolute Maximum Ratings
Symbol
Parameter
Min
-0.5
0.5
Max
3.8
Unit
V
Vdd
DC supply voltage
DC input voltage
Vin
Vout
Tstg
Vdd+0.5
Vdd+0.5
TBD
V
-0.5
TBD
V
DC output voltage
Storage temperature
℃
DC Electrical Characteristics (VDD=3.0V±20%, Ta=10°C~40°C )
Symbol
Type :PWR
VDD
Parameter
Min.
Typ.
Max. Unit
Analog and digital operating voltage
Operating Current
2.4
3.0
8
3.6
V
IDD
MA
UA
Istby
Standby current
100
Type :IN & I/O Reset and SYSCLK
VIH
VIL
Cin
Input voltage HIGH
Input voltage LOW
Input capacitor
2.0
0
VDD
0.8
V
V
10
PF
UA
Ilkg
Input leakage current
TBD
Type : OUT & I/O for PXD0:7, PXCK, H/VSYNC & SDA, load 10pf, 1.2kΩ, 3.0volts
VOH
VOL
Output voltage HIGH
Output voltage LOW
Vdd-0.2
V
V
0.2
AC Operating Condition
Symbol
Parameter
Min.
Typ.
Unit
Max.
SYSCLK
PXCK
Master clock frequency
4.5
48
MHz
MHz
Pixel clock output frequency
1.5
Sensor Characteristics
Parameter
Symbol
PRNU
Sat.
Typ.
1.40
696
17
Unit
Note
Photo response non-uniformity
Saturation output voltage
Dark output voltage
Dark signal non-uniformity
Fixed Pattern Noise
Signal to Noise ratio
Dynamic range
%
Level
Level/sec
Level
Level
dB
Vdark
DSNU
FPN
1.87
7.05
42
SNR
DR
48
dB
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
7. Package Information
7.1. Pin Connection Diagram
42 41 40 39 38 37 36 35 34 33 32 31
SYSCLK 43
HSYNC 44
PXCLK 45
30 SDA
29 SCL
28 VDDD
SYNC
NC
46
47
27
26
VSSD
VSSAY
VSYNC 48
25 X_VDDAY
-- Top View --
NC
CSB
1
2
3
4
5
6
24
23
22
VDDA
VSSA
VDDD
VSSD
VSS_ESD
VDDA
21 X_VREF
20 EXTRESP
19 EXTRESN
X_VDDD
7
8
9
10 11 12 13 14 15 16 17 18
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PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
7.2. Package Outline
0.30
0.13
14.22SQ
11.18 0.13
TYP.
1.58 0.19
REF
1.02 0.08
TYP.
1
48
6
1
48
43
6
43
7
42
42
7
Pin No.1
INDEX
30
0.51 0.08
TYP.
18
31
31
30
19
30
19
1.06 0.15
R0.19
48 PLCS
REF
-- Top View --
1.02 0.2
-- Bottom View --
-- Side View --
(All dimensions are in Millimeters)
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
PixArt Imaging Inc.
PAS005B
CMOS Image Sensor IC
8. Referencing application circuit
CSB_SW
VDDD
2
1
SCL
SDA
PX0
PX1
PX2
PX3
PX4
PX5
PX6
PX7
PX8
PX9
CSB
R5
300k
C17
1uF
VDDD
R1
1.5K
C1
10uF
R7
R8
C2
C3
C4
4.7K
4.7K
LED1
LED
0.1uF 0.1uF 0.1uF
SYSCLK
HSYNC
PXCLK
30
43
44
45
46
47
48
1
2
3
4
5
SYSCLK
HSYNC
PXCLK
SYNC
NC
VSYNC
CSB
VDDD
VSSD
VSS_ESD
VDDA
X_VDDD
SDA
29
VDDAY
SCL
28
VDDD
27
VSSD
26
25
24
23
22
21
20
19
JP1
L1
VSSAY
X_VDDAY
NC
VDDA
VSSA
X_VREF
EXTRESP
EXTRESN
VSYNC
CSB
C7
U1
1
2
C6
PAS005B
C5 JUMPER
0.1uF
FB
10uF
L2
0.1uF
R2
6
FB
27K
VDDA
VDDD
L3
R3
R4
FB
L4
300k
300k
C12
10uF
C9 C10 C11
0.1uF 0.1uF 0.1uF
C13
C14
0.1uF
FB
C15
C16
0.1uF
0.1uF
0.1uF
JP1
PX8
PX6
PX4
PX9
PX7
PX5
1
3
5
7
2
4
6
8
VDDD
PX2
PX0
VSYNC
SYSCLK
SDA
PX3
PX1
PXCLK
HSYNC
SCL
<OrgName>
9
10
11
13
15
17
19
21
12
14
16
18
20
22
VDDA
VDDAY
CSB
Title
PAS005-SENSORBOARD.DSN
Document Number
HEADER 11X2
Size
B
Rev
A1
PAS005B SENSOR BOARD
Date:
Wednesday, May 22, 2002 Sheet
1
of
1
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: fae_service@pixart.com.tw
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