PAS202BBA_技术文档

PAS202BCA

PAS202BBA

PAS202BCA SINGLE-CHIP CMOS VGA COLOR DIGITAL IMAGE SENSOR

PAS202BBA SINGLE-CHIP CMOS VGA B&W DIGITAL IMAGE SENSOR

General Description

ThePAS202BCA/PAS202BBA is a highly integrated CMOS active-pixel image sensor that has a VGA resolution

of 644H x 484V. To have an excellent image quality, the PAS202BCA/PAS202BBA outputs 10-bit RGB raw data

through a parallel data bus. It is available in color or monochrome and in 323-pin LCC.

The PAS202BCA/PAS202BBA can be programmed to set the exposure time for different luminance condition via

I2C^TMserial control bus. By programming the internal register sets, it performs on-chip frame rate adjustment,

offset correction DAC and programmable gain control.

Key Specification

Supply Voltage

Resolution

Features

§VGA(644 x 484 pixels) resolution, ~1/4” Lens

§Bayer-RGB color filter array

3.3V + 10%

644(H) x 484(V)

4.5mm (~1/4”Optic)

5.6mmX5.6mm

~30 fps

§On-chip 10-bit pipelined A/D converter

§Output format: 10-bit parallel RGB raw data

§On-chip 9-bit background compensation DAC

§On-chip programmable gain amplifier

Array diagonal

Pixel Size

q

4-bit color gain amplifier(x3)

5-bit global gain amplifier (x5)

Frame rate

System clock

Max. pixel rate

Sensitivity

Up to 48 MHz

§Continuous variable frame time(1/2sec~1/30sec)

§Continuous variable exposure time

§I2C Interface

12MHz

0.6V/Lux-sec(green)

29.5 dB max.

§Digitally programmable registers

PGA gain

§Single 3.3V supply voltage

§100 mW low power dissipation

Color filter

Exposure Time

Scan Mode

RGB Bayer Pattern

~ Frame time to 4 pxclk

§350 uW low power down dissipation

§Flash light timing

§Mirror output

Progressive

>42 dB

S/N Ratio

Package

32 pins LCC

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

1

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

1. Pin Assignment

Pin No.

Name

VSSAY

Type

Defintion

1

GND

BIAS

Analog ground

Fixed bias input voltage, 1.65V

2

VLRST

PXD9

PXD8

PXD7

PXD6

PXD5

VDDQ

VSSQ

PXD4

PXD3

NC

3

OUT

PWR

GND

OUT

Digital data out

Digital VDD, 3,3V

Digital ground

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Digital ground

Digital data out

Not connected

PXD2

PXD1

PXD0

SYSCLK

PXCLK

HSYNC

VSYNC

SCL

OUT

IN

Digital data out

Master clock input

Pixel clock output

Horizontal synchronization signal

Vertical synchronization signal

I2C clock

OUT

IN

SDA

I/O

I2C data

VDDD

VSSD

CSB

PWR

GND

IN

Digital VDD, 3.3V

Digital ground

Chip select (Low, active, chip disable if high)

Analog voltage reference

Not connected

VCM

BYPASS

VRT

VRB

NC

VSSA

VDDA

VDDAY

GND

PWR

Analog ground

Analog VDD, 3.3V

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

2

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

2. Block Diagram

dac[8:0]

9-bit

+/-1V

DAC

SensorArray

Colorgain

B,G,R

4-bits

Globalgain

5-bits

X3

CDSckts

X5

Col.Decoders

cmd

10-bit

pipelined

ADC

Timing

&

DigitalControl

Register

sets

I2C

Interface

Fig 2.1 – Block diagram of the PAS202BCA/PAS202BBA

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

3

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

3. Output Format

3.1. Pixel Array And Pixel Color Pattern

The output image format of PAS202BCA/PAS202BBA is VGA (640x480 pixel array). To provide the

co-processor with the extra information it needs for interpolation at the edges of the pixel array, an border of 2

pixels on all 4 sides of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern.

13 dark

pixel

13 dark

pixel

13 dark

pixel

13 dark

pixel

13

No filter

pixel

13

pixel

R

13

pixel

G

13

pixel

B

540 dark pixel

Dark pixel

Row 485

Row 484

R

G

B

G

R

G

R

G

R

G

R

B

G

B

G

B

G

B G

G

R

G

R

G

R

G

R

Pixel array: 644(H) x 486(V)

s

G

B

G

B

G

B G

G

R

G

R

G

R

G

R

Row 1

Row 0

B

G

B

G

B

G

R

G

B

Dark pixel

13

pixel

B

13

No filter

pixel

13

pixel

R

13

pixel

G

540 dark pixel

13 dark

pixel

13 dark

pixel

13 dark

pixel

13 dark

pixel

644

column lines

Fig 3.1. Pixel array and pixel color pattern

Note:

1. Pixel color pattern does not apply to monochrome sensor.

2. Pixel read-out proceeds from left to right, and from bottom row to top row.

3. Pixel array not drawn to scale.

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

4

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

3.2 Output timing:

Ÿ Pixel per line is programmable, 772 pixels ~ 1156 pixels.

Ÿ 4+4 blank pixel for each line. ( See Fig 3.2. Fig 3.3)

Ÿ 1+1 Dark line for each frame.(See Fig 3.4. Fig 3.5 )

Ÿ Dark line output format: Fig 3.6.

linetime(min)= 120+4+2+640+2+4= 772pixclks

Hsync.

120pixclks

2+640+2pixelsout

x x x

x x x x

x x x x 2+640+2pixelsout

Note:"x"indicatesdon'tcarePXD[9:0]

G

B

Pixclk_a

Fig 3.2. Inter-line timing (default)

Nov_by2*2-8

pixclks

linetime=4+644+4 pixclks

Hsync.

Note:"x"indicatesdon'tcarePXD[9:0]

2+640+2pixelsout

x x x

x x x x

x x x x 2+640+2pixelsout

G

B

Nov_by2*2 pixclks

Pixclk_a

Fig 3.3. Inter-line timing (programmable)

Frametime(min)(=486lines)

Vsync.

120

Pixclks

Dark

Hsync.

G,R,G,R...

B,G,B,G...

Validframedata(484lines)

Fig 3.4. Inter-frame timing (default)

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

5

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

Frametime=lpflines

Vsync.

Pixclks

Dark

Hsync.

Validframedat

(484lines)

Validframedata

(484lines)

Validframedata

(484lines)

Fig 3.5. Inter-frame timing (programmable)

R

G

B

Row

Dark pixel

13B

pixel

13

No

pixel

13R

pixel

13G

pixel

540 Dark pixel

13dark 13dark 13dark

pixel pixel pixel

13dark

pixel

644

column lines

Fig 3.6. Dark line output format

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

6

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

4. I2C Bus

PAS202BCA/PAS202BBA supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique

slave address is 1000000 and supports receiving / transmitting speed up to 400kHz.

4.1 I2C bus overview

§Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected

to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external

pull-up resistors.

§Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop).

§Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start

condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please

refer to Fig 4.1.

§Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each

byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to

Fig 4.2.

§Both the master and slave can transmit and receive data from the bus.

§Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock

line when a complete byte was transferred by transmitter. In the case of a master received data from a

slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master

read cycle.

SDA

SCL

S

P

Start

Condition

Stop

Condition

Fig 4.1 Start and Stop Conditions

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

7

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

SDA

DATA

CHANGE

ALLOWED

DATA

STABLE

SCL

Fig 4.2 Valid Data

4.2 Data Transfer Format

4.2.1 Master transmits data to slave (write cycle)

§

S : Start

A : Acknowledge by slave

P : Stop

RW : The LSB of 1^STbyte to decide whether current cycle is read or write cycle.

RW=1 read cycle, RW=0 write cycle.

§

SUBADDRESS : The address values of PAS202BCA/PAS202BBA internal control registers

(Please refer to PAS202BCA/PAS202BBA register description)

1ST BYTE

2ND BYTE

n BYTEs + A

S

SLAVE ID (7 BIT)

RW

A

SUBADDRESS (8 BIT)

A

DATA

A

DATA

A

P

MSB

LSB=0

st

During write cycle, the master generates start condition and then places the 1 byte data that are combined

slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS202BCA/PAS202BBA) issues

acknowledgment, the master places 2^ndbyte (sub-address) data on SDA line. Again follow the

PAS202BCA/PAS202BBA acknowledgment, the master places the 8 bits data on SDA line and transmit to

PAS202BCA/PAS202BBA control register (address was assigned by 2^ndbyte). After

PAS202BCA/PAS202BBA issue acknowledgment, the master can generate a stop condition to end of this

write cycle. In the condition of multi-byte write, the PAS202BCA/PAS202BBA sub-address is automatically

increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

8

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

registers value inside PAS202BCA/PAS202BBA can be programming via this way. (Please refer to Fig 4.3.)

4.2.2 Slave transmits data to master (read cycle)

§ The sub-address was taken from previous write cycle

§ The sub-address is automatically increment after each byte read

§ Am : Acknowledge by master

§ Note there is no acknowledgment from master after last byte read

1ST BYTE

2ND BYTE

n BYTE

Am

SLAVE ADDRESS

(7 BITS)

S

RW

A

DATA (8 BIT)

Am DATA

DATA

1

P

NO ACK IN LAST

BYTE

During read cycle, the master generates start condition and then place the 1^stbyte data that are combined

slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was

also placed on SDA line by PAS202BCA/PAS202BBA. The 8 bit data was read from PAS202BCA/PAS202BBA

internal control register that address was assigned by previous write cycle. Follow the master acknowledgment,

the PAS202BCA/PAS202BBA place the next 8 bits data (address is increment automatically) on SDA line and

then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read,

Am is no longer generated by master but instead by keep SDA line high. The slave (PAS202BCA/PAS202BBA)

must releases SDA line to master to generate STOP condition. (Please refer to Fig 4.3.)

SDA

SCL

1-7

8

9

1-7

8

9

1-7

8

9

P

S

ACK

from

ACK

from

Stop

Condition

ACK

from

Receiver

Address

R/W

Data

Start

Condition

Receiver

Fig 4.3 Data Transfer Format

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

9

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

4.3 I2C Bus Timing

SD A

tBUF

tHD;STA

tr

tf

tSP

tf

tr

tSU;DAT

tLOW

SC L

tSU;STO

P

S

tHD;STA

Sr

tSU;STA

tHD;DAT

tHIGH

Fig 4.4 I2C Bus Timing

4.4 I2C Bus Timing Specification

PARAMETER

STANDARD-MODE

UNIT

SYMBOL

MIN.

10

MAX.

400

-

SCL clock frequency

kHz

us

fscl

Hold tie (repeated) START condition.

After this period, the first clock pulse is generated.

Low period of the SCL clock

4.0

tHD:STA

4.7

0.75

4.7

0

-

us

ns

t

LOW

HIGH

SU;STA

HD;DAT

HIGH period of the SCL clock

-

Set-up time for a repeated START condition

Data hold time. For I2C-bus device

Data set-up time

-

3.45

250

30

-

t

SU;DAT

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

Bus free time between a STOP and START

Capacitive load for each bus line

N.D.

ns(note1)

tr

tf

30

N.D.

ns(note1)

4.0

4.7

1

-

us

pF

V

t

SU;STO

tBUF

15

-

C

b

Noise margin at the LOW level for each connected

device (including hysteresis)

Noise margin at the HIGH level for each

connected device (including hysteresis)

VnL

0.1 VDD

0.2 VDD

-

V

VnH

Note 1: It depends on the "high" period time of SCL.

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

10

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

5. Specifications

Absolute Maximum Ratings

Symbol

Parameter

Min

-0.5

0.5

Max

3.8

Unit

V

Vdd

DC supply voltage

DC input voltage

Vin

Vdd+0.5

V

Vout

-0.5

V

DC output voltage

DC Electrical Characteristics (VDD=3.3V±10%, Ta=0°C~40°C )

Symbol

Type :PWR

VDD

Parameter

Min.

Typ.

Unit

Max.

Analog and digital operating voltage

Operating Current

3.00

3.3

30

3.60

V

IDD

mA

Type :IN & I/O Reset and SYSCLK

VIH

VIL

Cin

Input voltage HIGH

Input voltage LOW

Input capacitor

2.0

0

VDD

0.8

10

V

pF

uA

Ilkg

Input leakage current

1.0

Type : OUT & I/O for PXD0:9, PXCLK, H/VSYNC & SDA, load 20pf, 3.3volts

VOH

VOL

Output voltage HIGH

Output voltage LOW

Vdd-0.2

V

0.2

AC Operating Condition

Symbol

Parameter

Min.

Typ.

Unit

Max.

48

fsysclk

fpxclk

Master clock frequency

8

MHz

Pixel clock output frequency

12

Sensor Characteristics

Parameter

Symbol Min. Typ.

Max.

Unit

%

Note

Photo response non-uniformity

Saturation output voltage

Dark output voltage

PRNU

Vsat.

Vdark

DSNU

R

1.7

1.2

53

V

mV/sec

Lsb

Dark signal non-uniformity

Sensitivity ( Red channel )

Sensitivity ( Green channel )

Sensitivity ( Blue channel )

Column non-uniformity

2.79

0.8

0.6

V/Lux-sec

%

G

B

Cnu

1.56

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

11

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

PXCLK Timing Specification @12M Hz

Symbol

Parameter

Min.

40%

Typ.

50%

10

Unit

%

Max.

60%

Low period of the PXCLK duty cycle

High period of the PXCLK duty cycle

tLOW

%

tHIGH

Rise time signal

ns

tr

tf

Fall time signal

10

ns

Capacitive load for each bus line

15

pF

C

b

PXCLK

tf

tr

tLOW

tHIGH

6. Package Information

6.1. Pin Connection Diagram

21

22

23

24

25

26

27

28

29

VSYNC

NC

20

30

31

32

VSSA

VDDA

HSYNC

PXCLK

19

18

17

16

SYSCLK

VHRST

VSSAY

PXD0

PXD1

PXD2

NC

1

2

15

VLRST

PXD9

3

4

14

13

PXD8

12

11

10

9

8

7

6

5

-- Bottom View --

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

12

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

6.2. Package Outline

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

13

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

6.3. Optical Center(Sensor Array Center)and Die/Package Center Offset

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

14

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002

PixArt Imaging Inc.

PAS202BCA/PAS202BBA

CMOS Image Sensor IC

7. Referencing Schematic

VDDD

C2

0.1uF

U1

PXD4

PXD3

PXD2

PXD1

PXD0

VDDA

R1

13

4

3.3V

NC

PXD8

PXD9

14

3

300k

PXD2

15

2

L1

PXD1

VLRST

VSSAY

VDDAY

VDDA

VSSA

NC

16

1

R2

300k

3.3UH

PXD0

SYSCLK

17

18

19

20

PAS202BCA

PAS202BBA

32

31

30

29

VDDD

VDDA

SYSCLK

PXCLK

HSYNC

VSYNC

PXCLK

HSYNC

VSYNC

C13

1uF

C14

C15

C16

1uF

C4

0.1uF

10uF

C3

0.1uF

PAS202

SCL

SDA

C6

10uF

R3

R4

C11

1uF

VDDD

4.7k 4.7k

C10

1uF

C12

1uF

C8

0.1uF

R5

S1

L2

300k

3.3UH

DGND

AGND

CSB

NOTES on capacitors:

1.The 0.1uF caps for pin 8,23,31 and 32 MUST have trace

lengths LESS than 5mm.

Title

pas202BXA-32P

2.C10,C11,C6 for pins 26,27 and 28 MUST have

trace lengths LESS than 5mm.

Size

A

Document Number

PAS202-32PINS-PP.opj BY Jeffery

Rev

V1.0

Date:

Tuesday, May 28, 2002

Sheet

1

of

1

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

15

PixArt Imaging Inc.

E-mail: fae_service@pixart.com.tw

V1.2, May. 2002


型号：	PAS202BBA
厂家：	PIXART IMAGING INC.
描述：	PAS202BCA SINGLE-CHIP CMOS VGA COLOR DIGITAL IMAGE SENSOR PAS202BBA SINGLE-CHIP CMOS VGA B&W DIGITAL IMAGE SENSOR PAS202BCA单片CMOS VGA彩色数字图像传感器PAS202BBA单片CMOS VGA黑白数字图像传感器传感器图像传感器
文件：	总15页 (文件大小：124K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PAS202BBA [PIXART]

相关型号：

PAS202BBB

PAS202BCA

PAS202BCB

PAS2126FR2R5504

PAS3012EV

PAS3012EV-501M

PAS3012EV-681K

PAS302BCA-32

PAS302BCW-22S

PAS309HR-VA5R

PAS309HR-VA6R

PAS309HR-VE5R