LV8844DV106.25M [PLETRONICS]

CRYSTAL OSCILLATOR, CLOCK, 106.25 MHz, LVDS OUTPUT, LEAD FREE, LEADLESS PACKAGE-6;
LV8844DV106.25M
型号: LV8844DV106.25M
厂家: PLETRONICS, INC.    PLETRONICS, INC.
描述:

CRYSTAL OSCILLATOR, CLOCK, 106.25 MHz, LVDS OUTPUT, LEAD FREE, LEADLESS PACKAGE-6

输出元件
文件: 总4页 (文件大小:65K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Pl tronics, Inc.  
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA  
Manufacturer of High Quality Frequency Control Products  
LV8845D LVDS Series  
Low Voltage Differential Signal Output with Enable / Disable  
6 Pad 7 x 5mm Leadless Surface Mount Oscillator  
106.25 MHz and 212.5 MHz typically stock, other frequencies available  
Consult factory for specific frequencies  
Standard Specifications  
Overall Frequency Stability  
± 50 PPM, ± 25 PPM and ± 20 PPM over Operating Temp. Range  
Operating Temperature Range 0 to +80°C is standard, can be extended to - 40 to +85°C  
Operable Supply Voltage (Vcc) 3.3 V ± 5%  
High Level Output Voltage  
Low Level Output Voltage  
1.43 V typical and 1.60 V maximum with output enabled (100 ohm load, R1 = 50 ohms) See Test circuit #6  
0.90 V minimum and 1.10 V typical with output enabled (same conditions as above)  
Differential Output Voltage  
Differential Output Error  
Offset Voltage  
Offset Voltage Error  
Output Leakage Current  
Supply Current (Icc)  
Symmetry (DC1)  
247 mV minimum, 330 mV typical and 454 mV maximum with output enabled (same conditions as above)  
50 mV maximum with output enabled (same conditions as above)  
1.125 V minimum, 1.25 V typical and 1.375 V maximum with output enabled (same as above)  
50 mV maximum with output enabled (same as above)  
100 uA maximum with output disabled  
70 mA maximum  
47/53% measured at crossing point  
Symmetry (DC2)  
47/53% measured at 50% of output swing  
Rise and Fall Time (Tr & Tf)  
RMS Jitter  
1.5 nS max at 20% to 80% output swing (100 ohm load) See Test circuit #6 and Waveform #2  
1.0 pS max at12 kHz to 20 MHz from the output  
Start Time  
5.0 mS maximum  
Enable / Disable Pin:  
The Enable / Disable pin has an internal pull up and if the pin is not connected the oscilaltor is enabled. Pletronics strongly recommends  
connecting the Enable / Disable pin to Vcc, if the oscillator is to be enabled at all times. In the disable condition, the output becomes a  
high impedance and the internal oscillator circuit is inhibited (the internal circuit is stopped).  
High Level Input Voltage  
Low Level Input Voltage  
High Level Input Current  
Low Level Input Current  
Output Enable Time  
2.0 V minimum at Enable / Disable Pin  
0.8 V maximum at Enable / Disable Pin  
±10 uA maximum at Enable / Disable  
±50 uA maximum at Enable / Disable  
200 nS maximum  
Output Disable Time  
200 nS maximum  
Part Numbering Guide  
Portions of the part number that appear after the frequency may not be marked on part (C of C provided)  
LV88 45 D V - 106.25M - XXX (Internal Code or blank)  
Packaging  
Tube or  
16mm tape  
8mm pitch  
Model  
Frequency in MHz  
Special Specifications (choose all that apply)  
E: Extended Operating Temp Range (-40 to +85°C) ,Optional  
V: Supply Voltage of 3.3 volts ±5% (Required)  
Frequency Stability  
45 = ± 50 PPM  
44 = ± 25 PPM  
20 = ± 20 PPM  
Consult factory for available frequencies and specs. Not all options available for all frequencies. A special part number may be assigned.  
Frequency Stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration and load  
July 2004  
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com  
TBD  
Pl tronics, Inc.  
Pl tronics, Inc.  
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA  
Manufacturer of High Quality Frequency Control Products  
LV8845D LVDS Series  
Mechanical: inches (mm)  
not to scale  
Solder Pads  
Due to part size and factory abilities, part marking may vary from lot to lot and may contain our part number or an internal code.  
0.200 (5.08)  
0.276 (7.0 ± .15)  
0.004 (0.10)  
0.050 (1.27)  
5
2
6
1
4
3
5
2
4
3
6
1
0 .087 (2.2)  
0 .079 (2.0)  
0.055  
(1.4)  
0.024  
(0.60)  
0.075 (1.9)  
MAX  
0.200 (5.08)  
0 .055  
(1.4)  
PIN SIGNAL  
1
2
3
4
5
6
E/D  
N.C.  
GND  
VoD+  
VoD-  
Vcc  
See page 6 for Layout Guidelines  
Mar 2004  
4A  
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com  
Pl tronics, Inc.  
Pl tronics, Inc.  
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA  
Manufacturer of High Quality Frequency Control Products  
PECL and LVDS Layout Guidelines  
'B Pkg'  
5 x7  
SUGGESTED PCB LAYOUTS  
Solder Pad Layout which  
accommodates all PECL surface mount  
devices  
TOP SIDE  
BYPASS  
0.200 (5.08)  
0 .185  
(4.7)  
0 .087  
(2.2)  
BOTTOM  
SIDE  
BYPASS  
0.055 0.100  
(1.4) (2.54)  
The output line should be designed with proper characteristic  
impedance. Pletronics recommends laying out for the larger  
'B package' with pads long enough to accept the smaller  
5 x 7mm device. This permits the best option for alternate  
sources of device. Pletronics also recommends connecting  
Pin 1 and Pin 2 together on the models with  
MULTI  
LAYER  
BYPASS  
Q & QN OUT on pins 4 & 5. This allows  
having E/D on either pin 1 or pin 2.  
For Optimum Jitter Performance, Pletronics recommends:  
A ground plane under the device with any other signals below the ground plane  
Minimize other RF signals near device  
No large transient signals (both current and voltage) should be routed under the device  
Do not layout near a large magnetic field such as a high frequency switching power supply  
Do not place near piezoelectric buzzers or mechancial fans  
Reflow Cycle for lead free processing  
260°C max  
10 Seconds max  
250  
200  
150  
100  
175°C ± 10°C  
120 to 160 Seconds  
215°C ± 10°C  
50 Seconds  
T Rise= 4 Degree/second max  
Mar 2004  
6
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com  
Pl tronics, Inc.  
Pl tronics, Inc.  
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA  
Manufacturer of High Quality Frequency Control Products  
PECL and LVDS Layout Guidelines Continued  
PECL Terminations:  
Suggested Terminations for 50 ohm impedance matched termination  
Vcc  
Vcc  
Thevenin Equivalent Termination  
R1  
Vcc  
5.0 V  
R1  
82 ohm  
R2  
130 ohm  
82 ohm  
Vcc  
Oscillator  
Vcc  
Out  
Out  
Oscillator  
3.3 V 130 ohm  
2.5 V 249 ohm 61.9 ohm  
GND  
R2  
50 ohm  
GND  
Vcc - 2.00 V  
Simple termination for NON impedance matched termination  
Vcc  
Vcc  
R load  
274 ohm  
147 ohm  
86.6 ohm  
Vcc  
Oscillator  
Out  
5.0 V  
3.3 V  
2.5 V  
GND  
R load  
LVDS Terminations:  
Vcc  
Vcc  
Oscillator  
QN Out  
Q Out  
Design PCB traces for 50 ohm characteristic impedance  
100 ohm  
GND  
Mixed System Power Supply:  
To use multiple supply voltages requires level translation. Direct circuit connection is not valid.  
PECL  
Mixed supply voltages are allowed. No translation is necessary. (ECL is returned to the most positive  
supply and this is common to all circuits)  
ECL  
Mixed supply voltages are allowed. LVDS signal levels are power supply independent.  
3.3 V LVDS oscillators properly interface 2.5 V Logic Arrays for example.  
LVDS  
Mar 2004  
6A  
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com  
Pl tronics, Inc.  

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