PE1144MFV-170.0M [PLETRONICS]

Oscillator, 10MHz Min, 170MHz Max, 170MHz Nom;
PE1144MFV-170.0M
型号: PE1144MFV-170.0M
厂家: PLETRONICS, INC.    PLETRONICS, INC.
描述:

Oscillator, 10MHz Min, 170MHz Max, 170MHz Nom

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Pl tronics, Inc.  
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA  
Manufacturer of High Quality Frequency Control Products  
Differential PECL Series  
Differential PECL Output, Some with Enable/ Disable Function  
Available in 9 Different Package/Configurations, See Next Pages  
Standard Specifications  
Overall Frequency Stability  
± 50 PPM, ± 25 PPM, ± 20 PPM over Operating Temperature Range  
Operating Temperature Range 0 to +80°C is standard, but can be extended to - 40 to +85°C  
Storage Temperature Range  
Supply Voltage (Vcc)  
Supply Current (Icc)  
- 55 to +125°C  
3.3 volts ± 5% standard, but 5.0 volts or 2.5 volts also available. See Test Cirucit 5.  
< 250 MHz = 90 mA maximum, 250 MHz and above = 100 mA maximum  
Output High Level  
2.275 V minimum referenced to Ground, Vcc = 3.300V,  
0.975 V minimum referenced to termination voltage,  
- 1.025 V minimum referenced to Vcc  
Output Low Level  
1.680 V maximum referenced to Ground, Vcc = 3.300V,  
0.380 V maximum referenced to termination voltage,  
- 1.620 V maximum referenced to Vcc  
Output Symmetry  
Output Rise & Fall (Tr & Tf)  
Jitter  
E/D Internal Pullup  
V disable  
45/55% referenced to 50% of amplitude  
1.0 nS maximum when Vth is 10% and 90% of waveform  
1 pS RMS maximum measured from 12 kHz to 20 MHz from Fnominal  
50 kohm minimum to Vcc  
0.3 Vcc maximum referenced to Ground  
V enable  
0.7 Vcc minumum referenced to Ground  
PE7745D only Output Enable / Disable  
High Level Input Current  
Low Level Input Current  
Output Enable Time  
-20 uA maximum at Enable / Disable Pin = 0.7 Vcc  
-200 uA maximum at Enable / Disable Pin = 0 V  
200 nS maximum at output enable or 1 mS maximum at output enabled and stable  
200 nS maximum at output disable  
Output Disable Time  
Vcc Supply Current disabled < 1 mA. Both outputs are high impedance when disabled.  
All other models Output Enable/Disable (E/D)  
Output Enable Time  
Output Disable Time  
When Disabled  
100 nS maximum  
100 nS maximum  
Q Output = Logic Low, QN Output = Logic High. Both Outputs are active  
Note 1:  
PECL and ECL are identical circuits.  
ECL has the most positive pin as ground and is ideally terminated by 50 ohms to - 2.00 V  
PECL has the most negative pin as ground and is ideally terminated by 50 ohms to the most (positive voltage less 2.00 V)  
Mechanical: See Next Pages  
D Package  
J Package Replacement  
B Package  
M Package  
Mar 2004  
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com  
1
Pl tronics, Inc.  
Pl tronics, Inc.  
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA  
Manufacturer of High Quality Frequency Control Products  
PE1145M PECL Series  
Differential PECL Output without Enable/ Disable Function  
4 Lead Full Size (14 Pin DIP) Metal Clock Oscillator  
10.00 MHz  
170.00 MHz  
Part Numbering Guide  
Portions of the part number that appear after the frequency may not be marked on part (C of C provided)  
PE11 45 M V - 70.0M - XXX (Internal Code or blank)  
Model Series  
Frequency in MHz  
Special Specifications (choose all that apply)  
Frequency Stability  
°
Packaging  
Tube  
E: Extended Operating Temperature Range (- 40 to +85 C)  
F: 47.5 /52.5% Symmetry at 50% of Vcc  
V: Supply Voltage of 3.3 volts ± 10%  
W: Supply Voltage of 2.5 volts ± 5%  
Y: Supply Voltage of 5.0 volts ± 10%  
45 = ± 50 PPM  
44 = ± 25 PPM  
20 = ± 20 PPM  
Consult factory for available frequencies and specs. Not all options available for all frequencies. A special part number may be assigned.  
Frequency Stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration and load  
Mechanical: inches (mm)  
not to scale  
Due to part size and factory abilities, part marking may vary from lot to lot and may contain our part number or an internal code.  
.200 (5.08) MAX  
.600 (15.24)  
.807 (20.5) MAX  
.031 (0.8)  
8
7
14  
.020  
(.51)  
1
.250 (6.35) MAX  
PIN SIGNAL  
1
7
8
E/D  
GND  
OUT  
Vcc  
See page 6 for Layout Guidelines  
14  
Mar 2004  
3A  
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com  
Pl tronics, Inc.  
Pl tronics, Inc.  
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA  
Manufacturer of High Quality Frequency Control Products  
PECL and LVDS Layout Guidelines  
'B Pkg'  
5 x7  
SUGGESTED PCB LAYOUTS  
Solder Pad Layout which  
accommodates all PECL surface mount  
devices  
TOP SIDE  
BYPASS  
0.200 (5.08)  
0 .185  
(4.7)  
0 .087  
(2.2)  
BOTTOM  
SIDE  
BYPASS  
0.055 0.100  
(1.4) (2.54)  
The output line should be designed with proper characteristic  
impedance. Pletronics recommends laying out for the larger  
'B package' with pads long enough to accept the smaller  
5 x 7mm device. This permits the best option for alternate  
sources of device. Pletronics also recommends connecting  
Pin 1 and Pin 2 together on the models with  
MULTI  
LAYER  
BYPASS  
Q & QN OUT on pins 4 & 5. This allows  
having E/D on either pin 1 or pin 2.  
For Optimum Jitter Performance, Pletronics recommends:  
A ground plane under the device with any other signals below the ground plane  
Minimize other RF signals near device  
No large transient signals (both current and voltage) should be routed under the device  
Do not layout near a large magnetic field such as a high frequency switching power supply  
Do not place near piezoelectric buzzers or mechancial fans  
Reflow Cycle for lead free processing  
260°C max  
10 Seconds max  
250  
200  
150  
100  
175°C ± 10°C  
120 to 160 Seconds  
215°C ± 10°C  
50 Seconds  
T Rise= 4 Degree/second max  
Mar 2004  
6
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com  
Pl tronics, Inc.  
Pl tronics, Inc.  
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA  
Manufacturer of High Quality Frequency Control Products  
PECL and LVDS Layout Guidelines Continued  
PECL Terminations:  
Suggested Terminations for 50 ohm impedance matched termination  
Vcc  
Vcc  
Thevenin Equivalent Termination  
R1  
Vcc  
5.0 V  
R1  
82 ohm  
R2  
130 ohm  
82 ohm  
Vcc  
Oscillator  
Vcc  
Out  
Out  
Oscillator  
3.3 V 130 ohm  
2.5 V 249 ohm 61.9 ohm  
GND  
R2  
50 ohm  
GND  
Vcc - 2.00 V  
Simple termination for NON impedance matched termination  
Vcc  
Vcc  
R load  
274 ohm  
147 ohm  
86.6 ohm  
Vcc  
Oscillator  
Out  
5.0 V  
3.3 V  
2.5 V  
GND  
R load  
LVDS Terminations:  
Vcc  
Vcc  
Oscillator  
QN Out  
Q Out  
Design PCB traces for 50 ohm characteristic impedance  
100 ohm  
GND  
Mixed System Power Supply:  
To use multiple supply voltages requires level translation. Direct circuit connection is not valid.  
PECL  
Mixed supply voltages are allowed. No translation is necessary. (ECL is returned to the most positive  
supply and this is common to all circuits)  
ECL  
Mixed supply voltages are allowed. LVDS signal levels are power supply independent.  
3.3 V LVDS oscillators properly interface 2.5 V Logic Arrays for example.  
LVDS  
Mar 2004  
6A  
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com  
Pl tronics, Inc.  

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