PL560-09OCL中文资料_数据手册_规格书

Analog Frequency Multiplier

PL560-xx VCXO Family

PRODUCT DESCRIPTION

FEATURES

•ꢀNonꢁPLLꢀfrequencyꢀmultiplicationꢀ

•ꢀInputꢀfrequencyꢀfromꢀ30ꢁ200ꢀMHzꢀꢀ

•ꢀOutputꢀfrequencyꢀfromꢀ60ꢁ800ꢀMHzꢀꢀ

•ꢀLowꢀphaseꢀnoiseꢀandꢀjitterꢀ(equivalentꢀtoꢀfundamentalꢀ

crystalꢀatꢀtheꢀoutputꢀfrequency)ꢀ

PhaseLink’sꢀAnalogꢀFrequencyꢀMultiplier^TMꢀ(AFM)ꢀisꢀ

theꢀindustry’sꢀfirstꢀ‘BalancedꢀOscillator’ꢀutilizingꢀ

analogꢀmultiplicationꢀofꢀtheꢀfundamentalꢀfrequencyꢀ

(atꢀdoubleꢀorꢀquadrupleꢀfrequency),ꢀcombinedꢀwithꢀ

anꢀattenuationꢀofꢀtheꢀfundamentalꢀofꢀtheꢀreferenceꢀ

crystal,ꢀwithoutꢀtheꢀuseꢀofꢀaꢀphaseꢁlockedꢀloopꢀ

(PLL),ꢀinꢀCMOSꢀtechnology.ꢀ

•ꢀUltraꢁlowꢀjitterꢀ

oꢀRMSꢀphaseꢀjitterꢀ<ꢀ0.25ꢀpsꢀ(12kHzꢁ20MHz)ꢀ

oꢀRMSꢀperiodꢀjitterꢀ<ꢀ2.5ꢀpsꢀ

ꢀ

•ꢀLowꢀphaseꢀnoiseꢀ

PhaseLink’sꢀpatentꢀpendingꢀPL560ꢁxxꢀfamilyꢀofꢀAFMꢀ

productsꢀcanꢀachieveꢀupꢀtoꢀ800ꢀMHzꢀoutputꢀ

frequencyꢀwithꢀlittleꢀjitterꢀorꢀphaseꢀnoiseꢀ

deterioration.ꢀꢀInꢀaddition,ꢀtheꢀlowꢀfrequencyꢀinputꢀ

crystalꢀrequirementꢀmakesꢀtheꢀAFMsꢀtheꢀmostꢀ

affordableꢀhighꢁperformanceꢀtimingꢁsourceꢀinꢀtheꢀ

market.ꢀ

oꢀꢁ142ꢀdBc/Hzꢀ@100kHzꢀoffsetꢀfromꢀ155.52ꢀMHzꢀ

oꢀꢁ150ꢀdBc/Hzꢀ@10MHzꢀoffsetꢀfromꢀ155.52ꢀMHzꢀ

•ꢀHighꢀlinearityꢀpullꢀrangeꢀ(typ.ꢀ5%)ꢀ

•ꢀ+/ꢁꢀ120ꢀPPMꢀpullabilityꢀVCXOꢀ

•ꢀLowꢀinputꢀfrequencyꢀeliminatesꢀtheꢀneedꢀforꢀexpensiveꢀ

crystalsꢀ

•ꢀDifferentialꢀoutputꢀlevelsꢀ(PECL,ꢀLVDS),ꢀorꢀsingleꢁ

endedꢀCMOSꢀꢀ

•ꢀSingleꢀ2.5Vꢀorꢀ3.3Vꢀ+/ꢁꢀ10%ꢀpowerꢀsupplyꢀ

•ꢀOptionalꢀindustrialꢀtemperatureꢀrangeꢀ(ꢁ40°Cꢀtoꢀ+85°C)ꢀꢀ

•ꢀAvailableꢀinꢀ16ꢁpinꢀGREEN/RoHSꢀcompliantꢀTSSOP,ꢀ

andꢀ3x3ꢀQFNꢀ

ꢀ

PL560ꢁxxꢀfamilyꢀofꢀproductsꢀutilizeꢀlowꢁpowerꢀCMOSꢀ

technologyꢀandꢀareꢀhousedꢀinꢀGREEN/ RoHSꢀ

compliantꢀ16ꢁpinꢀTSSOP,ꢀandꢀ16ꢁpinꢀ3x3ꢀQFNꢀ

packages.ꢀꢀꢀꢀ

ꢀ

Figure 1: 2x AFM Phase Noise at 311.04MHz

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCaliforniaꢀ94538ꢀꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀwww.phaselink.com Rev.ꢀ02/09/07ꢀPageꢀ1ꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

L 2 X

V C O N

O E

X IN

Q B A R

Q

F re q u e n c y

X 2

F re q u e n c y

X 4

O s c illa to rꢀ

A m p lifie rꢀ

X O U T

O n ly ꢀre q u ire d ꢀin ꢀx 4 ꢀd e s ig n s

L 4 X

ꢀ

Figure 2: Block Diagram of VCXO AFM

ꢀ

Figureꢀ3ꢀshowsꢀtheꢀperiodꢀjitterꢀhistogramꢀofꢀtheꢀ2xꢀAnalogꢀFrequencyꢀMultiplierꢀatꢀ311.04ꢀMHz,ꢀwhileꢀFigureꢀ4ꢀshowsꢀtheꢀveryꢀ

lowꢀrejectionꢀlevelsꢀofꢀsubꢁharmonicsꢀthatꢀcorrespondꢀtoꢀtheꢀexceptionallyꢀlowꢀjitterꢀperformance.ꢀ

ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ

Figure 3: Period Jitter Histogram at 311.04 MHz

Analog Frequency Multiplier (2x)

with 155.52MHz crystal

Figure 4: Spectrum Analysis at 311.04 MHz

Analog Frequency Multiplier (2x)

with sub-harmonics below –72 dBc

OE LOGIC SELECTION

OUTPUT

OESEL

OE

Output State

0ꢀ(Default)ꢀ

Enabledꢀ

Triꢁstateꢀ

Enabledꢀ

Triꢁstateꢀ

Enabledꢀ

Triꢁstateꢀ

0ꢀ(Default)ꢀ

1ꢀ

PECLꢀ

0ꢀ

1ꢀ

0ꢀ(Default)ꢀ

1ꢀ

1ꢀ(Default)ꢀ

0ꢀ

1ꢀ(Default)ꢀ

0ꢀ(Default)ꢀ

1ꢀ

LVDSꢀorꢀCMOSꢀ

OESELꢀandꢀOE:ꢀConnectꢀtoꢀVDDꢀtoꢀsetꢀtoꢀ“1”,ꢀconnectꢀtoꢀGNDꢀtoꢀsetꢀtoꢀ“0”.ꢀInternallyꢀsetꢀtoꢀdefaultꢀthroughꢀpullꢁdownꢀ/ꢀꢁup.

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ2ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

PRODUCT SELECTION GUIDE

FREQUENCY VERSUS PHASE NOISE PERFORMANCE

Phase Noise at Frequency Offset From Carrier (dBc/Hz)

Analog

Frequency

Multiplication

Factor

Input

Frequency

Range (MHz)

Output

Frequency

Range (MHz)

Part

Number

Output

Type

Carrier

Freq.

10

KHz

100

KHz

10

10 Hz 100 Hz

1 KHz

1 MHz

MHz

(MHz)

PL560ꢁ08ꢀ

PL560ꢁ09ꢀ

PL560ꢁ37ꢀ

PL560ꢁ38ꢀ

PL560ꢁ39ꢀ

PL560ꢁ47ꢀ

PL560ꢁ48ꢀ

PL560ꢁ49ꢀ

PL560ꢁ68ꢀ

PL560ꢁ69ꢀ

75ꢀꢁꢀ200ꢀ

30ꢀꢁꢀ80ꢀ

75ꢀꢁꢀ200ꢀ

4ꢀ

2ꢀ

300ꢀꢁꢀ800ꢀ

120ꢀꢁꢀ320ꢀ

60ꢀꢁꢀ160ꢀ

150ꢀꢁꢀ400ꢀ

PECLꢀ

LVDSꢀ

622.08ꢀ

ꢁ55ꢀ

ꢁ50ꢀ

ꢁ65ꢀ

ꢁ60ꢀ

ꢁ85ꢀ

ꢁ82ꢀ

ꢁ95ꢀ

ꢁ85ꢀ

ꢁ110ꢀ

ꢁ122ꢀ

ꢁ112ꢀ

ꢁ130ꢀ

ꢁ128ꢀ

ꢁ138ꢀ

ꢁ135ꢀ

ꢁ137ꢀ

ꢁ142ꢀ

ꢁ148ꢀ

ꢁ150ꢀ

ꢁ149ꢀ

ꢁ151ꢀ

CMOSꢀ 155.52ꢀ

PECLꢀ

LVDSꢀ

155.52ꢀ

CMOSꢀ 155.52ꢀ

PECLꢀ

LVDSꢀ

PECLꢀ

LVDSꢀ

155.52ꢀ

311.04ꢀ

PhaseꢀnoiseꢀwasꢀmeasuredꢀusingꢀAgilentꢀE5500.ꢀ

FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE

RMS Period

Jitter

Peak to Peak

Period Jitter

(ps)

RMS Phase Jitter

(12 KHz-20MHz)

(ps)

RMS Accumulated

(L.T.) Jitter (ps)

Spectral Specifications / Sub-harmonic Content

(dBc), Frequency (MHz)

Output.

Freq.

(MHz)

(ps)

Part

Number

Carrier

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Freq. -75%

(Fc) (Fc)

@

-50% -25% +25% +50% +75%

(Fc) (Fc) (Fc) (Fc) (Fc)

PL560ꢁ08ꢀ

PL560ꢁ09ꢀ

PL560ꢁ37ꢀ

PL560ꢁ38ꢀ

PL560ꢁ39ꢀ

PL560ꢁ47ꢀ

PL560ꢁ48ꢀ

PL560ꢁ49ꢀ

PL560ꢁ68ꢀ

PL560ꢁ69ꢀ

622ꢀ

155ꢀ

311ꢀ

ꢀ

4ꢀ

6ꢀ

3ꢀ

ꢀ

25ꢀ 30ꢀ

18ꢀ 20ꢀ

ꢀ

6ꢀ

3ꢀ

ꢀ

0.09ꢀ

0.25ꢀ

0.27ꢀ

0.18ꢀ

ꢀ

622ꢀ ꢁ50ꢀ ꢁ50ꢀ

155.52ꢀ ꢁ75ꢀ ꢁ62ꢀ

ꢁ45ꢀ

ꢁ47ꢀ

ꢁ55ꢀ

4ꢀ

ꢁ45ꢀ

ꢁ47ꢀ

ꢁ47ꢀ ꢁ55ꢀ

ꢁ65ꢀ ꢁ75ꢀ

2.5ꢀ

ꢀ

155.52ꢀ

311.04ꢀ

ꢀ

ꢁ68ꢀ

ꢁ72ꢀ

ꢁ68ꢀ

ꢁ85ꢀ

ꢀ

Note: Wavecrestꢀdataꢀ10,000ꢀhits.ꢀNoꢀfilteringꢀwasꢀusedꢀinꢀjitterꢀcalculations.ꢀꢀꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀAgilentꢀ5500ꢀwasꢀusedꢀforꢀphaseꢀjitterꢀmeasurements.ꢀꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀSpectralꢀspecificationsꢀwereꢀobtainedꢀusingꢀAgilentꢀE7401A.ꢀ

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ3ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

CRYSTAL SPECIFICATIONS AND BOARD LAYOUT CONSIDERATIONS

BOARD LAYOUT CONSIDERATIONS

AFM IC

XIN (Pin # 4)

XTAL

Ceramic

SMD

XTAL

XOUT (Pin # 5)

Toꢀminimizeꢀparasiticꢀeffects,ꢀandꢀimproveꢀperformance:ꢀ

•ꢀ PlaceꢀtheꢀcrystalꢀasꢀcloseꢀasꢀpossibleꢀtoꢀtheꢀIC.ꢀꢀ

•ꢀ Makeꢀtheꢀboardꢀtracesꢀthatꢀareꢀconnectedꢀtoꢀtheꢀcrystalꢀpinsꢀsymmetrical.ꢀꢀꢀ

•ꢀ Theꢀboardꢀtraceꢀsymmetryꢀisꢀimportant,ꢀasꢀitꢀreducesꢀtheꢀnegativeꢀparasiticꢀeffectsꢀtoꢀproduceꢀaꢀcleanꢀfrequencyꢀmultiplicationꢀwithꢀ

lowꢀjitter.ꢀꢀParasiticꢀeffectsꢀreduceꢀfrequencyꢀpullingꢀofꢀtheꢀVCXOꢀandꢀincreaseꢀjitter.ꢀ

CRYSTAL SPECIFICATIONS & TUNING PERFORMANCE

CRYSTAL SPECIFICATIONS

TUNING PERFORMANCE

ESR

(R_E)

CRYSTAL

RESONATOR

FREQUENCY

(FXIN)

CL (xtal)

CRYSTAL

TUNING (Typical)

PART

NUMBER

MODE

CRYSTAL

FREQ

(MHz)

ꢀ

VC:

CONDI-

TYP.

Max.

C0

C1

C0/C1

VC:

TIONS

1.65V

0V

1.65V 3.4V

Atꢀꢀ

VCONꢀ

=ꢀ

155.52ꢀ

30.72ꢀ

38.88ꢀ

77.76ꢀ

3.0pFꢀ

1.8pFꢀ

2.8pFꢀ

4.5pFꢀ

5.1pFꢀ

5.3pFꢀ

2.0pFꢀ

12.2fFꢀ

5.7fFꢀ

245ꢀ

316ꢀ

228ꢀ

236ꢀ

242ꢀ

207ꢀ

305ꢀ

ꢀꢁ145ꢀppmꢀ

ꢀꢁ134ꢀppmꢀ

ꢀꢁ167ppmꢀ

ꢀꢁ163ꢀppmꢀ

ꢀꢁ131ꢀppmꢀ

ꢀꢁ157ꢀppmꢀ

ꢀꢁ92ꢀppmꢀ

ꢀ+108ꢀppmꢀ

ꢀ+87ꢀppmꢀ

ꢀ+176ꢀppmꢀ

ꢀ+167ꢀppmꢀ

ꢀ+98ꢀppmꢀ

ꢀ+141ꢀppmꢀ

ꢀ+110ꢀppmꢀ

PL560ꢁ08/09ꢀ

PL560ꢁ68/69ꢀ

Fundaꢁꢀ

mentalꢀ

75~200MHzꢀ

5pFꢀ

30 ꢀ

1.65Vꢀ

12.4fFꢀ

19.1fFꢀ

20.9fFꢀ

25.6fFꢀ

6.7fFꢀ

PL560ꢁ

37/38/39ꢀ

PL560ꢁ

47/48/49ꢀ

Atꢀꢀ

VCONꢀ

=ꢀꢀ

Fundaꢁꢀ

mentalꢀ

30~80MHzꢀ

5pFꢀ

30 ꢀ

1.65Vꢀ

Note: Non specified parameters can be chosen as standard values from crystal suppliers.

CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink.

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ4ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

VOLTAGE CONTROL SPECIFICATION

PARAMETERS

VCXOꢀStabilizationꢀTimeꢀ

VCXOꢀTuningꢀRangeꢀ

SYMBOL

CONDITIONS

Fromꢀpowerꢀvalidꢀ

MIN.

ꢀꢀ

TYP.

MAX.

UNITS

msꢀ

T_VCXOSTB

ꢀ

ꢀ10ꢀ

ꢀ

XTALꢀC₀ꢀ/C_1ꢀꢀ<300ꢀ

200ꢀ

ppmꢀ

ꢀ

VCON=ꢀ1.65Vꢀ±ꢀ1.65Vꢀ

XTALꢀC₀ꢀ/C_1ꢀꢀ<300ꢀ

CLKꢀOutputꢀPullabilityꢀ

ꢀ

±100ꢀ

±120ꢀ

ꢀ

ppmꢀ

Linearityꢀ

ꢀꢀ

_ꢀꢀ

ꢀꢀ

5ꢀ

ꢀꢀ

10ꢀ

ꢀ

%ꢀ

kꢀ

VCONꢀInputꢀImpedanceꢀ

VCONꢀModulationꢀBWꢀ

ꢀꢀ

130ꢀ

25ꢀ

0Vꢀ<ꢀVCONꢀ<ꢀ3.3V,ꢀꢁ3dBꢀ

ꢀꢀ

kHzꢀ

EXTERNAL COMPONENT VALUES

INDUCTOR VALUE OPTIMIZATION

ꢀ

Theꢀrequiredꢀinductorꢀvalue(s)ꢀforꢀtheꢀbestꢀperformanceꢀdependsꢀonꢀtheꢀoperatingꢀfrequency,ꢀandꢀtheꢀboardꢀ

layoutꢀspecifications.ꢀꢀTheꢀlistedꢀvaluesꢀinꢀthisꢀdatasheetꢀareꢀbasedꢀonꢀtheꢀcalculatedꢀparasiticꢀvaluesꢀfromꢀ

PhaseLink’sꢀevaluationꢀboardꢀdesign.ꢀꢀTheseꢀinductorꢀvaluesꢀprovideꢀtheꢀuserꢀwithꢀaꢀstartingꢀpointꢀtoꢀdetermineꢀ

theꢀoptimumꢀinductorꢀvalues.ꢀꢀAdditionalꢀfineꢁtuningꢀmayꢀbeꢀrequiredꢀtoꢀdetermineꢀtheꢀoptimalꢀsolution.ꢀꢀꢀ

ꢀ

Toꢀassistꢀwithꢀtheꢀinductorꢀvalueꢀoptimization,ꢀPhaseLinkꢀhasꢀdevelopedꢀtheꢀ“AFMꢀTuningꢀAssistant”ꢀsoftware.ꢀꢀ

YouꢀcanꢀdownloadꢀthisꢀsoftwareꢀfromꢀPhaseLink’sꢀwebꢀsiteꢀ(www.phaselink.com).ꢀꢀTheꢀsoftwareꢀconsistsꢀofꢀtwoꢀ

worksheets.ꢀꢀTheꢀfirstꢀworksheetꢀ(namedꢀL2)ꢀisꢀusedꢀtoꢀfineꢁtuneꢀtheꢀ‘L2’ꢀinductorꢀvalue,ꢀandꢀtheꢀsecondꢀ

worksheetꢀ(namedꢀL4)ꢀisꢀusedꢀforꢀfineꢀtuningꢀofꢀtheꢀ‘L4’ꢀ(usedꢀinꢀ4xꢀAFMsꢀonly)ꢀinductorꢀvalue.ꢀꢀꢀ

ꢀ

ForꢀthoseꢀdesignsꢀusingꢀPhaseLink’sꢀrecommendedꢀboardꢀlayout,ꢀyouꢀcanꢀuseꢀtheꢀ“AFMꢀTuningꢀAssistant”ꢀtoꢀ

determineꢀtheꢀoptimumꢀvaluesꢀforꢀtheꢀrequiredꢀinductors.ꢀꢀThisꢀsoftwareꢀisꢀdevelopedꢀbasedꢀonꢀtheꢀparasiticꢀ

informationꢀfromꢀPhaseLink’sꢀboardꢀlayoutꢀandꢀcanꢀbeꢀusedꢀtoꢀdetermineꢀtheꢀrequiredꢀinductorꢀandꢀparallelꢀ

capacitorꢀ(seeꢀLWB1ꢀandꢀCstrayꢀparameters)ꢀvalues.ꢀꢀForꢀthoseꢀemployingꢀaꢀdifferentꢀboardꢀlayoutꢀinꢀtheirꢀ

design,ꢀweꢀrecommendꢀtoꢀuseꢀtheꢀparasiticꢀinformationꢀofꢀtheirꢀboardꢀlayoutꢀtoꢀcalculateꢀtheꢀoptimizedꢀinductorꢀ

values.ꢀꢀPleaseꢀuseꢀtheꢀfollowingꢀfineꢀtuningꢀprocedure:ꢀꢀ

ꢀ

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ5ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

Figure 5: Diagram Representation of the Related System Inductance and Capacitance

DIE SIDE

ꢁꢀCinternalꢀ=ꢀBasedꢀonꢀAFMꢀdeviceꢀ

ꢁꢀCpadꢀ=ꢀ2.0ꢀpF,ꢀBondꢀpadꢀandꢀitsꢀESDꢀcircuitryꢀꢀ

ꢁꢀC11ꢀ=ꢀ0.4ꢀpF,ꢀTheꢀfollowingꢀamplifierꢀstageꢀ

PCB side

ꢀ

ꢁꢀLWB1ꢀ=ꢀ2ꢀnH,ꢀ(2ꢀplaces),ꢀStrayꢀinductanceꢀ

ꢁꢀCstrayꢀ=ꢀ1.0ꢀpF,ꢀStrayꢀcapacitanceꢀ

ꢁꢀL2Xꢀ(L4X)ꢀ=ꢀ2xꢀorꢀ4xꢀinductorꢀ

ꢁꢀC2Xꢀ(C4X)ꢀ=ꢀrangeꢀ(0.1ꢀtoꢀ2.7ꢀpF),ꢀFineꢀtuneꢀꢀꢀꢀ

ꢀꢀinductorꢀifꢀusedꢀ

ꢀ

•ꢀThereꢀareꢀtwoꢀdefaultꢀvariablesꢀthatꢀnormallyꢀwillꢀnotꢀneedꢀtoꢀbeꢀmodified.ꢀꢀTheseꢀareꢀCpad,ꢀandꢀC11ꢀandꢀ

areꢀfoundꢀinꢀcellsꢀB22ꢀandꢀB27ꢀofꢀ‘AFMꢀTuningꢀAssistant’,ꢀrespectively.ꢀ

•ꢀLWB1ꢀisꢀtheꢀcombinedꢀstrayꢀinductanceꢀinꢀtheꢀlayout.ꢀꢀTheꢀDIEꢀwireꢀbondꢀisꢀ~ꢀ0.6ꢀnHꢀandꢀinꢀtheꢀcaseꢀofꢀaꢀ

leadedꢀpartꢀanꢀadditionalꢀ1.0ꢀnHꢀisꢀadded.ꢀꢀYourꢀlayoutꢀinductanceꢀmustꢀbeꢀaddedꢀtoꢀthese.ꢀꢀThereꢀareꢀ2ꢀofꢀ

theseꢀandꢀtheyꢀareꢀassumedꢀtoꢀbeꢀapproximatelyꢀsymmetricalꢀsoꢀyouꢀonlyꢀneedꢀtoꢀenterꢀthisꢀinductanceꢀ

onceꢀinꢀcellꢀB23.ꢀ

•ꢀEnterꢀtheꢀstrayꢀparasiticꢀcapacitanceꢀintoꢀcellꢀB26.ꢀꢀAnꢀadditionalꢀ0.5ꢀpFꢀmustꢀbeꢀaddedꢀtoꢀthisꢀvalueꢀifꢀaꢀ

leadedꢀpartꢀisꢀused.ꢀ

•ꢀEnterꢀtheꢀappropriateꢀvalueꢀforꢀCinternalꢀintoꢀB21ꢀbasedꢀonꢀtheꢀdeviceꢀusedꢀ(seeꢀcolumnꢀD).ꢀꢀUseꢀtheꢀ‘AFMꢀ

TuningꢀAssistant’ꢀsoftwareꢀtoꢀcalculateꢀL2Xꢀ(andꢀC2Xꢀifꢀused)ꢀforꢀyourꢀresonanceꢀfrequency.ꢀ

•ꢀForꢀ4XꢀAFMs,ꢀrepeatꢀtheꢀsameꢀprocedureꢀinꢀtheꢀL4Xꢀworksheet.ꢀ

•ꢀSeeꢀtheꢀexamplesꢀinꢀtheꢀfollowingꢀsection.ꢀ

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ6ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

DETERMINING STRAY L’s AND C’s IN A LAYOUT

Figure 6: Diagram Representation of the Board Layout

LetsꢀtakeꢀtheꢀPL560ꢁ38ꢀ(4xꢀVCXO)ꢀforꢀexample.ꢀꢀThisꢀtakesꢀaꢀcrystalꢀinputꢀinꢀtheꢀrangeꢀofꢀ30ꢀtoꢀ80ꢀMHzꢀandꢀ

multipliesꢀitꢀtoꢀanꢀoutputꢀofꢀ120ꢀtoꢀ320ꢀMHz.ꢀꢀToꢀdetermineꢀtheꢀstrayꢀL’sꢀandꢀC’sꢀofꢀtheꢀlayoutꢀweꢀwillꢀassembleꢀ

twoꢀtestꢀunits.ꢀꢀOneꢀAFMꢀwillꢀbeꢀtunedꢀtoꢀtheꢀlowerꢀrangeꢀofꢀtheꢀdeviceꢀ(120ꢀMHz),ꢀandꢀtheꢀotherꢀtoꢀtheꢀupperꢀ

rangeꢀofꢀtheꢀdeviceꢀ(320ꢀMHz).ꢀꢀꢀ

ꢀ

120 MHz AFM Tuning:ꢀUsingꢀtheꢀ“AFMꢀTuningꢀAssistant”ꢀfindꢀtheꢀPL560ꢁ3xꢀinꢀtheꢀL2Xꢀworksheet.ꢀꢀEnterꢀtheꢀ

CinternalꢀvalueꢀfoundꢀnextꢀtoꢀitꢀintoꢀcellꢀB21.ꢀꢀInꢀcellꢀB24ꢀenterꢀtheꢀclosestꢀstandardꢀinductorꢀvalueꢀ(seeꢀCoilCraftꢀ

0603CSꢀseriesꢀforꢀexample)ꢀtoꢀachieveꢀtheꢀclosestꢀpeakꢀfrequencyꢀtoꢀ60ꢀMHz.ꢀꢀꢀRepeatꢀtheꢀsameꢀprocedureꢀforꢀ

L4Xꢀatꢀ120ꢀMHz.ꢀꢀꢀ

Results: L2X = 180 nH, L4X = 82 nH.ꢀ

ꢀ

320 MHz AFM tuning:ꢀRepeatꢀtheꢀpreviousꢀprocedureꢀforꢀL2Xꢀatꢀ120ꢀMHzꢀandꢀL4Xꢀatꢀ320ꢀMHz.ꢀ

Results: L2X = 24 nH, L4X = 10 nH.ꢀ

ꢀ

Proceedꢀandꢀassembleꢀtheꢀtestꢀunits.ꢀ

ꢀ

Measuring 120 MHz L2X: ConnectꢀtheꢀRFꢀgeneratorꢀandꢀscopeꢀprobeꢀasꢀshownꢀinꢀFigureꢀ6,ꢀabove.ꢀꢀꢀWhileꢀ

powerꢀisꢀappliedꢀtoꢀtheꢀPCB,ꢀsetꢀtheꢀgeneratorꢀoutputꢀtoꢀ+12ꢀdBmꢀandꢀtheꢀfrequencyꢀtoꢀ30ꢀMHz.ꢀꢀSinceꢀthisꢀisꢀtheꢀ

2xꢀport,ꢀtheꢀscopeꢀwillꢀshowꢀ60ꢀMHzꢀwithꢀ~ꢀ3Vꢀpkꢁpkꢀamplitude.ꢀꢀVaryꢀtheꢀgeneratorꢀaboveꢀandꢀbelowꢀ30ꢀMHzꢀuntilꢀ

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ7ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

theꢀamplitudeꢀonꢀtheꢀscopeꢀisꢀmaximumꢀandꢀrecordꢀtheꢀgeneratorꢀfrequency.ꢀꢀForꢀexample,ꢀtheꢀpeakꢀisꢀrecordedꢀ

atꢀ29.8x2ꢀorꢀ59.6ꢀMHz.ꢀ

ꢀ

Measuring 320 MHz L2X: ConnectꢀtheꢀRFꢀgeneratorꢀandꢀscopeꢀprobeꢀasꢀshownꢀinꢀFigureꢀ6,ꢀabove.ꢀꢀꢀWhileꢀ

powerꢀisꢀappliedꢀtoꢀtheꢀPCB,ꢀsetꢀtheꢀgeneratorꢀoutputꢀtoꢀ+12ꢀdBmꢀandꢀtheꢀfrequencyꢀtoꢀ80ꢀMHz.ꢀꢀSinceꢀthisꢀisꢀtheꢀ

2xꢀportꢀtheꢀscopeꢀwillꢀshowꢀ160ꢀMHzꢀwithꢀ~ꢀ3Vꢀpkꢁpkꢀamplitude.ꢀꢀVaryꢀtheꢀgeneratorꢀaboveꢀandꢀbelowꢀ80ꢀMHzꢀ

untilꢀtheꢀamplitudeꢀonꢀtheꢀscopeꢀisꢀmaximumꢀandꢀrecordꢀtheꢀgeneratorꢀfrequency.ꢀꢀForꢀexample,ꢀtheꢀpeakꢀisꢀ

recordedꢀatꢀ78.0ꢀxꢀ2ꢀ=ꢀ156ꢀMHzꢀ

ꢀ

InꢀtheꢀAFMꢀTuningꢀAssistant,ꢀaddꢀtheꢀscope’sꢀprobeꢀcapacitanceꢀtoꢀtheꢀCstrayꢀcell.ꢀꢀForꢀourꢀexampleꢀ0.5ꢀpFꢀ+ꢀ1.0ꢀ

pFꢀ=ꢀ1.5ꢀpF.ꢀWithꢀL2Xꢀatꢀ24ꢀnHꢀadjustꢀLWB1ꢀ(cellꢀB23)ꢀuntilꢀtheꢀpeakꢀfrequencyꢀreadsꢀ156ꢀMHz.ꢀꢀNextꢀreplaceꢀtheꢀ

L2Xꢀvalueꢀwithꢀ180ꢀnHꢀandꢀseeꢀifꢀitꢀpeaksꢀatꢀ59.6ꢀMHz.ꢀꢀIfꢀitꢀdoesꢀnot,ꢀadjustꢀCstrayꢀuntilꢀ59.4ꢀMHzꢀisꢀachieved.ꢀꢀ

Againꢀenterꢀ24ꢀnHꢀforꢀL2XꢀandꢀfineꢀtuneꢀLWB1ꢀforꢀ156ꢀMHz.ꢀ

Results: LWB1 = 1.6 nH, Cstray = 2.9 pF-0.5 pF = 2.4 pF (subtract scope probe stray capacitance)

RepeatꢀtheꢀsameꢀstepsꢀforꢀtheꢀL4X:ꢀSetꢀtheꢀgeneratorꢀtoꢀ80ꢀMHz.ꢀꢀTheꢀ82ꢀnHꢀpeaksꢀatꢀ118ꢀMHzꢀandꢀtheꢀ10ꢀnHꢀ

peaksꢀatꢀ304ꢀMHz.ꢀ

Results: LWB1 = 1.8 nH, Cstray = 2.5 pF-0.5 pF = 2.0 pF (subtract scope probe stray capacitance)

Internal Capacitor Selection by Device

Cinternal (pF)

Device Number

2X

4X

P560ꢁ0xꢀ

P560ꢁ3xꢀ

P560ꢁ4xꢀ

P560ꢁ6xꢀ

7.625ꢀ

34.125ꢀ

7.625ꢀ

6.250ꢀ

16.500ꢀ

ꢀ

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ8ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

SupplyꢀVoltageꢀꢀ

V_DD

V_Iꢀ

ꢀ

4.6ꢀ

V_DD+0.5ꢀ

150ꢀ

Vꢀ

InputꢀVoltage,ꢀDCꢀ

GNDꢁ0.5ꢀ

OutputꢀVoltage,ꢀDCꢀ

V_Oꢀ

T_Sꢀ

GNDꢁ0.5ꢀ

Vꢀ

StorageꢀTemperatureꢀ

ꢁ65ꢀ

°Cꢀ

kVꢀ

AmbientꢀOperatingꢀTemperature,ꢀIndustrialꢀTemperatureꢀ

AmbientꢀOperatingꢀTemperature,ꢀCommercialꢀTemperatureꢀ

JunctionꢀTemperatureꢀ

T_{A_I}

ꢀ

ꢁ40ꢀ

+85ꢀ

T_{A_C}

ꢀ

0ꢀ

ꢀ

+70ꢀ

T_Jꢀ

125ꢀ

LeadꢀTemperatureꢀ(soldering,ꢀ10s)ꢀ

InputꢀStaticꢀDischargeꢀVoltageꢀProtectionꢀ

ꢀ

260ꢀ

ꢀ

2ꢀ

ExposureꢀofꢀtheꢀdeviceꢀunderꢀconditionsꢀbeyondꢀtheꢀlimitsꢀspecifiedꢀbyꢀMaximumꢀRatingsꢀforꢀextendedꢀperiodsꢀmayꢀcauseꢀpermanentꢀ

damageꢀtoꢀtheꢀdeviceꢀandꢀaffectꢀproductꢀreliability.ꢀꢀTheseꢀconditionsꢀrepresentꢀaꢀstressꢀratingꢀonly,ꢀandꢀfunctionalꢀoperationsꢀofꢀtheꢀ

deviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀtheꢀoperationalꢀlimitsꢀnotedꢀinꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀ

PECL ELECTRICAL CHARACTERISTICS

PARAMETERS

SupplyꢀCurrentꢀ(withꢀloadedꢀoutputs)ꢀ

OperatingꢀVoltageꢀ

SYMBOL CONDITIONS

MIN.

ꢀꢀ

TYP.

75ꢀ

ꢀꢀ

MAX.

80ꢀ

UNITS

mAꢀ

Vꢀ

I_DDꢀ

V_DDꢀ

_ꢀꢀ

Foutꢀ=ꢀ622ꢀMHzꢀ

ꢀ

2.25ꢀ

45ꢀ

3.63ꢀ

55ꢀ

OutputꢀClockꢀDutyꢀCycleꢀ

@ꢀVddꢀ–ꢀ1.3Vꢀ

50ꢀ

%ꢀ

ShortꢀCircuitꢀCurrentꢀ

OutputꢀHighꢀVoltageꢀ

ꢀ

ꢀꢀ

mAꢀ

Vꢀ

±50ꢀ

R_Lꢀ=ꢀ50ꢀꢀꢀtoꢀꢀ

(V_DDꢀ–ꢀ2V)ꢀ

V_OHꢀ

V_DDꢀ–ꢀ1.025ꢀ

ꢀꢀ

OutputꢀLowꢀVoltageꢀ

ClockꢀRiseꢀTimeꢀ

ClockꢀFallꢀTimeꢀ

V_OLꢀ

t_rꢀ

ꢀ

V_DDꢀ–ꢀ1.620ꢀ

0.45ꢀ

Vꢀ

@20/80%ꢀ

@80/20%ꢀ

ꢀꢀ

0.25ꢀ

nsꢀ

t_fꢀ

0.45ꢀ

ꢀ

PECLꢀTransitionꢀTimeꢀWaveform

DUTYꢀCYCLE

PECLꢀLevelsꢀTestꢀCircuit

PECLꢀOutputꢀSkew

45ꢀꢁꢀ55%

55ꢀꢁꢀ45%

OUT

VDD

OUT

80%

50

ꢀ

2.0V

50%

20%

OUT

t_R

t_F

t_SKEW

OUT

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ9ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

LVDS ELECTRICAL CHARACTERISTICS

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

SupplyꢀCurrentꢀ(withꢀloadedꢀoutputs)ꢀ

OperatingꢀVoltageꢀ

I_DDꢀ

V_DDꢀ

_ꢀꢀ

Foutꢀ=ꢀ622ꢀMHzꢀ

ꢀꢀ

55ꢀ

ꢀꢀ

60ꢀ

3.63ꢀ

55ꢀ

mAꢀ

Vꢀ

ꢀꢀ

2.25ꢀ

45ꢀ

OutputꢀClockꢀDutyꢀCycleꢀ

@ꢀ1.25Vꢀ(LVDS)ꢀ

ꢀꢀ

50ꢀ

%ꢀ

ShortꢀCircuitꢀCurrentꢀ

_ꢀꢀ

ꢀꢀ

mAꢀ

mVꢀ

±50ꢀ

355ꢀ

ꢀꢀ

OutputꢀDifferentialꢀVoltageꢀ

VDDꢀMagnitudeꢀChangeꢀ

V_ODꢀ

ꢁV_ODꢀ

V_OHꢀ

247ꢀ

ꢁ50ꢀ

454ꢀ

50ꢀ

OutputꢀHighꢀVoltageꢀ

ꢀꢀ

1.4ꢀ

1.6ꢀ

Vꢀ

R_Lꢀ=ꢀ100ꢀꢂꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

(seeꢀfigure)ꢀ

OutputꢀLowꢀVoltageꢀ

OffsetꢀVoltageꢀ

V_OLꢀ

V_OSꢀ

0.9ꢀ

1.1ꢀ

1.2ꢀ

ꢀꢀ

Vꢀ

1.125ꢀ

1.375ꢀ

OffsetꢀMagnitudeꢀChangeꢀ

PowerꢁoffꢀLeakageꢀ

0ꢀ

ꢀꢀ

3ꢀ

25ꢀ

mVꢀ

ꢂA

ꢁV_OSꢀ

V_outꢀ=ꢀV_DDꢀorꢀGNDꢀꢀꢀꢀꢀ

VDDꢀ=ꢀ0Vꢀ

I_OXD

ꢀ

±1ꢀ

±10ꢀ

OutputꢀShortꢀCircuitꢀCurrentꢀ

DifferentialꢀClockꢀRiseꢀTimeꢀ

I_OSD

t_rꢀ

ꢀꢀ

ꢁ5.7ꢀ

0.5ꢀ

ꢁ8ꢀ

mAꢀ

nsꢀ

R_Lꢀ=ꢀ100ꢀꢃꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀCLꢀ=ꢀ10ꢀpFꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

(seeꢀfigure)ꢀ

0.2ꢀ

0.7ꢀ

DifferentialꢀClockꢀFallꢀTimeꢀ

t_fꢀ

0.2ꢀ

0.5ꢀ

0.7ꢀ

nsꢀ

LVDSꢀTransitionꢀTimeꢀWaveform

LVDSꢀLevelsꢀTestꢀCircuit

LVDSꢀSwitchingꢀTestꢀCircuit

OUT

0Vꢀ(Differential)

OUT

C_Lꢀ=ꢀ10pF

50

ꢀ

V_OD

V_OS

V_DIFF

R_Lꢀ=ꢀ100ꢀ

80%

V_DIFF

0V

C_Lꢀ=ꢀ10pF

20%

OUT

t_R

t_F

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ10ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

CMOS ELECTRICAL CHARACTERISTICS

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

SupplyꢀCurrent,ꢀDynamic,ꢀwithꢀ

LoadedꢀOutputsꢀ

Atꢀ100MHz,ꢀload=15pFꢀ

ꢀꢀ

ꢀ16ꢀ

20ꢀ

mAꢀ

I_DDꢀ

OperatingꢀVoltageꢀ

ꢀꢀ

2.25ꢀ

ꢀ

3.63ꢀ

V_DDꢀ

V_OH3.3ꢀ

V_OL3.3ꢀ

V_OHC3.3ꢀ

Vꢀ

OutputꢀHighꢀVoltageꢀ(LVTTL)ꢀ

OutputꢀLowꢀVoltageꢀ(LVTTL)ꢀ

OutputꢀHighꢀVoltageꢀ(LVCMOS)ꢀ

OutputꢀHighꢀVoltageꢀꢀ

I_OHꢀ=ꢀꢁ8.5mA,ꢀ3.3VꢀSuppliesꢀ

I_OLꢀ=ꢀ8.5mA,ꢀ3.3VꢀSuppliesꢀ

I_OHꢀ=ꢀꢁ4mA,ꢀ3.3VꢀSuppliesꢀ

I_OHꢀ=ꢀ1mA,ꢀ2.5VꢀSuppliesꢀ

I_OLꢀ=ꢀ1mA,ꢀ2.5VꢀSuppliesꢀ

2.4ꢀ

ꢀ

0.4ꢀ

V_DDꢀ–ꢀ0.4ꢀ

V_DDꢀ–ꢀ0.2ꢀ

ꢀ

V_OH2.5

ꢀ

OutputꢀLowꢀVoltageꢀꢀ

V_OL2.5ꢀ

0.2ꢀ

V_OLꢀ=ꢀ0.4V,ꢀV_OHꢀ=ꢀ2.4Vꢀꢀ

Outputꢀdriveꢀcurrentꢀ

ꢀ

8.5ꢀ

ꢀ

mAꢀ

I_OSD3.3

ꢀ

(perꢀoutput),ꢀ3.3VꢀSuppliesꢀ

10%ꢀ~ꢀ90%ꢀVDDꢀwithꢀ10ꢀpFꢀ

loadꢀ

OutputꢀClockꢀRise/FallꢀTimeꢀ

OutputꢀClockꢀDutyꢀCycleꢀ

ShortꢀCircuitꢀCurrentꢀ

_ꢀT_r,T_fꢀꢀ

_ꢀꢀ

ꢀꢀ

45ꢀ

ꢀꢀ

1.2ꢀ

50ꢀ

1.6ꢀ

55ꢀ

ꢀꢀ

nsꢀ

%ꢀ

Measuredꢀ@ꢀ50%ꢀVDDꢀ

ꢀꢀ

mAꢀ

_ꢀI_Sꢀ

±50ꢀ

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ11ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

BOARD DESIGN AND LAYOUT CONSIDERATIONS

ꢀ

L2X and L4X:ꢀꢀTryꢀtoꢀreduceꢀtheꢀPCBꢀtraceꢀ

inductanceꢀtoꢀaꢀminimumꢀbyꢀplacingꢀL2XꢀandꢀL4Xꢀasꢀ

physicallyꢀcloseꢀtoꢀtheirꢀrespectiveꢀpinsꢀasꢀpossible.ꢀꢀ

AlsoꢀbeꢀsureꢀtoꢀbypassꢀeachꢀVddꢀconnectionꢀ

especiallyꢀtakingꢀcareꢀtoꢀplaceꢀaꢀ0.01ꢀuFꢀbypassꢀatꢀ

theꢀVddꢀsideꢀofꢀL2XꢀandꢀL4Xꢀ(seeꢀrecommendedꢀ

layout).ꢀ

ꢀ

Crystal connections:ꢀꢀBeꢀsureꢀtoꢀkeepꢀtheꢀgroundꢀ

planeꢀunderꢀtheꢀcrystalꢀconnectionsꢀcontinuousꢀsoꢀ

thatꢀtheꢀstrayꢀcapacitanceꢀisꢀconsistentꢀonꢀbothꢀ

crystalꢀconnections.ꢀꢀAlsoꢀbeꢀsureꢀtoꢀkeepꢀtheꢀcrystalꢀ

connectionsꢀsymmetricalꢀwithꢀrespectꢀtoꢀoneꢀanotherꢀ

andꢀtheꢀcrystalꢀconnectionꢀpinsꢀofꢀtheꢀIC.ꢀꢀIfꢀyouꢀ

choseꢀtoꢀuseꢀaꢀseriesꢀcapacitanceꢀandꢀorꢀinductorꢀtoꢀ

fineꢀtuneꢀtheꢀcrystalꢀfrequencyꢀbeꢀsureꢀtoꢀputꢀ

symmetricalꢀpadsꢀforꢀthisꢀcapꢀonꢀbothꢀcrystalꢀpinsꢀ

(seeꢀCadjꢀinꢀrecommendedꢀlayout),ꢀevenꢀifꢀoneꢀofꢀ

theꢀcapacitorsꢀwillꢀbeꢀaꢀ0.01ꢀuFꢀandꢀtheꢀotherꢀisꢀ

usedꢀtoꢀtuneꢀtheꢀfrequency.ꢀToꢀfurtherꢀmaintainꢀaꢀ

symmetricalꢀbalanceꢀonꢀaꢀcrystalꢀthatꢀmayꢀhaveꢀ

moreꢀinternalꢀCstrayꢀonꢀoneꢀpinꢀorꢀtheꢀother,ꢀplaceꢀ

capacitorꢀpadsꢀ(Cbal)ꢀonꢀeachꢀcrystalꢀleadꢀtoꢀgroundꢀ

(seeꢀrecommendedꢀlayout).ꢀꢀR3rdꢀisꢀonlyꢀrequiredꢀifꢀ

aꢀ3^rdꢀovertoneꢀcrystalꢀisꢀused.ꢀ

2X Layout (TSSOP)

ꢀ

V_DDand GND:ꢀBypassꢀVDDANAꢀandꢀVDDBUFꢀwithꢀ

separateꢀbypassꢀcapacitorsꢀandꢀifꢀaꢀV_DDꢀplaneꢀisꢀ

used,ꢀfeedꢀeachꢀbypassꢀcapꢀwithꢀitsꢀownꢀvia.ꢀꢀBeꢀ

sureꢀtoꢀconnectꢀanyꢀgroundꢀpinꢀincludingꢀtheꢀbypassꢀ

capsꢀwithꢀshortꢀviaꢀconnectionsꢀtoꢀtheꢀgroundꢀplane.ꢀ

ꢀ

OESEL:ꢀꢀJ1ꢀisꢀrecommendedꢀsoꢀtheꢀsameꢀPCBꢀ

layoutꢀcanꢀbeꢀusedꢀforꢀbothꢀOESELꢀsettings.ꢀ

ꢀ

4X Layout (TSSOP)

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ12ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

PACKAGE PIN DESCRIPTION AND ASSIGNMENT

OSCOFFSEL

GNDOSC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

L2X

OSCOFFSEL

GNDOSC

VCON

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

L2X

VDDOSC

OESEL

VDDANA

VDDBUF

QBAR

12

11

10

9

VDDOSC

OESEL

VDDANA

VDDBUF

QBAR

12

11

10

9

VDDANA

13

14

15

8

7

6

5

VDDOSC

L4X

VDDANA

13

14

15

8

7

6

5

GNDANA

VCON

XIN

OESEL

P560-0X

DNC

OE

OESEL

P560-4X

VDDOSC

OE

XIN

VDDOSC

16

XOUT

L2X

XOUT

OE

1

2

3

4

XOUT

16

XOUT

L2X

1

2

3

4

OE

L4X

Q

DNC

Q

GNDANA

GNDBUF

VDDOSC

GNDBUF

2X AFM Package Pin Out

4X AFM Package Pin Out

ꢀ

PIN ASSIGNMENTS

Name

Pin# Type Product

Description

Setꢀtoꢀ“0”ꢀ(GND)ꢀtoꢀchooseꢀtoꢀturnꢀoffꢀtheꢀoscillatorꢀwhenꢀoutputsꢀareꢀdisabledꢀ(OE).ꢀDefaultꢀ(noꢀ

connect)ꢀisꢀOSCꢀalwaysꢀon.ꢀ

OSCOFFSELꢀ

GNDOSCꢀ

VCONꢀ

1ꢀ

2ꢀ

3ꢀ

Iꢀ

Pꢀ

Iꢀ

2Xꢀ&ꢀ4Xꢀ

GNDꢀconnectionꢀforꢀoscillatorꢀcircuitry.ꢀ

ControlꢀVoltageꢀinput.ꢀUseꢀthisꢀpinꢀtoꢀchangeꢀtheꢀoutputꢀfrequencyꢀbyꢀvaryingꢀtheꢀappliedꢀControlꢀ

Voltage.ꢀ

XINꢀ

4ꢀ

5ꢀ

6ꢀ

Iꢀ

Oꢀ

Iꢀ

2Xꢀ&ꢀ4Xꢀ

2Xꢀ

Inputꢀfromꢀcrystalꢀoscillatorꢀcircuitry.ꢀ

Outputꢀfromꢀcrystalꢀoscillatorꢀcircuitry.ꢀ

OutputꢀEnableꢀinputꢀ(seeꢀ"OEꢀLOGICꢀSELECTIONꢀTABLE").ꢀ

DoꢀNotꢀConnect.ꢀ

XOUTꢀ

OEꢀ

DNCꢀ

Externalꢀinductorꢀconnection.ꢀTheꢀinductorꢀisꢀrecommendedꢀtoꢀbeꢀaꢀhighꢀQꢀsmallꢀ

sizeꢀ0402ꢀorꢀ0603ꢀSMDꢀcomponent,ꢀandꢀmustꢀbeꢀplacedꢀbetweenꢀL4Xꢀandꢀadjacentꢀ

VDDOSC.ꢀPlaceꢀinductorꢀasꢀcloseꢀtoꢀtheꢀICꢀasꢀpossibleꢀtoꢀminimizeꢀparasiticꢀeffectsꢀ

andꢀtoꢀmaintainꢀinductorꢀQ.ꢀꢀThisꢀinductorꢀisꢀusedꢀwithꢀ4XꢀAFMs.ꢀꢀꢀ

7ꢀ

8ꢀ

Iꢀ

L4Xꢀ

4Xꢀ

GNDANAꢀ

VDDOSCꢀ

2Xꢀ

4Xꢀ

GNDꢀconnection.ꢀ

Pꢀ

VDDꢀconnectionꢀforꢀoscillatorꢀcircuitry.ꢀVDDOSCꢀshouldꢀbeꢀseparatelyꢀdecoupledꢀfromꢀotherꢀ

VDDsꢀwheneverꢀpossible.ꢀ

GNDBUFꢀ

Qꢀ

9ꢀ

Pꢀ

Oꢀ

2Xꢀ&ꢀ4Xꢀ

GNDꢀconnectionꢀforꢀoutputꢀbufferꢀcircuitry.ꢀ

PECL/LVDSꢀorꢀCMOSꢀoutput.ꢀ

10ꢀ

11ꢀ

QBARꢀ

ComplementaryꢀPECL/LVDSꢀoutputꢀorꢀinꢀphaseꢀCMOS.ꢀ

VDDꢀconnectionꢀforꢀoutputꢀbufferꢀcircuitry.ꢀꢀVDDBUFꢀshouldꢀbeꢀseparatelyꢀdecoupledꢀfromꢀotherꢀ

VDDsꢀwheneverꢀpossible.ꢀ

VDDBUFꢀ

12ꢀ

Pꢀ

2Xꢀ&ꢀ4Xꢀ

VDDꢀconnectionꢀforꢀanalogꢀcircuitry.ꢀꢀVDDANAꢀshouldꢀbeꢀseparatelyꢀdecoupledꢀfromꢀotherꢀVDDsꢀ

wheneverꢀpossible.ꢀ

VDDANAꢀ

OESELꢀ

13ꢀ

14ꢀ

15ꢀ

Pꢀ

Iꢀ

2Xꢀ&ꢀ4Xꢀ

SelectorꢀinputꢀtoꢀchooseꢀtheꢀOEꢀcontrolꢀlogicꢀ(seeꢀ“OEꢀSELECTIONꢀTABLE”).ꢀInternalꢀpullꢁdown.ꢀ

VDDꢀconnectionꢀforꢀoscillatorꢀcircuitry.ꢀꢀVDDOSCꢀshouldꢀbeꢀseparatelyꢀdecoupledꢀfromꢀotherꢀ

VDDsꢀwheneverꢀpossible.ꢀ

VDDOSCꢀ

Pꢀ

Externalꢀinductorꢀconnection.ꢀTheꢀinductorꢀisꢀrecommendedꢀtoꢀbeꢀaꢀhighꢀQꢀsmallꢀ

sizeꢀ0402ꢀorꢀ0603ꢀSMDꢀcomponent,ꢀandꢀmustꢀbeꢀplacedꢀbetweenꢀL2Xꢀandꢀadjacentꢀ

VDDOSC.ꢀPlaceꢀinductorꢀasꢀcloseꢀtoꢀtheꢀICꢀasꢀpossibleꢀtoꢀminimizeꢀparasiticꢀeffectsꢀ

andꢀtoꢀmaintainꢀinductorꢀQ.ꢀ

L2Xꢀ

16ꢀ

Iꢀ

2Xꢀ&ꢀ4Xꢀ

ꢀꢀ

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ13ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

PACKAGE INFORMATION

16 PIN TSSOP

16 PIN TSSOP ( mm )

Symbol

Min.

Max.

1.20

0.15

0.30

0.20

5.10

4.50

E

H

A

A1

B

ꢁ

0.05

0.19

0.09

4.90

4.30

D

C

D

E

A

H

L

6.40ꢀBSC

A1

0.45

0.75

C

e

0.65ꢀBSC

L

B

e

16 PIN 3x3 QFN

ꢀ

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ14ꢀꢀ

Analog Frequency Multiplier

PL560-xx VCXO Family

ꢀ

ORDERING INFORMATION

For part ordering, please contact our Sales Department:

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538,ꢀUSAꢀ

Tel:ꢀ(510)ꢀ492ꢁ0990ꢀFax:ꢀ(510)ꢀ492ꢁ0991ꢀ

ꢀ

PART NUMBER

Theꢀorderꢀnumberꢀforꢀthisꢀdeviceꢀisꢀaꢀcombinationꢀofꢀtheꢀfollowing:ꢀ

Deviceꢀnumber,ꢀPackageꢀtypeꢀandꢀOperatingꢀtemperatureꢀrangeꢀ

PL560-XX X X X X

NONE=ꢀTUBEꢀ

R=ꢀTAPEꢀANDꢀREELꢀ

PART NUMBER

NONE=ꢀꢀNORMALꢀPACKAGEꢀ

L=ꢀGREENꢀPACKAGEꢀ

PACKAGE TYPE

O=TSSOPꢀ

Q=ꢀQFNꢀ3x3ꢀ

TEMPERATURE

C=COMMERCIALꢀ

I=INDUSTRIALꢀ

Order Number

Marking

P560ꢁXXꢀOC

Package Option

PL560ꢁXXOC

TSSOPꢀ–ꢀTube

PL560ꢁXXOCꢁR

PL560ꢁXXOCL

PL560ꢁXXOCLꢁR

PL560ꢁXXQC

P560ꢁXXꢀOC

P560ꢁXXꢀQC

TSSOPꢀ–ꢀTapeꢀandꢀReel

TSSOPꢀ(GREEN)–ꢀTube

TSSOPꢀ(GREEN)–ꢀTapeꢀandꢀReel

QFNꢀ–ꢀTube

PL560ꢁXXQCꢁR

PL560ꢁXXQCL

PL560ꢁXXQCLꢁR

QFNꢀ–ꢀTapeꢀandꢀReel

QFNꢀꢀ(GREEN)–ꢀTube

QFNꢀꢀ(GREEN)–ꢀTapeꢀandꢀReel

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information

furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said

information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.

LIFE SUPPORT POLICY:ꢀPhaseLink’sꢀproductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀasꢀcriticalꢀcomponentsꢀinꢀlifeꢀsupportꢀdevicesꢀorꢀsystemsꢀwithoutꢀtheꢀ

expressꢀwrittenꢀapprovalꢀofꢀtheꢀPresidentꢀofꢀPhaseLinkꢀCorporation.ꢀꢀ

47745ꢀFremontꢀBlvd.,ꢀFremont,ꢀCAꢀ94538ꢀꢀTELꢀ(510)ꢀ492ꢁ0990,ꢀFAXꢀ(510)ꢀ492ꢁ0991ꢀꢀꢀ www.phaselink.comꢀꢀꢀꢀꢀRev.:02ꢁ09ꢁ07ꢀꢀPageꢀ15ꢀꢀ

生命周期：	Transferred	Reach Compliance Code：	unknown
风险等级：	5.79	Is Samacsys：	N
Base Number Matches：	1

型号	制造商	描述	价格	文档
PL560-09OCLR	PLL	Analog Frequency Multiplier	获取价格
PL560-09OCR	PLL	Analog Frequency Multiplier	获取价格
PL560-09OI	PLL	Analog Frequency Multiplier	获取价格
PL560-09OIL	PLL	Analog Frequency Multiplier	获取价格
PL560-09OILR	PLL	Analog Frequency Multiplier	获取价格
PL560-09OIR	PLL	Analog Frequency Multiplier	获取价格
PL560-09QC	PLL	Analog Frequency Multiplier	获取价格
PL560-09QC-R	PLL	Clock Generator	获取价格
PL560-09QCL	PLL	Analog Frequency Multiplier	获取价格
PL560-09QCL-R	PLL	Clock Generator	获取价格

PL560-09OCL

PL560-09OCL 概述

PL560-09OCL 规格参数

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