PL611S-27 [PLL]
1.8V to 3.3V PicoPLLTM Programmable Clock; 1.8V至3.3V PicoPLLTM可编程时钟
| 型号： | PL611S-27 |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | 1.8V to 3.3V PicoPLLTM Programmable Clock |
| 文件： | 总9页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
(Preliminary)PL611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
FEATURES
DESCRIPTION
The PL611s-27 is a general purpose frequency
synthesizer and a member of PhaseLink’s PicoPLL
product family. Designed to fit in a small 6-pin DFN,
or 6-pin SOT package for high performance
• Advanced One Time Programmable (OTP) PLL design
• Programmable PLL or direct oscillation operation
• Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
• Output Frequency up to
applications, the PL611s-27 offers very low phase
noise, jitter, and power consumption, while offering 2
clock outputs. The Frequency Switching (FSEL)
capability of PL611s-27 allows for programming two
sets of frequencies, while the power down feature of
PL611s-27, when activated, allows the IC to
consume less than 10µA of power. PL611s-27’s
programming flexibility allows generating any output
using a Reference input signal.
o65MHz @ 1.8V operation
o9/MHz @ 2.5V operation
o125MHz @ 3.3V operation
• Reference Input Frequency: 1MHz to 200MHz
• Accepts >0.1V reference signal input voltage
• Low current consumption, <10µA when PDB is
activated
• One programmable I/O pin can be configured as
Output Enable (OE), Frequency Switching
(FSEL), or Power Down (PDB) input.
• Disabled outputs programmable as HiZ or Active Low.
• Single 1.8V, 2.5V, or 3.3V ± 10% power supply
• Operating temperature range from 0°C to 70°C
• Available in 6-pin SOT23 & DFN GREEN/RoHS
Compliant packages
PACKAGE PIN CONFIGURATION
CLK1
GND
FIN
CLK0
VDD
1
2
3
6
5
4
FIN
CLK1
GND
1
2
3
6
5
4
OE, PDB, FSEL
VDD
CLK0
OE, PDB, FSEL
DFN-6L
(2.0mmx1.3mmx0.6mm)
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
R-counter
ref
F
FIN
(8-Bit)
Loop
Filter
Phase
Detector
Charge
Pump
M-counter
(11-Bit)
F
=F * (2 * M/R)
vco ref
VCO
CLK1
CLK0
P-counter
(5-Bit)
Fout=FVCO/(2*P)
Programming
Logic
OE, PDB,
FSEL
Programmable Function
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 1
(Preliminary)PL611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Programmable
Input/Output
Output Drive Strength
Output Frequency
F
OUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
Three optional drive strengths to
choose from:
One output pin can be configured
as:
P = 5 bit
• Low: 4mA
• OE - input
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
• Std: 8mA (default)
• High: 16mA
• PDB - input
• FSEL – input
•
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Pin Assignment
Name
Type
Description
DFN
Pin#
SOT
Pin #
CLK1
GND
FIN
2
3
1
1
2
3
O
P
I
Programmable Clock Output
GND connection
Reference input pin
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down (PDB) input or Frequency Switching (FSEL) input. This
pin has an internal 60KΩ pull up resistor.
The OE and PDB features can be programmed to allow the output to float
(Hi Z), or to operate in the ‘Active low’ mode.
OE,
PDB,
FSEL
6
4
I
State
OE
PDB
FSEL
0
Disable CLK
Normal mode
Power Down Mode
Normal mode
Frequency ‘2’
Frequency ‘1’
1 (default)
VDD
5
4
5
6
P
VDD connection
CLK0
O
Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
OE
PDB
Osc.
PLL
CLK0
CLK1
1
N/A
N/A
1
On
On
On
Off
On
Off
On
Off
On
On
On
On
0
HiZ or Active Low
On
N/A
N/A
0
HiZ or Active Low
HiZ or Active Low
Note: HiZ or Active Low states are programmable functions and will be set per request.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 2
(Preliminary)PL611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-27 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-27 accepts a reference clock input of 1MHz to 200MHz and is
capable of producing two outputs up to 55MHz. This flexible design allows the PL611s-27 to deliver any PLL
generated frequency, FREF (Ref Clk) frequency or FREF /(2*P) to CLK0 and/or CLK1. Some of the design features
of the PL611s-27 are mentioned below:
PLL Programming
Output Enable (OE)
The PLL in the PL611s-27 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [FOUT = FREF * M / (R * P) ].
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60kΩ pull up
resistor giving a default condition of logic “1”.
The OE feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
Clock Output (CLK0)
Power-Down Control (PDB)
CLK0 is the main clock output. The output of CLK0
can be configured as the PLL output (FVCO/(2*P)),
The Power Down (PDB) feature allows the user to
put the PL611s-27 into “Sleep Mode”. When
F
REF (Ref Clk Frequency) output, or FREF/(2*P)
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10µA of power. The PDB pin incorporates a 60kΩ
pull up resistor giving a default condition of logic “1”.
output. The output drive level can be programmed to
Low Drive (4mA), Standard Drive (8mA) or High Drive
(16mA). The maximum output frequency is 125MHz.
Clock Output (CLK1)
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
The CLK1 feature allows the PL611s-27 to have an
additional clock output. This output can be
programmed to one of the following:
Frequency Select (FSEL)
F
F
REF - Reference (Ref Clk) Frequency
REF / 2
The Frequency Select (FSEL) feature allows the
PL611s-27 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60kΩ pull
up resistor giving a default condition of logic “1”.
CLK0
CLK0 / 2
When using the OE function CLK1 will remain
“Always On” and will not be disabled when OE is
pulled low. When using the PDB function CLK1 will
be disabled along with CLK0. The output drive level
can be programmed to Low Drive (4mA), Standard
Drive (8mA) or High Drive (16mA). The maximum
output frequency is 125MHz.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 3
(Preliminary)PL611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD
7
V
V
-
-
-
0.5
0.5
0.5
Input Voltage Range
V
VDD
VDD
+
+
0.5
0.5
I
Output Voltage Range
V
V
O
Soldering Temperature (Green package)
Data Retention @ 85°C
260
°C
Year
°C
°C
10
Storage Temperature
-65
-40
150
85
T
S
Ambient Operating Temperature*
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNITS
@ VDD =3.3V
@ VDD =2.5V
@ VDD =1.8V
200
Input (FIN) Frequency
1
MHz
Vpp
166
133
VDD
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Internally AC coupled (High Frequency)
0.9
0.1
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
VDD
Vpp
@ VDD =3.3V
125
90
65
2
MHz
MHz
MHz
ms
ns
Output Frequency
@ VDD =2.5V
@ VDD =1.8V
Settling Time
At power-up (after VDD increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
15pF Load, 10/90% VDD, High Drive, 3.3V
15pF Load, 90/10% VDD, High Drive, 3.3V
10
2
Output Enable Time
ms
ns
Output Rise Time
Output Fall Time
1.2
1.2
50
1.7
1.7
55
ns
Duty Cycle
VDD /2
45
%
Period Jitter,Pk-to-Pk*
(measured from 10,000 samples) GND.
With capacitive decoupling between VDD and
70
ps
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 4
(Preliminary)PL611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
5.5
MAX.
UNITS
mA
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
Loaded CMOS Outputs
Stand By Current, with Loaded
Outputs
@ VDD =3.3V, 27MHz,
load=15pF
@ VDD =2.5V, 27MHz,
load=15pF
@ VDD =1.8V, 27MHz,
load=15pF
IDD
IDD
IDD
IDD
3.8
mA
1.8*
mA
When PDB=0
<10
µA
Operating Voltage
VDD
VOL
1.62
3.63
0.4
V
V
Output Low Voltage
IOL = +4mA Standard Drive
Output High Voltage
VOH
IOSD
IOSD
IOHD
IOH = -4mA Standard Drive VDD – 0.4
V
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
4
8
mA
mA
mA
16
* Note: Please contact PhaseLink, if super low-power is required.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 5
(Preliminary)PL611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
LAYOUT RECOMMENDATIONS
DFN-6L Evaluation Board
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to the
VDD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this equals
ringing!
- Multiple VDD pins should be decoupled separately for
best performance.
- Long trace = Transmission Line. Without proper
termination this will cause reflections ( looks like ringing ).
- Addition of a ferrite bead in series with VDD can help
prevent noise from other board sources
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Value of decoupling capacitor is frequency dependant.
Typical values to use are 0.1µF for designs using crystals
< 50MHz and 0.01µF for designs using crystals > 50MHz.
- Match trace at one side to avoid reflections bouncing
back and forth.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20 Ω )
To CMOS Input
50Ω line
Series Resistor
Use value to match output
buffer impedance to 50 Ω
trace. Typical value 30 Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 6
(Preliminary)PL611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load .
Crystal
Cst
XIN
XOUT
1
8
Cpt
Cpt
CST – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency
offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the
oscillator.
CPT – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 7
(Preliminary)PL611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6L
Dimension in MM
Symbol
Min.
1.05
0.05
1.00
0.30
0.08
2.80
1.50
2.60
0.35
Max.
1.35
0.15
1.20
0.50
0.20
3.00
1.70
3.0
Pin1 Dot
E
H
A
A1
A2
b
D
c
D
E
A2
A
H
L
A1
C
0.55
b
e
L
e
0.95 BSC
DFN-6L
D1
Dimension in MM
e
Symbol
D
b
Min.
0.50
0.00
0.152
0.15
Max.
0.60
0.05
0.152
0.25
Pin 6 ID
Chamfer
A
A1
A3
b
E
E1
e
0.40BSC
D
1.25
1.95
0.75
0.95
0.20
1.35
2.05
0.85
1.05
0.30
L
E
Pin1 Dot
D1
E1
L
A1
A
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 8
(Preliminary)PL611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL611s-27-XXX X X X
PART NUMBER
3 DIGIT ID Code *
(will be assigned at
programming time)
NONE= TUBE
R=TAPE and REEL
PACKAGE TYPE
G=DFN-6L
T=SOT23-6L
TEMPERATURE
C=COMMERCIAL
I = INDUSTRIAL
Part/Order Number
Marking†
Package Option
PL611s-27-XXXGC-R
PL611s-27-XXXTC-R
XXX
6-Pin DFN (Tape and Reel)
6-Pin SOT23 (Tape and Reel)
27XXX
† Note: ‘XXX’ designates marking identifier that, at times, could be independent of the part number. Please consult your
PhaseLink sales for marking information.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 9
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