PL663-29 [PLL]
Analog Frequency Multiplier; 模拟倍频器
| 型号： | PL663-29 |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Analog Frequency Multiplier |
| 文件： | 总15页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Analog Frequency Multiplier
PL660 and PL663 XO Families
DESCRIPTION
PhaseLink’s Analog Frequency Multipliers TM
FEATURES
• Non-PLL frequency multiplication
(AFMs) are the industry’s first “Balanced Oscillator”
utilizing analog multiplication of the fundamental
frequency (at double or quadruple frequency),
combined with an attenuation of the fundamental of
the reference crystal, without using a phase-locked
loop (PLL), in CMOS technology.
• Input frequency from 30-200 MHz
• Output frequency from 60-800 MHz
• Low phase noise and jitter (equivalent to fundamental
at the output frequency)
• Ultra-low jitter
o RMS phase jitter < 0.25 ps (12 kHz to 20 MHz)
o RMS period jitter < 2.5 ps typ.
• Low phase noise
o -145 dBc/Hz @ 100 kHz offset from 155.52 MHz
o -150 dBc/Hz @ 10 MHz offset from 155.52 MHz
• Low input frequency eliminates the need for expensive
crystals
PhaseLink’s patent pending PL66x family of AFM
products can achieve up to 800 MHz differential
PECL, LVDS, or single-ended CMOS output with
little jitter or phase noise deterioration.
PL66x-xx family of products utilize a low-power
CMOS technology and are housed in GREEN/
RoHS compliant 16-pin TSSOP and 3x3 QFN
packages.
• Differential PECL/LVDS, or single-ended CMOS output
• Single 2.5V or 3.3V +/- 10% power supply
• Optional industrial temperature range (-40°C to +85°C)
• Available in 16-pin GREEN/RoHS compliant TSSOP, and
16-pin 3x3 QFN packages.
Figure 1: 2X AFM Phase Noise at 212.5 MHz (106.25 MHz 3rd overtone crystal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 1
Analog Frequency Multiplier
PL660 and PL663 XO Families
L 2 X
O E
X IN
Q B A R
Q
F re q u e n c y
X 2
O s c illa to r
A m p lifie r
R
F re q u e n c y
X 4
X O U T
O n ly re q u ire d in x 4 d e s ig n s
L 4 X
Figure 2: Block Diagram of AFM XO
Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 212.5 MHz, while
Figure 4 shows the very low levels of sub-harmonics that correspond to the exceptional performance (i.e.
low jitter).
Figure 3: Period Jitter Histogram at 212.5MHz
Analog Frequency Multiplier (2x),
with 106.25 MHz crystal
Figure 4: Spectrum Analysis at 212.5MHz
Analog Frequency Multiplier (2x),
with sub-harmonics below –69 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
OE
Output State
0 (Default)
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
0 (Default)
1
0
PECL
1
0 (Default)
1
1 (Default)
0
1 (Default)
0 (Default)
1
LVDS or CMOS
OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. [The ‘Default’ state is set by internal pull up/down resistor.]
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 2
Analog Frequency Multiplier
PL660 and PL663 XO Families
PRODUCT SELECTOR GUIDE
FREQUENCY VERSUS PHASE NOISE PERFORMANCE
Phase Noise at Frequency Offset From Carrier (dBc/Hz)
Input
Frequency
Range
Analog
Frequency
Multiplication
Factor
Output
Frequency Output
Range
(MHz)
Part
Number
Type
Carrier
Freq.
(MHz)
100
Hz
10
KHz
100
KHz
1
MHz
10
10 Hz
1 KHz
(MHz)
MHz
PL660-08
PL660-09
PL663-07
PL663-08
PL663-09
PL663-17
PL663-18
PL663-19
PL663-28
PL663-29
30 - 80
30 - 80
4
4
2
2
2
2
2
2
2
2
120 - 320
120 - 320
60 - 160
PECL
LVDS
CMOS
PECL
LVDS
CMOS
PECL
LVDS
PECL
LVDS
155.52
155.52
156.25
156.25
156.25
212.5
-72
-72
-75
-75
-75
-70
-70
-70
-60
-60
-100
-100
-105
-105
-105
-100
-100
-100
-92
-125
-125
-130
-130
-130
-130
-130
-130
-122
-122
-132
-132
-140
-140
-140
-140
-140
-140
-140
-140
-142
-142
-145
-145
-145
-145
-145
-145
-142
-142
-147
-147
-150
-150
-150
-148
-148
-148
-146
-146
-149
-149
-150
-150
-150
-148
-148
-148
-146
-148
30 - 80
30 - 80
60 - 160
30 - 80
60 - 160
75 - 140
75 - 140
75 - 140
140 - 160
140 - 160
150 - 280
150 - 280
150 - 280
280 - 320
280 - 320
212.5
212.5
311.04
311.04
-92
FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE
RMS Period Peak to Peak
RMS
Accumulated
(L.T.) Jitter (ps)
Phase Jitter
(12 KHz-20MHz)
(ps)
Spectral Specifications / Sub-harmonic Content
Jitter
(ps)
Period Jitter
(ps)
(dBc)
Frequency (MHz)
Output
Freq.
(MHz)
Part
Number
Carrier
@
@
@
@
@
@
Freq.
MHz
(Fc)
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Min. Typ. Max.
-75% -50% -25% +25% +50% +75%
(Fc)
(Fc) (Fc)
(Fc)
(Fc)
(Fc)
PL660-08
PL660-09
PL663-07
PL663-08
PL663-09
PL663-17
PL663-18
PL663-19
PL663-28
PL663-29
155.52
155.52
156.25
156.25
156.25
212.50
212.50
212.50
311.04
311.04
3
3
5
5
3
3
3
4
4
4
4
4
21 30
21 30
18 20
18 20
18 20
18 20
18 20
18 20
18 20
18 20
5
5
3
3
3
4
4
4
4
4
0.25
0.25
0.24
0.24
0.24
0.19
0.19
0.19
0.16
0.16
155.52
155.52
156.25
156.25
156.25
212.50
212.50
212.50
311.04
311.04
-66
-66
-61
-61
-70
-70
-70
-70
-70
-70
-65
-65
-67
-67
-75
-75
-75
-75
-75
-75
-70
-70
-70
-70
2
2
2
2.5
2.5
2.5
2.5
2.5
Note: Wavecrest data 10,000 hits. No Filtering was used in Jitter Calculations.
Agilent E5500 was used for phase jitter measurements.
Spectral specifications were obtained using Agilent E7401A.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 3
Analog Frequency Multiplier
PL660 and PL663 XO Families
BOARD LAYOUT CONSIDERATIONS AND CRYSTAL SPECIFICATIONS
BOARD LAYOUT CONSIDERATIONS
To minimize parasitic effects and improve performance, do the following:
Place the crystal as close as possible to the IC.
•
•
Make the board traces that are connected to the crystal pins symmetrical. The board trace
symmetry is very important, as it reduces the negative parasitic effects to produce clean
frequency multiplication with low jitter.
CRYSTAL SPECIFICATIONS
Crystal
Resonator
CL (xtal)
Typical
ESR(RE)
Max.
C0
C0/C1
Max.
Part Number
Mode
Frequency
)
Max.
(FXIN
PL660-08
PL660-09
Fundamental or
3rd overtone
25~75MHz
30~80MHz
5 pF
5 pF
5 pF
5 pF
30
30
60
60
Ω
Ω
Ω
Ω
4.5 pF
4.5 pF
4.0 pF
4.0 pF
N.A.
N.A.
N.A.
N.A.
PL663-07
PL663-08
PL663-09
Fundamental or
3rd overtone
PL663-17
PL663-18
PL663-19
Fundamental or
3rd overtone
75~140MHz
140~200MHz
PL663-28
PL663-29
Fundamental or
3rd overtone
Note: Non-specified parameters can be chosen as standard values from crystal suppliers.
CL ratings larger than 5pF require a crystal frequency adjustment.
Request detailed crystal specifications from PhaseLink.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 4
Analog Frequency Multiplier
PL660 and PL663 XO Families
EXTERNAL COMPONENT VALUES
INDUCTOR VALUE OPTIMIZATION
The required inductor value(s) for the best performance depends on the operating frequency, and the board layout
specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink’s
evaluation board design. These inductor values provide the user with a starting point to determine the optimum
inductor values. Additional fine-tuning may be required to determine the optimal solution.
To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software. You
can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two
worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second worksheet
(named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value.
For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to
determine the optimum values for the required inductors. This software is developed based on the parasitic
information from PhaseLink’s board layout and can be used to determine the required inductor and parallel
capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their design,
we recommend to use the parasitic information of their board layout to calculate the optimized inductor values.
Please use the following fine tuning procedure:
Figure 5: Diagram Representation of the Related System Inductance and Capacitance
DIE SIDE
- Cinternal = Based on AFM Device
PCB side
- LWB1 = 2 nH, (2 places), Stray inductance
- Cpad = 2.0 pF, Bond pad and its ESD circuitry - Cstray = 1.0 pF, Stray capacitance
- L2X (L4X) = 2x or 4x inductor
- C11 = 0.4 pF, The following amplifier stage
- C2X (C4X) = range (0.1 to 2.7), Fine tune inductor if
used
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Rev. 3/20/07 Page 5
Analog Frequency Multiplier
PL660 and PL663 XO Families
• There are two default variables that normally will not need to be modified. These are Cpad, and C11 and are
found in cells B22 and B27 of ‘AFM Tuning Assistant’, respectively.
• LWB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a
leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of
these and they are assumed to be approximately symmetrical so you only need to enter this inductance once
in cell B23.
• Enter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a
leaded part is used.
• Enter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the ‘AFM
Tuning Assistant’ software to calculate L2X (and C2X if used) for your resonance frequency.
• For 4X AFMs, repeat the same procedure in the L4X worksheet.
• See the examples below.
DETERMINING STRAY L’s AND C’s IN A LAYOUT
Figure 6: Diagram Representation of PL660-08 Board Layout
Let’s take the PL660-08 (4x XO) for example, as shown in Figure 6. This takes a crystal input range of 30 to 80
MHz and multiplies this to an output of 120 to 320 MHz. To determine the stray L’s and C’s of the layout we will
assemble two test units. One AFM will be tuned to the lower range of the device (120 MHz), and the other to the
upper range of the device (320 MHz).
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Rev. 3/20/07 Page 6
Analog Frequency Multiplier
PL660 and PL663 XO Families
120 MHz AFM Tuning: Using the “AFM Tuning Assistant” find the PL660-0x in the L2X worksheet. Enter the
Cinternal value found next to it into cell B21. In cell B24 enter the closest standard inductor value (see CoilCraft
0603CS series for example) to achieve the closest peak frequency to 60 MHz. Repeat the same procedure for
L4X at 120 MHz.
Results: L2X = 180 nH, L4X = 82 nH.
320 MHz AFM tuning: Repeat the previous procedure for L2X at 120 MHz and L4X at 320 MHz.
Results: L2X = 24 nH, L4X = 10 nH.
Proceed and assemble the test units.
Measuring 120 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6. While power is
applied to the PCB, set the generator output to +12 dBm and the frequency to 30 MHz. Since this is the 2x port,
the scope will show 60 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 30 MHz until the
amplitude on the scope is maximum and record the generator frequency. For example peak recorded at 29.8x2 or
59.6 MHz.
Measuring 320 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6. While power is
applied to the PCB, set the generator output to +12 dBm and the frequency to 80 MHz. Since this is the 2x port the
scope will show 160 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 80 MHz until the
amplitude on the scope is maximum and record the generator frequency. For example peak recorded at 78.0 x 2 =
156 MHz
In the AFM Tuning Assistant, add the scope’s probe capacitance to the Cstray cell. For our example 0.5 pF + 1.0
pF = 1.5 pF. With L2X at 24 nH adjust LWB1 (cell B23) until the peak frequency reads 156 MHz. Next replace the
L2X value with 180 nH and see if it peaks at 59.6 MHz. If it does not, adjust the Cstray until 59.4 MHz is achieved.
Again enter 24 nH for L2X and fine tune LWB1 for 156 MHz.
Results: LWB1 = 1.6 nH, Cstray = 2.9 pF-0.5 pF = 2.4 pF (subtract scope probe stray)
Repeat the same steps for the L4X: Set the generator to 80 MHz. The 82 nH peaks at 118 MHz and the 10 nH
peaks at 304 MHz.
Results: LWB1 = 1.8 nH, Cstray = 2.5 pF-0.5 pF = 2.0 pF (subtract scope probe stray)
Internal Capacitor Selection by Device
Device Number
Cinternal (pF)
2X
4X
PL660-0X
PL663-0X
PL663-1X
PL663-2X
34.125
46.500
14.625
14.625
16.500
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Rev. 3/20/07 Page 7
Analog Frequency Multiplier
PL660 and PL663 XO Families
EXTERNAL COMPONENT VALUES – 3RD OVERTONE RESISTOR SELECTIONS (R3rd)
This resistor is only required when a third overtone crystal is used. The chart below indicates the calculated and
the nearest “E12” resistor values versus frequency.
PL660-08/09
PL663-07/08/09
E12
Pick
PL663-017/18/19
E12
Pick
PL663-28/29
Freq. R3rd
E12
Pick
KΩ
E24
Pick
KΩ
Freq.
(MHz)
R3rd
(Ω)
Freq. R3rd
Freq. R3rd
(MHz)
(Ω)
(MHz)
(Ω)
(MHz)
(Ω)
KΩ
KΩ
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
12,396
11,442
10,625
9,917
9,297
8,750
8,264
7,829
7,438
7,083
6,761
6,467
6,198
5,950
5,721
5,509
5,313
5,129
4,958
4,798
4,648
4,508
4,375
4,250
4,132
4,020
3,914
12
12
10
10
10
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
9,917
9,297
8,750
8,264
7,829
7,438
7,083
6,761
6,467
6,198
5,950
5,721
5,509
5,313
5,129
4,958
4,798
4,648
4,508
4,375
4,250
4,132
4,020
3,914
3,814
3,719
10
10
75
77.5
80
82.5
85
87.5
90
92.5
95
97.5
100
102.5
105
107.5
110
112.5
115
117.5
120
122.5
125
127.5
130
132.5
135
2,125
2,056
1,992
1,932
1,875
1,821
1,771
1,723
1,678
1,635
1,594
1,555
1,518
1,483
1,449
1,417
1,386
1,356
1,328
1,301
1,275
1,250
1,226
1,203
1,181
1,159
1,138
2.2
2.2
2.2
1.8
1.8
1.8
1.8
1.8
1.8
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
140.0
142.0
144.0
146.0
148.0
150.0
152.0
154.0
156.0
158.0
160.0
162.0
164.0
166.0
168.0
170.0
172.0
174.0
176.0
178.0
180.0
182.0
184.0
186.0
188.0
190.0
192.0
194.0
196.0
198.0
200.0
915
902
890
878
866
854
843
832
821
811
801
790
780
770
759
749
740
730
720
711
701
692
683
674
665
656
647
639
630
622
614
0.91
0.91
0.91
0.91
0.91
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.75
0.75
0.75
0.75
0.75
0.75
0.75
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.62
0.62
0.62
0.62
0.62
8.2
8.2
8.2
6.8
6.8
6.8
6.8
6.8
5.6
5.6
5.6
5.6
4.7
4.7
4.7
4.7
4.7
4.7
3.9
3.9
3.9
3.9
3.9
3.9
8.2
8.2
8.2
6.8
6.8
6.8
6.8
6.8
5.6
5.6
5.6
5.6
4.7
4.7
4.7
4.7
4.7
4.7
3.9
3.9
3.9
3.9
137.5
140
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www.phaselink.com
Rev. 3/20/07 Page 8
Analog Frequency Multiplier
PL660 and PL663 XO Families
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
+150
+85
V
Input Voltage, DC
GND-0.5
GND-0.5
-55
V
Output Voltage, DC
VO
V
Storage Temperature
TS
°C
°C
°C
°C
°C
Industrial Ambient Operating Temperature
Commercial Ambient Operating Temperature
Junction Temperature
TA_I
TA_C
TJ
-40
0
+70
125
Lead Temperature (soldering, 10s)
260
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
PECL ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL CONDITIONS
MIN.
TYP.
MAX. UNITS
Supply Current (with loaded outputs)
IDD
Fout = 212.5 MHz
@ VDD – 1.3V
58
65
75
mA
V
Operating Supply Voltage
Output Clock Duty Cycle
Short Circuit Current
VDD
2.25
45
3.63
50
50
55
%
mA
V
RL = 50 Ω to
VDD – 2V
Output High Voltage
VOH
V
DD – 1.025
VDD
1.620
–
Output Low Voltage
Clock Rise Time
Clock Fall Time
VOL
tr
RL = 50 Ω to VDD – 2V
@20/80%
V
0.25
0.25
0.45
0.45
ns
ns
tf
@80/20%
PECL Levels Test Circuit
PECL Transistion Time Waveform
DUTY CYCLE
OUT
VDD
45 - 55%
55 - 45%
50Ω
2.0V
OUT
80%
50Ω
20%
OUT
OUT
tR
tF
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Rev. 3/20/07 Page 9
Analog Frequency Multiplier
PL660 and PL663 XO Families
LVDS ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (with loaded outputs)
IDD
Fout = 212.5 MHz
55
60
mA
Operating Supply Voltage
Output Clock Duty Cycle
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
VDD
2.25
45
3.63
55
V
%
@ 1.25V
50
VOD
∆VOD
VOH
247
-50
355
454
50
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
Output Low Voltage
VOL
0.9
1.125
0
V
Offset Voltage
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
V
out = VDD or GND
Power-off Leakage
IOXD
µA
1
10
VDD = 0V
Output Short Circuit Current
Differential Clock Rise Time
IOSD
tr
-5.7
0.5
-8
mA
ns
RL = 100 Ω
CL = 10 pF
(see figure)
0.2
0.2
0.7
Differential Clock Fall Time
tf
0.5
0.7
ns
LVDS Transistion Time Waveform
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
0V (Differential)
OUT
OUT
CL = 10pF
50
Ω
VOD
VOS
VDIFF
RL = 100Ω
80%
80%
VDIFF
0V
50
Ω
CL = 10pF
20%
20%
OUT
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 10
Analog Frequency Multiplier
PL660 and PL663 XO Families
CMOS ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
40
UNITS
Supply Current, Dynamic, with
Loaded Outputs
IDD
At 100MHz, load=15pF
32
mA
Operating Supply Voltage
Output High Voltage (LVTTL)
Output Low Voltage (LVTTL)
Output High Voltage (LVCMOS)
Output High Voltage
VDD
2.25
2.4
3.63
V
V
V
V
V
V
VOH3.3
VOL3.3
VOHC3.3
VOH2.5
VOL2.5
IOH = -8.5mA, 3.3V Supplies
IOL = 8.5mA, 3.3V Supplies
IOH = -4mA, 3.3V Supplies
IOH = 1mA, 2.5V Supplies
IOL = 1mA, 2.5V Supplies
0.4
0.2
VDD – 0.4
VDD – 0.2
Output Low Voltage
VOL = 0.4V, VOH = 2.4V
(per output)
Output drive current
IOSD
Tr/Tf
8.5
mA
10% ~ 90% VDD with 10 pF
load
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
1.2
50
50
1.6
55
ns
%
Measured @ 50% VDD
45
IS
mA
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 11
Analog Frequency Multiplier
PL660 and PL663 XO Families
BOARD DESIGN AND LAYOUT CONSIDERATIONS
L2X and L4X: Reduce the PCB trace inductance to a
minimum by placing L2X and L4X as physically close to
their respective pins as possible. Also be sure to bypass
each VDD connection especially taking care to place a 0.01
uF bypass at the VDD side of L2X and L4X (see
recommended layout).
Crystal Connections: Be sure to keep the ground plane
under the crystal connections continuous so that the stray
capacitace is consistent on both crystal connections. Also
be sure to keep the crystal connections symmetrical with
respect to one another and the crystal connection pins of
the IC. If you chose to use a series capacitance and/or
inductor to fine tune the crystal frequency, be sure to put
symmetrical pads for this cap on both crystal pins (see
Cadj in recommended layout), even if one of the capacitors
will be a 0.01 uF and the other is used to tune the
PL660 (4x AFM) TSSOP Layout
frequency. To further maintain a symmetrical balance on a
crystal that may have more internal Cstray on one pin or
the other, place capacitor pads (Cbal) on each crystal lead
to ground (see recommended layout). R3rd is only
required if a 3rd overtone crystal is used.
VDD and GND: Bypass VDDANA and VDDBUF with
separate bypass capacitors and if a VDD plane is used, feed
each bypass cap with its own via. Be sure to connect any
ground pin including the bypass caps with short via
connection to the ground plane.
OESEL: J1 is recommended so the same PCB layout can
be used for both OESEL settings.
PL663 (2x AFM) TSSOP Layout
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 12
Analog Frequency Multiplier
PL660 and PL663 XO Families
PACKAGE PIN DESCRIPTION AND ASSIGNMENT
1
2
3
4
5
6
7
8
DNC
GNDOSC
DNC
OSCOFFSEL
GNDOSC
16
L2X
1
2
3
4
5
6
7
8
L2X
16
15
14
13
12
11
10
9
1
2
1
1
1
0
9
VDDOSC
OESEL
VDDANA
VDDBUF
QBAR
15
14
13
12
VDDOSC
VDDANA
OESEL
VDDBUF
QBAR
1
2
1
1
1
0
1
3
1
4
1
5
1
6
9
8
7
6
5
VDDANA
OESEL
VDDOSC
L2X
VDDOSC
L4X
1
3
1
4
1
5
1
6
8
7
6
5
OESEL
VDDANA
VDDOSC
L2X
GNDANA
DNC
XIN
DNC
OE
PL660-XX
XIN
PL663-XX
OE
XOUT
OE
XOUT
OE
XOUT
1
2
3
4
XOUT
1
2
3
4
11
10
9
DNC
L4X
Q
Q
GNDANA
VDDOSC
GNDBUF
GNDBUF
2x AFM Package Pin Out
4x AFM Package Pin Out
Description
PIN ASSIGNMENTS
Name
DNC
Pin #
Type Product
2X
Do Not Connect.
1
I
Set to “0” (GND) to turn off the oscillator when outputs are disabled (OE). Default (no connect) is
OSC always on.
OSCOFFSEL
4X
GNDOSC
DNC
2
3
4
5
6
P
I
2X & 4X
2X & 4X
2X & 4X
2X & 4X
2X & 4X
2X
GND connection for oscillator.
Do Not Connect.
XIN
I
Input from crystal oscillator circuitry.
Output from crystal oscillator circuitry.
XOUT
O
I
OE
Output Enable input. See “OE LOGIC SELECTION TABLE”.
Do Not Connect.
DNC
External inductor connection. The inductor is recommended to be a high Q small size 0402 or
0603 SMD component, and must be placed between L4X and adjacent VDDOSC. Place inductor
as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. This
inductor is used with 4x AFMs.
7
8
I
L4X
4X
GNDANA
VDDOSC
2X
4X
GND connection.
P
VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other
VDDs whenever possible.
GNDBUF
Q
9
P
O
O
2X & 4X
2X & 4X
2X & 4X
GND connection.
10
11
PECL/LVDS/CMOS output.
QBAR
Complementary PECL/LVDS output or in-phase CMOS.
VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other
VDDs whenever possible.
VDDBUF
OESEL
12
P
I
2X & 4X
13
14
14
13
2X
4X
2X
4X
Selector input to choose the OE control logic (see “OE SELECTION TABLE”). If no connection
is applied, value will be set to default through internal pull-down resistor.
VDD connection for analog circuitry.VDDANA should be separately decoupled from other VDDs
whenever possible.
VDDANA
VDDOSC
P
P
VDD connection for oscillator. VDD should be separately decoupled from other VDDs whenever
possible.
15
2X & 4X
External inductor connection. The inductor is recommended to be a high Q small size 0402 or
0603 SMD component, and must be placed between L2X and adjacent VDDOSC. Place inductor
as close to the IC as possible to minimize parasitic effects and to maintain inductor Q.
L2X
16
I
2X & 4X
Note: 663-xx devices are 2x multipliers, and 660-xx devices are 4x multipliers.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com
Rev. 3/20/07 Page 13
Analog Frequency Multiplier
PL660 and PL663 XO Families
PACKAGE INFORMATION
16 PIN TSSOP
16 PIN TSSOP ( mm )
Symbol
Min.
-
Max.
1.20
0.15
0.30
0.20
5.10
4.50
E
H
A
A1
B
0.05
0.19
0.09
4.90
4.30
D
C
D
E
A
H
L
6.40 BSC
A1
0.45
0.75
C
e
0.65 BSC
L
B
e
16 PIN 3x3 QFN
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 14
Analog Frequency Multiplier
PL660 and PL663 XO Families
ORDERING INFORMATION
To order parts, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL66X-XX X X X X
NONE= TUBE
R= TAPE AND REEL
PART NUMBER
NONE= NORMAL PACKAGE
L= GREEN PACKAGE
PACKAGE TYPE
O=TSSOP
Q= QFN 3x3
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
Order Number
Marking
P66X-XX OC
Package Option
PL66X-XXOC
TSSOP – Tube
PL66X-XXOC-R
PL66X-XXOCL
PL66X-XXOCL-R
PL66X-XXQC
P66X-XX OC
P66X-XX OC
P66X-XX OC
P66X-XX QC
P66X-XX QC
P66X-XX QC
P66X-XX QC
TSSOP – Tape and Reel
TSSOP (GREEN)– Tube
TSSOP (GREEN)– Tape and Reel
QFN – Tube
PL66X-XXQC-R
PL66X-XXQCL
PL66X-XXQCL-R
QFN – Tape and Reel
QFN (GREEN)– Tube
QFN (GREEN)– Tape and Reel
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 3/20/07 Page 15
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