PLL103-02XI [PLL]
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS; DDR SDRAM缓存的台式机有4个DDR DIMM内存
| 型号： | PLL103-02XI |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| 文件： | 总6页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
FEATURES
PIN CONFIGURATION
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Generates 24 output buffers from one input.
FBOUT
VDD2.5
GND
DDR0T
DDR0C
DDR1T
DDR1C
VDD2.5
GND
DDR2T
DDR2C
VDD2.5
BUF_IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N/C
VDD2.5
GND
Supports up to four DDR DIMMS.
Supports 266MHz DDR SDRAM.
One additional output for feedback.
Less than 5ns delay.
Skew between any outputs is less than 100 ps.
2.5V Supply range.
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PD#
Enhanced DDR Output Drive selected by I2C.
Available in 48 pin SSOP.
BLOCK DIAGRAM
DDR0T
DDR0C
DDR1T
DDR1C
DDR2T
DDR2C
DDR3T
DDR3C
DDR4T
DDR4C
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
GND
DDR3T
GND
SDATA
I2C
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
Control
SCLK
DDR3C
VDD2.5
GND
DDR4T
DDR4C
DDR5T
DDR5C
VDD2.5
SDATA
BUF_IN
SCLK
Note: #: Active Low
DESCRIPTION
The PLL103-02 is designed as a 2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 24 outputs. These outputs can be
configured to support four unbuffered DDR DIMMS.
The PLL103-02 can be used in conjunction with a
clock synthesizer for the VIA Pro 266 chipset.
The PLL103-02 also has an I2C interface, which can
enable or disable each output clock. When powered
up, all output clocks are enabled (have internal pull
ups).
PD#
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
PIN DESCRIPTIONS
Name
Number
Type
Description
FBOUT
BUF_IN
PD
1
O
I
Feedback clock for chipset.
Reference input from chipset.
13
36
48
I
Power Down Control input. When low, it will tri-state all outputs.
Not connected.
N/C
4,6,10,15,19,
21,28,30,34,
39,43,45
5,7,11,16,20,
22,27,29,33,
38,42,44
DDR[0:11]T
DDR[0:11]C
O
O
These outputs provide True copies of BUF_IN.
These outputs provide complementary copies of BUF_IN.
2,8,12,17,23,
32,37,41,47
3,9,14,18,26,
31,35,40,46
VDD2.5
GND
P
P
2.5V power supply.
Ground.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
I2C BUS CONFIGURATION SETTING
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
_
Address Assignment
Slave
Receiver/Transmitter
Provides both slave write and readback functionality
Data Transfer Rate
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Data Protocol
Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
48
1
0
0
0
1
1
1
1
Reserved
-
Reserved
-
Enhanced DDR Drive. 1 = Enhanced 25%
Reserved
-
45, 44
43, 42
39, 38
34, 33
DDR11T, DDR11C
DDR10T, DDR10C
DDR9T, DDR9C
DDR8T, DDR8C
2. BYTE 7: Outputs Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
30, 29
28, 27
21, 22
19, 20
15, 16
10, 11
6, 7
1
1
1
1
1
1
1
1
DDR7T, DDR7C
DDR6T, DDR6C
DDR5T, DDR5C
DDR4T, DDR4C
DDR3T, DDR3C
DDR2T, DDR2C
DDR1T, DDR1C
DDR0T, DDR0C
4, 5
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 3
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
VSS-0.5
VSS-0.5
-65
V
Output Voltage, dc
VO
TS
TA
TJ
V
Storage Temperature
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Operating Conditions
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD2.5
CIN
2.375
2.625
V
Input Capacitance
Output Capacitance
5
6
pF
pF
COUT
3. Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
All Inputs except I2C
MIN.
TYP.
MAX.
UNITS
2.0
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VIL
IIH
VDD+0.3
0.8
V
V
All inputs except I2C
VIN = VDD
VSS-0.3
TBM
uA
uA
IIL
VIN = 0
TBM
Output High
Voltage
Output Low
Voltage
Output High
Current
Output Low
Current
1.7
VOH
VOL
IOH
IOL = -12mA, VDD = 2.375V
IOL = 12mA, VDD = 2.375V
VDD = 2.375V, VOUT=1V
VDD = 2.375V, VOUT=1.2V
V
V
0.6
-18
26
-32
35
mA
mA
IOL
Note: TBM: To be measured
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 4
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
3. Electrical Specifications (Continued)
PARAMETERS
SYMBOL
IDDS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
mA
Supply Current
Output Crossing
Voltage
PD = 0
TBM
(VDD/2)+
0.1
(VDD/2)
-0.1
VOC
VDD/2
V
Output Voltage
Swing
Duty Cycle
Max. Operating
Frequency
VOUT
DT
1.1
45
66
VDD-0.4
55
V
%
Measured @ 1.5V
50
170
MHz
Rising Edge Rate
Falling Edge Rate
Clock Skew ( pin to
pin )
TOR
TOF
Measured @
Measured @
0.4V ~ 2.4V
2.4V ~ 0.4V
1.0
1.0
1.5
1.5
2.0
2.0
V/ns
V/ns
TSKEW
TST
All outputs equally loaded
100
0.1
ps
Stabilization Time
ms
Note: TBM: To be measured
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 5
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
PACKAGE INFORMATION
0.292 - 0.299
7.417 - 7.959
0.400 - 0.410
10.160 - 10.414
0.008 - 0.0135
0.203 - 0.343
0.025
0.835
0.015
(0.381)
0.088 - 0.096
(2.250 - 2.450)
0.620 - 0.630
(15.75 - 16.00)
0.010 - 0.016
(0.25 - 0.41)
45 0
0.097 - 0.104
(2.467 - 2.642)
30-60
0.050
MIN
0.008 - 0.016
(0.20 - 0.41)
(1.346)
48PIN SSOP
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL103-02 X C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
X=SSOP
Order Number
Marking
Package Option
PLL103-02XC-R
PLL103-02XC
P103-02XC
P103-02XC
SSOP - Tape and Reel
SSOP - Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 6
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