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PLL130-07AOC-R [PLL]

Interface Circuit, PDSO8,;
PLL130-07AOC-R
型号： PLL130-07AOC-R
厂家： PHASELINK CORPORATION    PHASELINK CORPORATION
描述：

Interface Circuit, PDSO8,

光电二极管
文件： 总5页 (文件大小：256K)
中文：  中文翻译
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High Speed Translator Buffer to LVCMOS  
FEATURES  
PIN CONFIGURATION  
(TOP VIEW)  
LVCMOS output  
Selectable Drive capability  
Drive 15pF or 30pF output load  
Single AC coupled input (min. 100mV swing).  
Accepts LVCMOS or Sine Wave inputs.  
Input range from 0 to 200 MHz.  
OE High (PLL130-07) or OE Low (PL130-07A)  
Enable  
GND  
REF_IN  
GND  
DRV_SEL^  
VDD  
1
2
3
4
8
7
6
5
GND  
VDD  
CLK_OUT  
SOP-8L  
2.5V to 3.3V operation.  
Available in 8-Pin SOP, 8-Pin TSSOP and  
VDD  
DRV_SEL  
GND  
CLK_OUT  
VDD  
1
8
3x3mm 16-Pin QFN.  
2
3
4
7
6
5
DNC  
DESCRIPTION  
OE  
FIN  
The PLL130-07 is a low cost, high performance, high  
speed, buffer that reproduces any input frequency  
from 0 to 200MHz. It provides an LVCMOS output  
with 15pF output load drive capability. Any input sig-  
nal with at least 100mV swing can be used as refer-  
ence signal. This chip is ideal for conversion from  
sine wave to LVCMOS.  
TSSOP-8L  
12  
11  
10  
9
13  
8
DRV_SEL  
CLK_OUT  
14  
15  
7
VDD  
N/C  
GND  
GND  
PLL130-07(A)  
6
16  
5
GND  
OE  
1
2
3
4
BLOCK DIAGRAM  
Input  
REF_IN  
CLK_OUT  
Amplifier  
OE  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 1  
High Speed Translator Buffer to LVCMOS  
PIN DESCRIPTION  
Name  
SOP-8L  
TSSOP-8L QFN-16L  
Type  
Description  
1,2,4,5,  
9,14,15  
GND  
VDD  
1,3,6  
4,7  
8
3
P
P
I
Ground.  
1,7  
2
7,10,11,12  
Power supply.  
Drive Select input: ‘1’ for standard drive, ‘0’ for hi-  
drive output. Internal pull-up (default is ‘1’).  
DRV_SEL  
13  
Reference input signal. The frequency of this signal  
will be reproduced at the output (after translation to  
CMOS level).  
REF_IN  
2
5
3
I
CLK_OUT  
OE  
5
8
4
8
O
I
CMOS clock output.  
N/A  
16  
Output Enable. See OE LOGIC TABLE below  
OE LOGIC TABLE  
Part Number  
OE State  
Output Buffer State  
0
Tri-State  
Active  
PLL130-07  
1 (Default)  
0 (Default)  
1
Active  
PLL130-07A  
Tri-State  
ELECTRICAL SPECIFICATIONS  
1. Absolute Maximum Ratings  
PARAMETERS  
Supply Voltage  
SYMBOL  
MIN.  
MAX.  
4.6  
UNITS  
VDD  
VI  
V
Input Voltage, dc  
-0.5  
-0.5  
-65  
VDD+0.5  
VDD+0.5  
150  
V
Output Voltage, dc  
VO  
TS  
TA  
TJ  
V
Storage Temperature  
C  
C  
C  
C  
kV  
Ambient Operating Temperature*  
Junction Temperature  
-40  
85  
125  
Lead Temperature (soldering, 10s)  
ESD Protection, Human Body Model  
260  
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent  
damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the  
device at these or any other conditions above the operational limits noted in this specification is not implied.  
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL  
grade only.  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 2  
High Speed Translator Buffer to LVCMOS  
2. AC Specifications  
PARAMETERS  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
Input Frequency  
Input Signal Swing  
Output Frequency  
0
100  
0
200  
MHz  
mV  
REF_IN input  
200  
MHz  
3. CMOS Output Electrical Specifications  
PARAMETERS  
SYMBOL  
CONDITIONS  
IOH = -12mA  
MIN.  
TYP.  
MAX.  
UNITS  
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
2.4  
V
V
ILO = 12mA  
IOH = -4mA  
0.4  
Output High Voltage at  
CMOS level  
VOHC  
VDD– 0.4  
V
At TTL level (High Drive*)  
36  
12  
51  
17  
mA  
mA  
Output Drive Current  
At TTL level (Standard Drive)  
* Note: High Drive CMOS is selectable through DRIV_SEL selector input on pin 8(SOP) or 13(QFN).  
4. CMOS Switching Characteristics  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
tr / tf  
tr / tf  
tr / tf  
tr / tf  
0.8V ~ 2.0V with 10 pF load  
0.3V ~ 3.0V with 15 pF load  
0.8V ~ 2.0V with 10 pF load  
0.3V ~ 3.0V with 15 pF load  
1.15  
3.7  
Output Clock Rise/Fall  
Time  
ns  
0.5  
Output Clock Rise/Fall  
Time (High Drive*)  
1.5  
* Note: High Drive CMOS is selectable through DRIV_SEL selector input on pin 8(SOIC) or 13(QFN).  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 3  
High Speed Translator Buffer to LVCMOS  
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)  
8 PIN ( dimensions in mm )  
TSSOP  
SOP  
Min.  
-
Max.  
1.20  
0.15  
0.30  
0.20  
3.10  
4.50  
6.60  
0.75  
Symbol  
Min.  
1.47  
0.10  
0.33  
0.19  
4.80  
3.80  
5.80  
0.38  
Max.  
1.73  
0.25  
0.51  
0.25  
4.95  
4.00  
6.20  
1.27  
E
H
A
A1  
B
C
D
E
H
L
0.05  
0.19  
0.09  
2.90  
4.30  
6.20  
0.45  
D
A
A
1
C
e
0.65 BSC  
1.27 BSC  
L
B
e
QFN-16L  
Dimensions in MM  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 4  
High Speed Translator Buffer to LVCMOS  
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)  
For part ordering, please contact our Sales Department:  
47745 Fremont Blvd., Fremont, CA 94538, USA  
Tel: (510) 492-0990 Fax: (510) 492-0991  
PART NUMBER  
The order number for this device is a combination of the following:  
Device number, Package type and Operating temperature range  
PLL130-07(A) X C  
PART NUMBER  
TEMPERATURE  
C=Commercial  
I=Industrial  
PACKAGE TYPE  
O=TSSOP-8L  
Q=QFN-16L  
OE STATE  
None= High Enable  
A=Low Enable  
S=SOP-8L  
Order Number  
Marking  
Package Option  
PLL130-07OC-R  
PLL130-07OC  
P130-07OC  
P130-07OC  
TSSOP - Tape and Reel  
TSSOP – Tube  
PLL130-07AOC-R  
PLL130-07AOC  
P130-07AOC  
P130-07AOC  
TSSOP - Tape and Reel  
TSSOP - Tube  
PLL130-07QC-R  
PLL130-07AQC-R  
P130-07QC  
QFN - Tape and Reel  
QFN - Tape and Reel  
P130-07AQC  
PLL130-07SC-R  
PLL130-07SC  
P130-07SC  
P130-07SC  
SOP -Tape and Reel  
SOP – Tube  
PLL130-07ASC-R  
PLL130-07ASC  
P130-07ASC  
P130-07ASC  
SOP-Tape and Reel  
SOP - Tube  
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-  
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said  
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.  
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-  
press written approval of the President of PhaseLink Corporation.  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/14/07 Page 5  

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