PLL500-17BSIL-R [PLL]
Oscillator;
| 型号： | PLL500-17BSIL-R |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Oscillator |
| 文件： | 总7页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
FEATURES
PIN CONFIGURATION
XIN
OE^
XOUT
DRIVSEL^
VDD
1
2
3
4
8
7
6
5
VCXO output for the 17MHz to 130MHz range
-
-
-
PLL500-17B: 17MHz to 36MHz
PLL500-27B: 27MHz to 65MHz
PLL500-37B: 65MHz to 130MHz
VCON
GND
CLK
Low phase noise.
CMOS output with OE tri-state control.
Selectable output drive
^: Denotes internal Pull-up
-
-
Standard: 8mA drive capability.
High: 24mA drive capability.
DIE PAD LAYOUT
32 mil
(812,986)
Fundamental crystal input.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5V ~ 3.3V operation.
8
XOUT
1
2
XIN
DRIVSEL^
7
OE^
VDD
CLK
6
5
Available in 8-Pin SOP or Die.
VCON
GND
3
4
DESCRIPTION
The PLL500-17B/27B/37B are a low cost, high per-
formance, low phase noise, and high linearity VCXO
family for the 17 to 130MHz range, providing less
than -130dBc/Hz at 10kHz offset. The very low jitter
(2.5 ps RMS period jitter) makes these chips ideal
for applications requiring voltage controlled fre-
quency sources. The IC’s are designed to accept
fundamental resonant mode crystals.
DIE ID:PLL500-17B: C500A-0505-05P
PLL500-27B: C500A-0505-05Q
PLL500-37B: C500A-0505-05R
(0,0)
Y
X
Note: ^ Denotes internal pull up
DIE SPECIFICATIONS
FREQUENCY RANGE
Name
Value
PART #
MULTIPLIER
FREQUENCY
Size
39 x 32 mil
GND
PLL500-17B
PLL500-27B
PLL500-37B
No PLL
No PLL
No PLL
17 – 36 MHz
27 – 65 MHz
65 – 130 MHz
Reverse side
Pad dimensions
Thickness
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
XIN
XTAL
OSC
CLK
XOUT
VARICAP
VCON
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 1
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
PIN AND PAD DESCRIPTION
Die Pad Position
Name
Pin#
Type
Description
X (m)
Y (m)
XIN
1
94.183
768.599
I
Crystal input pin.
Output Enable input pin. Disables the output when pulled
to “0”. Internal pull-up enables output by default if pin is
not connected.
OE
2
94.157
605.029
I
VCON
GND
CLK
3
4
5
6
94.183
94.193
331.756
140.379
203.866
455.726
I
Frequency control voltage input pin.
Ground pin.
P
O
P
715.472
715.307
Clock output pin.
VDD
VDD power supply pin.
Output drive select pin. High drive if set to ‘0’. Standard
drive if set to ‘1’. Internal pull-up.
DRIVSEL
XOUT
7
8
715.472
476.906
626.716
888.881
I
I
Crystal output pin.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, DC
-0.5
-0.5
-65
V
Output Voltage, DC
VO
TS
TA
TJ
V
Storage Temperature
C
C
C
C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 2
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
2. AC Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
PLL500-17B
MIN.
TYP.
MAX. UNITS
17
27
65
36
Input Crystal Frequency
MHz
ns
PLL500-27B
65
PLL500-47B
130
TR/TF
TR/TF
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V (3.3V)
0.8
2.5
50
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
45
55
%
mA
50
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
TVCXOSTB
From power valid
10
ms
XTAL C0/C1 < 250
0V VCON 3.3V
VCXO Tuning Range
300
100
ppm
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
ppm
ppm/V
%
VCON=1.65V, 1.65V
150
5
Frequency change with
VDD varied +/- 10%
Power Supply Rejection
PWSRR
-1
+1
ppm
VCON pin input impedance
2000
k
0V < VCON < 3.3V, -3dB
-17B
-27B
-37B
18
18
25
VCON modulation BW
kHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 3
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
4. Jitter and Phase Noise Specifications
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
RMS Period Jitter
(1 sigma – 10,000 samples)
With capacitive decoupling
between VDD and GND.
2.5
ps
PLL500-17B
Phase Noise relative to carrier at 27MHz
Phase Noise relative to carrier at 27MHz
Phase Noise relative to carrier at 27MHz
Phase Noise relative to carrier at 27MHz
PLL500-27B
@100Hz offset
-100
-125
-142
-150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@1kHz offset
@10kHz offset
@100kHz offset, and 1MHz
Phase Noise relative to carrier at 61.44MHz @100Hz offset
Phase Noise relative to carrier at 61.44MHz @1kHz offset
Phase Noise relative to carrier at 61.44MHz @10kHz offset
Phase Noise relative to carrier at 61.44MHz @100kHz offset, and 1MHz
-100
-125
-142
-150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL500-37B
Phase Noise relative to carrier at 77.76MHz @100Hz offset
Phase Noise relative to carrier at 77.76MHz @1kHz offset
Phase Noise relative to carrier at 77.76MHz @10kHz offset
Phase Noise relative to carrier at 77.76MHz @100kHz offset
Phase Noise relative to carrier at 77.76MHz @1MHz offset
-100
-125
-142
-150
-152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 4
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
5. DC Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
27MHz, 15pF output load, 3.3V
35MHz, 15pF output load, 3.3V
78MHz, 15pF output load, 3.3V
27MHz, 15pF output load, 2.5V
35MHz, 15pF output load, 2.5V
78MHz, 15pF output load, 2.5V
PLL500-17B
3.7
4.2
7.2
2.4
2.8
5.2
5
6
Supply Current,
Dynamic, with
Loaded Outputs
9
IDD
mA
3.5
4
7
30
20
15
10
3.63
pF
pF
pF
pF
V
PLL500-27B
Allowable output load
capacitance
CL
(Output)
PLL500-37B Std drive <100MHz
PLL500-37B High drive
Operating Voltage
Output High Voltage
Output Low Voltage
VDD
VOH
VOL
2.25
2.4
IOH = -8mA, 3.3V Supplies
IOL = 8mA, 3.3V Supplies
V
0.4
V
Output High Voltage
at CMOS level
IOH = -4mA, 3.3V Supplies
VDD – 0.4
V
Standard drive, 3.3V
High drive, 3.3V
8
9.5
27
Output drive current
mA
24
Short Circuit Current
VCXO Control Voltage
mA
V
50
VCON
0
VDD
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 5
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
6. Crystal Specifications
PARAMETERS
SYMBOL
MIN.
TYP.
MAX.
UNITS
Crystal Loading Rating (VCON = 1.65V, PLL500-17B)
Crystal Loading Rating (VCON = 1.65V, PLL500-27B)
Crystal Loading Rating (VCON = 1.65V, PLL500-37B)
Crystal Loading Rating (VCON = 1.25V, PLL500-17B)
Crystal Loading Rating (VCON = 1.25V, PLL500-27B)
Crystal Loading Rating (VCON = 1.25V, PLL500-37B)
Maximum Sustainable Drive Level
Operating Drive Level
7.8
6.3
5.1
8.9
7.2
5.7
CL (xtal)
pF
(see note
below)
200
W
W
50
Max C0 for PLL500-17B
5
pF
Max C0 for PLL500-27B
3.5
2.5
250
30
Max C0 for PLL500-37B
C0/C1
-
ESR
RS
Ω
Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
Note that the Cload values above are for the IC only, and do not include PCB parasitics. Crystal specifications for Cload include PCB parasitics.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 6
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
PACKAGE INFORMATION
SOP 8L
Dimension in MM
Symbol
Min.
1.35
0.10
1.25
0.33
0.19
4.80
3.80
5.80
0.40
Max.
1.75
0.25
1.50
0.53
0.27
5.00
4.00
6.20
0.89
A
A1
A2
B
C
D
E
H
L
e
E
H
D
A2
A
A1
C
L
b
1.27 BSC
e
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
R=Tape & Reel
Blank=Normal Package
L=GREEN Package
D=Die
S=SOP-8L
C=Commercial (0°C to 70°C)
I=Industrial (-40°C to 85°C)
Order Number
Marking
Package Option
PLL500-X7BDC
PLL500-X7BSC
PLL500-X7BSC-R
PLL500-X7BSCL
PLL500-X7BSCL-R
No marking on die
P500-X7B
Die (Waffle Pack)
8-Pin SOP (Tube)
P500-X7B
8-Pin SOP (Tape and Reel)
8-Pin SOP (Tube), GREEN
8-Pin SOP (Tape and Reel) , GREEN
P500-X7B
P500-X7B
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 7
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