PLL500-37BDC [PLL]
Low Power CMOS Output VCXO Family (27MHz to 200MHz); 低功耗CMOS输出VCXO系列（ 27MHz的频率为200MHz ）
| 型号： | PLL500-37BDC |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Low Power CMOS Output VCXO Family (27MHz to 200MHz) |
| 文件： | 总5页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
FEATURES
PIN CONFIGURATION
•
VCXO output for the 27MHz to 200MHz range
-
-
-
PLL500-27: 27MHz to 65MHz
PLL500-37: 65MHz to 130MHz
PLL500-47: 100MHz to 200MHz
XIN
OE^
VIN
XOUT
DS^
1
2
3
4
8
7
6
5
VDD*
CLK
•
•
•
Low phase noise (-130 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable output drive (Standard or High drive).
GND
-
-
Standard: 12mA drive capability at TTL level.
High: 36mA drive capability at TTL level.
^: Denotes internal Pull-up
•
•
•
•
•
•
Fundamental crystal input.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5-3.3V operation.
DIE PAD LAYOUT
8
1
Die ID:
Available in 8-Pin SOIC or DIE.
7
6
PLL500-27B:
2
C500A0505-05P
DESCRIPTION
PLL500-37BDC:
C500A0505-05Q
3
4
The PLL500-27/-37/-47 are a low cost, high perform-
ance, low phase noise, and high linearity VCXO fam-
ily for the 27 to 200MHz range, providing less than -
130dBc at 10kHz offset. The very low jitter (2.5 ps
RMS period jitter) makes these chips ideal for appli-
cations requiring voltage controlled frequency
sources. The IC’s are designed to accept fundamen-
tal resonant mode crystals.
5
PLL500-47BDC:
C500A0505-05R
FREQUENCY RANGE
PART #
MULTIPLIER
No PLL
FREQUENCY
27 – 65 MHz
PLL500-27B
PLL500-37B
PLL500-47B
No PLL
65 – 130 MHz
100 – 200 MHz
No PLL
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 1
PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
PIN AND PAD DESCRIPTION
Die Pad Position
Name
Pin#
Type
Description
X (µm)
Y (µm)
XIN
OE
1
2
94.183
768.599
I
I
Crystal input pin.
Output Enable input pin. Disables the output when low. Internal
pull-up enables output by default if pin is not connected low.
94.157
605.029
VCON
GND
CLK
3
4
5
6
94.183
94.193
331.756
140.379
203.866
455.726
I
Frequency control voltage input pin.
Ground pin.
P
O
P
715.472
715.307
Output clock pin.
VDD
VDD power supply pin.
Output drive select pin. High drive if set to ‘0’. Low drive if set
to ‘1’. Internal pull-up.
DRIVSEL
XOUT
7
8
715.472
476.906
626.716
888.881
I
I
Crystal output pin. Ref clock input.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
Input Voltage Range
4.6
V
V
VCC
VI
-0.5
-0.5
-0.5
VCC+0.5
VCC+0.5
240
Output Voltage Range
Soldering Temperature
Storage Temperature
V
VO
°C
°C
°C
-65
-40
150
TS
Ambient Operating Temperature
+85
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 2
PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
2. AC Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
PLL500-27
MIN.
TYP.
MAX.
UNITS
27
65
65
Input Crystal Frequency
MHz
PLL500-37
130
200
PLL500-47
100
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V
1.15
3.7
ns
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
45
50
55
%
mA
±50
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
ms
From power valid
10
TVCXOSTB
300
ppm
XTAL C0/C1 < 250
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
ppm
ppm/V
%
0V ≤ VCON ≤ 3.3V
±150
100
5
Frequency change with
VDD varied +/- 10%
Power Supply Rejection
PWSRR
-1
+1
ppm
2000
45
VCON pin input impedance
VCON modulation BW
kΩ
kHz
0V ≤ VCON ≤ 3.3V, -3dB
Note: Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not
production tested to any specific limits.
4. Jitter and Phase Noise specification
PARAMETERS
RMS Period Jitter
CONDITIONS
MIN.
TYP.
MAX.
UNITS
With capacitive decoupling
between VDD and GND.
2.5
ps
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
-80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-110
-130
-138
-145
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 3
PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
5. DC Specification
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
FXIN = 36MHz, 15pF output load
FXIN = 77MHz, 15pF output load
FXIN = 155MHz, 15pF output load
PLL500-27
5
6
12
Supply Current, Dynamic,
with Loaded Outputs
IDD
mA
10
15
18
N/A
15
pF
pF
pF
V
Allowable output load
capacitance
CL
(Output)
PLL500-37 and-47: Std drive
PLL500-37 and-47: High drive
10
Operating Voltage
Output High Voltage
Output Low Voltage
VDD
VOH
VOL
2.25
2.4
3.63
IOH = -12mA
IOL = 12mA
V
0.4
V
Output High Voltage at
CMOS level
IOH = -4mA
VDD – 0.4
V
Standard drive at TTL level
High drive at TTL level
12
36
17
51
Output drive current
mA
Short Circuit Current
VCXO Control Voltage
ESD Protection
mA
V
±50
VCON
0
3.3
Human Body Model
2000
V
6. Crystal Specifications
PARAMETERS
SYMBOL
MIN.
TYP.
MAX.
UNITS
Crystal Loading Rating (VCON = 1.65V)
8.5
pF
CL
(xtal)
Maximum Sustainable Drive Level
Operating Drive Level
Max C0 for PLL500-27
Max C0 for PLL500-37
Max C0 for PLL500-47
C0/C1
200
µW
µW
50
3.5
2.5
2
pF
250
-
ESR
RS
30
Ω
Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 4
PLL500-27B/-37B/-47B
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
Narrow SOIC
E
H
Symbol
Min.
1.47
0.10
0.33
0.19
4.80
3.80
5.80
0.38
Max.
1.73
0.25
0.51
0.25
4.95
4.00
6.20
1.27
A
A1
B
C
D
E
D
H
L
A
A
1
C
e
1.27 BSC
L
B
e
ORDERING INFORMATION
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
Order Number
Marking
Package Option
PLL500-27BSC
PLL500-27BSC-R
PLL500-27BDC
PLL500-37BSC
PLL500-37BSC-R
PLL500-37BDC
PLL500-47BSC
PLL500-47BSC-R
PLL500-47BDC
P500-27B SC
P500-27B SC
P500-27B DC
P500-37B SC
P500-37B SC
P500-37B DC
P500-47B SC
P500-47B SC
P500-47B DC
8-Pin SOIC (Tube)
8-Pin SOIC (Tape and Reel)
Die (Waffle Pack)
8-Pin SOIC (Tube)
8-Pin SOIC (Tape and Reel)
Die (Waffle Pack)
8-Pin SOIC (Tube)
8-Pin SOIC (Tape and Reel)
Die (Waffle Pack)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/13/04 Page 5
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