PLL520-30 [PLL]
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal); PECL和LVDS低相位噪声压控石英振荡器（为65-130MHz基金XTAL）
| 型号： | PLL520-30 |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) |
| 文件： | 总7页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
FEATURES
DIE CONFIGURATION
65 mil
(1550,1475)
•
•
•
•
•
•
•
•
•
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 130MHz (no PLL).
Low Injection Power for crystal 50uW.
Complementary outputs: PECL or LVDS.
Selectable OE Logic
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
25
23
21
20
19
18
24
22
17
16
26
15
14
27
28
13
12
29
11
30
31
Thickness 10 mil.
10
9
2
4
5
6
8
1
3
7
DESCRIPTIONS
(0,0)
Y
X
PLL520-30 is a VCXO IC specifically designed to
pull frequency fundamental crystals from 65MHz to
130MHz, with selectable PECL or LVDS outputs and
OE logic (enable high or enable low). Its design was
optimized to tolerate higher limits of interelectrodes
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
DIE SPECIFICATIONS
Name
Value
Size
62 x 65 mil
GND
Reverse side
Pad dimensions
Thickness
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
OUTPUT SELECTION AND ENABLE
Pad #9
Selected Output
OUTSEL
OE
Q
0
1
LVDS
Oscillator
VCON
PECL (default)
Amplifier
w/
Q
X+
X-
integrated
varicaps
Pad #25
OESEL
Pad #30
OE_CTRL
State
0
1
0
1
Tri-state
PLL520-30
0
Output enabled (default)
Output enabled (default)
Tri-state
1
(default)
Pad #9, #25 and #30: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OESEL is “1”
Logical states defined by CMOS levels if OESEL is “0”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 1
Preliminary PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
7
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
Output Voltage, dc
Storage Temperature
VSS-0.5
VSS-0.5
-65
V
VO
TS
TA
TJ
V
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
0
70
125
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
CX+
CX-
C0
2
2
Built-in Capacitance
65MHz to 130MHz
(VDD=3.3V)
pF
Inter-electrode capacitance
C0/C1 ratio (gamma)
2.6
300
130
-
γ
Oscillation Frequency
OF
Fund.
65
MHz
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
VCXO Tuning Range
TVCXOSTB
From power valid
XTAL C0/C1 < 300
10
ms
200*
ppm
0V ≤ VCON ≤ 3.3V
at room temperature
VCON = 0 to 3.3V
CLK output pullability
ppm
±100*
On-chip Varicaps control range
Linearity
4 – 18*
5*
pF
%
10*
VCXO Tuning Characteristic
65
ppm/V
VCON input impedance
VCON modulation BW
60
kΩ
25
kHz
0V ≤ VCON ≤ 3.3V, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 2
Preliminary PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
4. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded Outputs)
Operating Voltage
IDD
PECL/LVDS
100/80
3.47
mA
V
VDD
3.13
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
45
45
50
50
55
55
Output Clock Duty Cycle
Short Circuit Current
%
mA
±50
5. Jitter specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS
77.76MHz
77.76MHz
Integrated 12 kHz to 20 MHz at 77.76MHz
ps
ps
ps
3.5*
24*
Period jitter peak-to-peak
Integrated jitter RMS
0.5*
*: To be measured
6. Phase noise specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz @10kHz @100kHz UNITS
-125 -145 -155 dBc/Hz
Phase Noise
relative to carrier
77.76MHz
-75
-95
Note: Phase Noise at VCON = 0V – to be measured
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 3
Preliminary PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
454
50
UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
∆VOD
VOH
247
-50
355
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
VOL
0.9
1.125
0
V
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
Vout = VDD or GND
VDD = 0V
Power-off Leakage
IOXD
IOSD
uA
±1
±10
Output Short Circuit Current
-5.7
-8
mA
8. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
SYMBOL
CONDITIONS
MIN.
0.2
TYP.
0.7
MAX.
1.0
UNITS
ns
RL = 100 Ω
CL = 10 pF
(see figure)
tr
tf
0.2
0.7
1.0
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50
50
Ω
Ω
VOD
VOS
VDIFF
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 4
Preliminary PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
9. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
Output Low Voltage
VOH
VOL
VDD – 1.025
VDD – 1.900
VDD – 0.750
VDD – 1.620
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
10. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
tr
tf
@20/80% - PECL
@80/20% - PECL
0.3
0.3
0.6
0.5
1.5
1.5
ns
ns
PECL Levels Test Circuit
PECL Output Skew
OUT
VDD
OUT
50
50
Ω
Ω
2.0V
50%
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 5
Preliminary PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
PAD ASSIGNMENT
Pad #
Name
X (µm)
Y (µm)
1
Optional GND
Optional GND
Optional GND
Optional GND
GND
248
361
109
109
2
3
473
109
4
587
109
5
702
109
6
Reserved
874
109
7
Optional GNDBUF
GNDBUF
1042
1171
1400
1400
1400
1400
1400
1400
1400
1400
1389
1232
1042
854
109
8
109
9
OUTSEL
125
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LVDS
259
PECL
476
VDDBUF
616
Optional VDDBUF
PECLB
716
871
LVDSB
1089
1227
1365
1365
1365
1365
1365
1365
1365
1365
1365
1223
1017
858
Not connected
GNDBUF
Reserved
Reserved
Not connected
Optional VDD
Optional VDD
VDD
659
559
459
Optional VDD
OESEL
358
194
XIN
109
XOUT
109
Not connected
Not connected
OE_CTRL
VCON
109
109
646
109
397
109
181
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 6
Preliminary PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
ORDERING INFORMATION
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL520-30 D C
TEMPERATURE
C=COMMERCIAL
PART NUMBER
PACKAGE TYPE
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 7
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