PLL601-15SI [PLL]
Low Phase Noise PLL Clock Multiplier; 低相位噪声PLL时钟乘法器
| 型号： | PLL601-15SI |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Low Phase Noise PLL Clock Multiplier |
| 文件： | 总5页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary PLL601-15
Low Phase Noise PLL Clock Multiplier
FEATURES
PIN CONFIGURATION
·
Full swing CMOS outputs with 25 mA drive
capability at TTL levels.
XIN
GND
GND
GND
XOUT
VDD
VDD
CLK
1
2
3
4
8
7
6
5
·
·
Reference 20-30MHz crystal or clock.
Integrated crystal load capacitor: no external
load capacitor required.
Output clocks up to 150MHz at 3.3V.
Low phase noise (-126dBc/Hz @ 1kHz).
Output Enable function.
·
·
·
·
·
·
·
Low jitter (RMS): 6.4ps (period), 9.4ps (accum.)
Advanced low power sub-micron CMOS process.
3.3V operation.
CRYSTAL RANGE
Available in 8-Pin SOIC or TSSOP.
Multiplier
Xtal range
5x
20-30MHz
DESCRIPTIONS
The PLL601-15 is a low cost, high performance and
low phase noise clock synthesizer. It implements
PhaseLink’s proprietary analog and digital Phase
Locked Loop techniques for a fixed 5x multiplier.
The chip accepts crystal or clock inputs ranging from
20 to 30MHz, and produces outputs clocks up to
150MHz at 3.3V.
BLOCK DIAGRAM
Phase
Locked
Loop
CLK
XIN
XTAL
OSC
XOUT
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/08/02 Page 1
Preliminary PLL601-15
Low Phase Noise PLL Clock Multiplier
PIN DESCRIPTIONS
Name
Number
Type
Description
CLK
VDD
5
O
P
Clock output from VCO. Equals the input frequency times multiplier.
3.3V Power Supply.
7,6
Crystal input to be connected to 20-30MHz fundamental parallel mode crys-
tal (CL=15pF). On chip load capacitors: No external capacitor required.
XIN
1
I
XOUT
GND
8
O
P
Crystal Connection.
Ground.
2, 3,4
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/08/02 Page 2
Preliminary PLL601-15
Low Phase Noise PLL Clock Multiplier
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
7
UNITS
Supply Voltage Range
Input Voltage Range
V
V
VCC
VI
-0.5
-0.5
-0.5
VCC+0.5
Output Voltage Range
Soldering Temperature
Storage Temperature
V
VO
VCC+0.5
260
°C
°C
°C
-65
0
150
TS
Ambient Operating Temperature
70
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
2. AC Specification
PARAMETERS
Input Frequency
CONDITIONS
MIN.
TYP.
MAX.
UNITS
20
30
150
1.5
1.5
55
MHz
MHz
ns
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
At 3.3V
0.8V to 2.0V with no load
2.0V to 0.8V with no load
At VDD/2
ns
45
50
%
With capacitive decoupling
between VDD and GND
Period jitter RMS
6.4
ps
ps
With capacitive decoupling
between VDD and GND
Accumulated jitter RMS
9.4
Phase Noise, relative to carrier, 150Mhz(x5)
Phase Noise, relative to carrier, 150Mhz(x5)
Phase Noise, relative to carrier, 150Mhz(x5)
Phase Noise, relative to carrier, 150Mhz(x5)
100Hz offset, 3.3V
1kHz offset, 3.3V
10kHz offset, 3.3V
100kHz offset, 3.3V
-103
-126
-133
-128
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/08/02 Page 3
Preliminary PLL601-15
Low Phase Noise PLL Clock Multiplier
3. DC Specification
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
VDD
VIH
3.135
2
3.465
V
V
V
V
V
V
V
VIL
0.8
VIH
For XIN pin
VDD/2
VDD/2
(VDD/2) + 1
VIL
For XIN pin
IOH = -25mA
IOL = 25mA
(VDD/2) - 1
VOH
VOL
2.4
0.4
Output High Voltage At
CMOS Level
VOH
IOH = -8mA
No Load
VDD-0.4
V
Operating Supply Current
Short-circuit Current
IDD
IS
35
mA
mA
±120
4. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
Parallel Fundamental Mode
MIN.
20
TYP.
MAX.
UNITS
Crystal Resonator Frequency
30
MHz
FXIN
Crystal Loading Capacitance
Rating
15
pF
CL
(xtal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/08/02 Page 4
Preliminary PLL601-15
Low Phase Noise PLL Clock Multiplier
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
TSSOP
Narrow SOIC
Min.
Min.
-
Max.
1.20
0.15
0.30
0.20
3.10
4.50
6.60
0.75
Symbol
Max.
1.73
0.25
0.51
0.25
4.95
4.00
6.20
1.27
E
H
A
A1
B
1.47
0.10
0.33
0.19
4.80
3.80
5.80
0.38
0.05
0.19
0.09
2.90
4.30
6.20
0.45
C
D
D
E
H
L
A
A1
C
e
0.65 BSC
1.27 BSC
L
B
e
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL601-15 X C
PART NUMBER
TEMPERATURATURE
C=COMMERCIAL
M=MILITARY
I=INDUSTRAL
PACKAGE TYPE
S=SOIC, O=TSSOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/08/02 Page 5
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