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PLL602-10DI [PLL]

96MHz - 400MHz Low Phase Noise XO (for 12 - 25MHz Crystals); 的96MHz - 400MHz的低相位噪声XO （ 12 - 25MHz的晶体）
PLL602-10DI
型号： PLL602-10DI
厂家： PHASELINK CORPORATION    PHASELINK CORPORATION
描述：

96MHz - 400MHz Low Phase Noise XO (for 12 - 25MHz Crystals)
的96MHz - 400MHz的低相位噪声XO （ 12 - 25MHz的晶体）

晶体 石英晶振
文件： 总7页 (文件大小：119K)
中文：  中文翻译
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Preliminary PLL602-10  
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)  
FEATURES  
DIE CONFIGURATION  
65 mil  
(1550,1475)  
·
Low phase noise output for the 96MHz to  
400MHz range (-134 dBc at 10kHz offset).  
Selectable CMOS, PECL and LVDS output.  
12 to 25MHz crystal input.  
Output Enable selector.  
3.3V operation.  
25  
24 23  
21  
20  
19  
18  
17  
16  
22  
26  
·
·
·
·
·
15  
14  
27  
28  
13  
12  
29  
Available in DIE (65 mil x 62 mil).  
11  
30  
31  
DESCRIPTIONS  
10  
9
2
4
5
6
8
1
3
7
The PLL602-10 is a monolithic low jitter and low  
phase noise (-134dBc/Hz @ 10kHz offset) XO IC  
Die, with CMOS, LVDS and PECL output, for 96MHz  
to 400MHz output range, using a low frequency  
crystal.  
(0,0)  
Y
X
MULTIPLIER SELECTION  
The same die can be used as a XO with output  
frequencies ranging from FXIN x 8 to FXIN x 16 thanks  
to selector pads allowing bonding options (see  
Divider Selection Table on this page). This makes  
the PLL602-10 ideal for a wide range of applications.  
MULTIPLIER  
OUTPUT RANGE  
Pad #19  
0
1
FXIN x 16  
FXIN x 8  
192 – 400 MHz  
96 – 200 MHz  
Note: Selector pad defaults to ‘1’, wire bond to GND to set to ‘0’  
DIE SPECIFICATIONS  
OUTPUT SELECTION AND ENABLE  
Name  
Value  
Pad #18  
OUTSEL1  
Pad #25  
OUTSEL0  
Selected Output  
Size  
62 x 65 mil  
GND  
Reverse side  
0
0
1
1
0
1
0
High Drive CMOS  
Standard CMOS  
PECL  
Pad dimensions  
Thickness  
80 micron x 80 micron  
10 mil  
1
LVDS  
OE (Pad #30)  
State  
Tri-state  
0
1 (Default)  
Output enabled  
BLOCK DIAGRAM  
VCO  
Divider  
CLKBAR  
CLK  
Reference  
SELECT  
Phase  
Comparator  
Charge  
Pump  
Loop  
Filter  
VCO  
OE  
Divider  
XIN  
XTAL  
OSC  
XOUT  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 11/06/02 Page 1  
Preliminary PLL602-10  
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)  
ELECTRICAL SPECIFICATIONS  
1. Absolute Maximum Ratings  
PARAMETERS  
SYMBOL  
MIN.  
MAX.  
UNITS  
Supply Voltage  
7
V
VDD  
VI  
Input Voltage, dc  
Output Voltage, dc  
Storage Temperature  
V
VSS-0.5  
VSS-0.5  
-65  
VDD+0.5  
VDD+0.5  
150  
V
VO  
TS  
TA  
TJ  
°C  
°C  
°C  
°C  
kV  
Ambient Operating Temperature  
Junction Temperature  
0
70  
125  
Lead Temperature (soldering, 10s)  
Input Static Discharge Voltage Protection  
260  
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the  
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other  
conditions above the operational limits noted in this specification is not implied.  
2. Crystal Specifications  
PARAMETERS  
Crystal Resonator  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
Parallel Fundamental  
Mode  
12  
25  
MHz  
FXIN  
Frequency  
Crystal Loading Rating  
Recommended ESR  
TBD  
pF  
CL (xtal)  
RE  
AT cut  
30  
W
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 11/06/02 Page 2  
Preliminary PLL602-10  
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)  
3. General Electrical Specifications  
PARAMETERS  
SYMBOL  
CONDITIONS  
PECL/LVDS/CMOS  
MIN.  
TYP.  
MAX.  
UNITS  
Supply Current, Dynamic  
(with Loaded Outputs)  
IDD  
80/60/35  
3.47  
mA  
V
Operating Voltage  
VDD  
3.13  
@ 1.4V (CMOS)  
@ 1.25V (LVDS)  
@ Vdd – 1.3V (PECL)  
45  
45  
45  
50  
50  
50  
55  
55  
55  
Output Clock Duty Cycle  
Short Circuit Current  
%
mA  
±50  
4. Jitter and Phase Noise specification  
PARAMETERS CONDITIONS  
Period jitter RMS  
MIN.  
TYP.  
MAX.  
UNITS  
With capacitive decoupling  
between VDD and GND.  
7
ps  
ps  
With capacitive decoupling  
between VDD and GND. Over  
10,000 cycles.  
Accumulated jitter RMS  
11  
Phase Noise relative to carrier  
Phase Noise relative to carrier  
Phase Noise relative to carrier  
Phase Noise relative to carrier  
155MHz @100Hz offset  
155MHz @1kHz offset  
155MHz @10kHz offset  
155MHz @100kHz offset  
-90  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
-114  
-134  
-134  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 11/06/02 Page 3  
Preliminary PLL602-10  
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)  
5. LVDS Electrical Characteristics  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
Output Differential Voltage  
VDD Magnitude Change  
Output High Voltage  
Output Low Voltage  
Offset Voltage  
VOD  
DVOD  
VOH  
247  
-50  
355  
454  
50  
mV  
mV  
V
1.4  
1.1  
1.2  
3
1.6  
RL = 100 W  
(see figure)  
VOL  
0.9  
1.125  
0
V
VOS  
1.375  
25  
V
Offset Magnitude Change  
mV  
DVOS  
Vout = VDD or GND  
VDD = 0V  
Power-off Leakage  
IOXD  
IOSD  
uA  
±1  
±10  
Output Short Circuit Current  
-5.7  
-8  
mA  
6. LVDS Switching Characteristics  
PARAMETERS  
Differential Clock Rise Time  
Differential Clock Fall Time  
SYMBOL  
CONDITIONS  
MIN.  
0.2  
TYP.  
0.7  
MAX.  
1.0  
UNITS  
ns  
RL = 100 W  
CL = 10 pF  
(see figure)  
tr  
tf  
0.2  
0.7  
1.0  
ns  
LVDS Levels Test Circuit  
LVDS Switching Test Circuit  
OUT  
OUT  
CL = 10pF  
50  
50  
W
W
VOD  
VOS  
VDIFF  
RL = 100W  
CL = 10pF  
OUT  
OUT  
LVDS Transistion Time Waveform  
OUT  
OUT  
0V (Differential)  
80%  
80%  
VDIFF  
0V  
20%  
20%  
tR  
tF  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 11/06/02 Page 4  
Preliminary PLL602-10  
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)  
7. PECL Electrical Characteristics  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
MAX.  
UNITS  
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
VDD – 1.025  
V
V
RL = 50 W to (VDD – 2V)  
(see figure)  
VDD – 1.620  
8. PECL Switching Characteristics  
PARAMETERS  
Clock Rise Time  
Clock Fall Time  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
tr  
tf  
@20/80% - PECL  
@80/20% - PECL  
0.6  
0.5  
1.5  
1.5  
ns  
ns  
PECL Levels Test Circuit  
PECL Output Skew  
OUT  
VDD  
OUT  
50  
W
W
2.0V  
50%  
50  
OUT  
tSKEW  
OUT  
PECL Transistion Time Waveform  
DUTY CYCLE  
45 - 55%  
55 - 45%  
OUT  
80%  
50%  
20%  
OUT  
tR  
tF  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 11/06/02 Page 5  
Preliminary PLL602-10  
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)  
PAD ASSIGNMENT  
Pad #  
Name  
X (mm)  
Y (mm)  
1
GND  
GND  
248  
361  
109  
109  
2
3
GND  
473  
109  
4
GND  
587  
109  
5
GND  
702  
109  
6
N/C  
874  
109  
7
GND  
1042  
1171  
1400  
1400  
1400  
1400  
1400  
1400  
1400  
1400  
1389  
1232  
1042  
854  
109  
8
GNDBUF  
CMOS  
LVDS  
PECL  
VDDBUF  
VDDBUF  
PECLB  
LVDSB  
CMOSB  
GNDBUF  
OUTSEL1  
FSEL  
N/C  
109  
9
125  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
259  
476  
616  
716  
871  
1089  
1227  
1365  
1365  
1365  
1365  
1365  
1365  
1365  
1365  
1365  
1223  
1017  
858  
VDD  
659  
VDD  
559  
VDD  
459  
VDD  
358  
OUTSEL0  
XIN  
194  
109  
XOUT  
N/C  
109  
109  
N/C  
109  
646  
OE  
109  
397  
N/C  
109  
181  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 11/06/02 Page 6  
Preliminary PLL602-10  
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)  
ORDERING INFORMATION  
For part ordering, please contact our Sales Department:  
47745 Fremont Blvd., Fremont, CA 94538, USA  
Tel: (510) 492-0990 Fax: (510) 492-0991  
PART NUMBER  
The order number for this device is a combination of the following:  
Device number, Package type and Operating temperature range  
PLL602-10 D C  
TEMPERATURATRE  
C=COMMERCIAL  
M=MILITARY  
PART NUMBER  
I=INDUSTRAL  
PACKAGE TYPE  
D=DIE  
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information  
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said  
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.  
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the  
express written approval of the President of PhaseLink Corporation.  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 11/06/02 Page 7  

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