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PLL620-09OCL [PLL]

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal); 低相位噪声XO与乘数（用于100-200MHz基金或3rdOT XTAL）
PLL620-09OCL
型号： PLL620-09OCL
厂家： PHASELINK CORPORATION    PHASELINK CORPORATION
描述：

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
低相位噪声XO与乘数（用于100-200MHz基金或3rdOT XTAL）

石英晶振
文件： 总8页 (文件大小：265K)
中文：  中文翻译
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PLL620-05/-06/-07/-08/-09  
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)  
Universal Low Phase Noise IC’s  
FEATURES  
PIN CONFIGURATION  
(Top View)  
•
100MHz to 200MHz Fundamental or 3rd  
Overtone Crystal.  
VDD  
XIN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
SEL0^  
SEL1^  
GND  
•
Output range: 100 – 200MHz (no multiplication),  
200 – 400MHz (2x multiplier), 400 – 700MHz (4x  
multiplier), or 800MHz-1GHz(PLL620-09 only, 8x  
multiplier).  
CMOS (Standard drive PLL620-07 or Selectable  
Drive PLL620-06), PECL (Enable low PLL620-08  
or Enable high PLL620-05) or LVDS output  
(PLL620-09).  
XOUT  
SEL3^  
SEL2^  
OE  
•
CLKC  
VDD  
CLKT  
GND  
•
•
Supports 3.3V-Power Supply.  
GND  
GND  
Available in 16-Pin (TSSOP or 3x3mm QFN)  
Note: PLL620-06 only available in 3x3mm.  
Note: PLL620-07 only available in TSSOP.  
GND  
DESCRIPTION  
The PLL620-0x family of XO IC’s is specifically  
designed to work with high frequency fundamental  
and third overtone crystals. Their low jitter and low  
phase noise performance make them well suited for  
high frequency XO requirements. They achieve very  
low current into the crystal resulting in better overall  
stability.  
12  
11  
10  
9
13  
8
7
6
5
XIN  
GND  
CLKC  
VDD  
14 PLL620-0x  
XOUT  
SEL2^  
15  
16  
CLKT  
OE  
1
2
3
4
^: Internal pull-up  
*: PLL620-06 pin 12 is output drive select (DRIVSEL)  
(0 for High Drive CMOS, 1 for Standard Drive CMOS)  
The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.  
BLOCK DIAGRAM  
SEL  
OUTPUT ENABLE LOGICAL LEVELS  
OE  
PLL  
Part #  
OE  
State  
Q
(Phase  
0
Output enabled  
Locked  
(Default)  
Q
PLL620-08  
Oscillator  
Loop)  
1
0
Tri-state  
Tri-state  
Amplifier  
X+  
X-  
PLL620-05  
PLL620-06  
PLL620-07  
PLL620-09  
1
PLL by-pass  
Output enabled  
(Default)  
OE input: Logical states defined by PECL levels for PLL620-08  
Logical states defined by CMOS levels for PLL620-05/-06/-  
07/-09  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 1  
PLL620-05/-06/-07/-08/-09  
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)  
Universal Low Phase Noise IC’s  
PIN DESCRIPTIONS  
3x3mm QFN*  
Pin number  
TSSOP*  
Pin number  
Name  
Type  
Description  
VDD  
XIN  
1, 12  
6,11  
13  
P
I
+3.3V power supply.  
2
Crystal input. See Crystal Specification on page 3.  
Crystal output. See Crystal Specification on page 3.  
Output enable.  
XOUT  
OE  
3
14  
I
6
16  
I
GND  
7,8,9, 10, 14  
1,2,3,4,8  
P
Ground (except pin 12 on PLL620-06: DRIVSEL see below).  
PLL620-06 only: Drive Select Input. This pin has an internal  
pull-up that will default DRIVSEL to ‘1’ when not connect to  
GND. CMOS output of PLL620-06 will be high drive CMOS  
when DRIVSEL is set to ‘0’, and will be standard CMOS  
otherwise. The pin remains ‘Do Not Connect (DNC)’ for  
PLL620-05/07/08/09.  
DRIVSEL**  
-
12  
I
True output PECL (PLL620-08) or LVDS (PLL620-09)  
(N/C for PLL620-07)  
Complementary output PECL (PLL620-08) or LVDS (PLL620-  
09)  
CLKT  
CLKC  
11  
13  
5
7
O
O
(CMOS out for PLL620-07).  
SEL0  
SEL1  
SEL2  
SEL3  
16  
15  
5
10  
I
I
I
I
9
15  
Multiplier selector pins. These pins have an internal pull-up  
that will default SEL to ‘1’ when not connected to GND.  
4
Not available  
* Note: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP.  
** Note: DRIVSEL on pin 12 on PLL620-06 only. The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.  
FREQUENCY SELECTION TABLE  
SEL3  
SEL2  
SEL1  
SEL0  
Selected Multiplier  
Fin x 8(PLL620-09 only)  
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
Fin x 4  
Fin x 2  
No multiplication  
Note: SEL3 is not available (always “1”) in 3x3mm package  
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 2  
PLL620-05/-06/-07/-08/-09  
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)  
Universal Low Phase Noise IC’s  
ELECTRICAL SPECIFICATIONS  
1. Absolute Maximum Ratings  
PARAMETERS  
SYMBOL  
MIN.  
MAX.  
UNITS  
Supply Voltage  
VDD  
VI  
4.6  
VDD+0.5  
VDD+0.5  
150  
V
Input Voltage, dc  
Output Voltage, dc  
Storage Temperature  
-0.5  
-0.5  
-65  
V
VO  
TS  
TA  
TJ  
V
°C  
°C  
°C  
°C  
kV  
Ambient Operating Temperature*  
Junction Temperature  
-40  
85  
125  
Lead Temperature (soldering, 10s)  
ESD Protection, Human Body Model  
260  
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the  
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other  
conditions above the operational limits noted in this specification is not implied.  
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.  
2. Crystal Specifications  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
Fundamental or 3rd  
overtone*  
Crystal Resonator Frequency  
FXIN  
100  
200  
MHz  
Crystal Loading Rating  
Interelectrode Capacitance  
Recommended ESR  
CL (xtal)  
C0  
5
pF  
pF  
Ω
5
RE  
AT cut  
30  
* Note: 3rd overtone crystals require an external resistor between XIN and XOUT to prevent the fundamental from oscillating.  
3. General Electrical Specifications  
PARAMETERS  
SYMBOL  
CONDITIONS  
PECL/LVDS/CMOS  
MIN.  
TYP.  
MAX.  
UNITS  
Supply Current (Loaded  
Outputs)  
Operating Voltage  
IDD  
100/80/40  
3.63  
mA  
V
VDD  
2.97  
@ 50% VDD (CMOS)  
@ 1.25V (LVDS)  
@ VDD – 1.3V (PECL)  
45  
45  
45  
50  
50  
50  
55  
55  
55  
Output Clock Duty Cycle  
Short Circuit Current  
%
mA  
±50  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 3  
PLL620-05/-06/-07/-08/-09  
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)  
Universal Low Phase Noise IC’s  
4. Jitter Specifications  
PARAMETERS  
CONDITIONS  
MIN.  
TYP.  
2.5  
MAX.  
UNITS  
At 155.52MHz, with capacitive decoupling  
between VDD and GND. Over 10,000  
cycles  
At 155.52MHz, with capacitive decoupling  
between VDD and GND. Over 1,000,000  
cycles.  
Period jitter RMS  
ps  
Period jitter peak-to-peak  
Accumulated jitter RMS  
Accumulated jitter peak-to-peak  
18.5  
2.5  
20  
ps  
24  
27  
0.4  
49  
Random Jitter  
“RJ” measured on Wavecrest SIA 3000  
Integrated 12 kHz to 20 MHz  
2.5  
0.3  
11  
ps  
ps  
Integrated jitter RMS at 155MHz  
Period jitter RMS  
At 622.08MHz, with capacitive decoupling  
between VDD and GND. Over 10,000  
cycles  
At 622.08MHz, with capacitive decoupling  
between VDD and GND. Over 1,000,000  
cycles.  
ps  
ps  
Period jitter peak-to-peak  
Accumulated jitter RMS  
45  
11  
24  
Accumulated jitter peak-to-peak  
27  
Random Jitter  
“RJ” measured on Wavecrest SIA 3000  
Integrated 12 kHz to 20 MHz  
3
ps  
ps  
Integrated jitter RMS at 622MHz  
1.6  
1.8  
5. Phase Noise Specifications  
PARAMETERS  
FREQUENCY  
@10Hz  
@100Hz  
@1kHz @10kHz @100kHz UNITS  
155.52MHz  
622.08MHz  
-75  
-75  
-95  
-95  
-125  
-110  
-140  
-125  
-145  
-120  
Phase Noise relative  
to carrier  
dBc/Hz  
6. CMOS Electrical Specifications  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
mA  
IOH  
IOL  
IOH  
IOL  
VOH= VDD-0.4V, VDD=3.3V  
VOL = 0.4V, VDD = 3.3V  
VOH= VDD-0.4V, VDD=3.3V  
VOL = 0.4V, VDD = 3.3V  
30  
30  
10  
10  
Output drive current  
(High Drive)  
mA  
mA  
Output drive current  
(Standard Drive)  
mA  
Output Clock Rise/Fall Time  
(Standard Drive)  
Output Clock Rise/Fall Time  
(High Drive)  
0.3V ~ 3.0V with 15 pF load  
0.3V ~ 3.0V with 15 pF load  
2.4  
1.2  
ns  
* Note: High Drive CMOS is available on PLL620-06 through DRIVSEL selector input on pin 12.  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 4  
PLL620-05/-06/-07/-08/-09  
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)  
Universal Low Phase Noise IC’s  
7. LVDS Electrical Characteristics  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
Output Differential Voltage  
VDD Magnitude Change  
Output High Voltage  
Output Low Voltage  
Offset Voltage  
VOD  
∆VOD  
VOH  
247  
-50  
355  
454  
50  
mV  
mV  
V
1.4  
1.1  
1.2  
3
1.6  
RL = 100 Ω  
(see figure)  
VOL  
0.9  
1.125  
0
V
VOS  
1.375  
25  
V
Offset Magnitude Change  
mV  
∆VOS  
Vout = VDD or GND  
VDD = 0V  
Power-off Leakage  
IOXD  
IOSD  
uA  
±1  
±10  
Output Short Circuit Current  
-5.7  
-8  
mA  
8. LVDS Switching Characteristics  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
RL = 100 Ω  
CL = 10 pF  
(see figure)  
Differential Clock Rise Time  
Differential Clock Fall Time  
tr  
tf  
0.2  
0.2  
0.7  
0.7  
1.0  
1.0  
ns  
ns  
LVDS Levels Test Circuit  
LVDS Switching Test Circuit  
OUT  
OUT  
CL = 10pF  
50  
50  
Ω
Ω
VOD  
VOS  
VDIFF  
RL = 100Ω  
CL = 10pF  
OUT  
OUT  
LVDS Transistion Time Waveform  
OUT  
OUT  
0V (Differential)  
80%  
80%  
VDIFF  
0V  
20%  
20%  
tR  
tF  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 5  
PLL620-05/-06/-07/-08/-09  
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)  
Universal Low Phase Noise IC’s  
9. PECL Electrical Characteristics  
PARAMETERS  
SYMBOL  
CONDITIONS  
MIN.  
MAX.  
UNITS  
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
VDD – 1.025  
V
V
RL = 50 Ω to (VDD – 2V)  
(see figure)  
VDD – 1.620  
19. PECL Switching Characteristics  
PARAMETERS  
Clock Rise Time  
Clock Fall Time  
SYMBOL  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNITS  
tr  
tf  
@20/80% - PECL  
@80/20% - PECL  
0.6  
0.5  
1.5  
1.5  
ns  
ns  
PECL Levels Test Circuit  
PECL Output Skew  
OUT  
VDD  
OUT  
50  
50  
Ω
Ω
2.0V  
50%  
OUT  
tSKEW  
OUT  
PECL Transistion Time Waveform  
DUTY CYCLE  
45 - 55%  
55 - 45%  
OUT  
80%  
50%  
20%  
OUT  
tR  
tF  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 6  
PLL620-05/-06/-07/-08/-09  
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)  
Universal Low Phase Noise IC’s  
PACKAGE INFORMATION  
16 PIN TSSOP ( mm )  
Symbol  
Min.  
-
Max.  
1.20  
0.15  
0.30  
0.20  
5.10  
4.50  
E
H
A
A1  
B
C
D
E
0.05  
0.19  
0.09  
4.90  
4.30  
D
A
H
L
e
A1  
C
L
B
e
3mm x 3mm, QFN  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 7  
PLL620-05/-06/-07/-08/-09  
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)  
Universal Low Phase Noise IC’s  
ORDERING INFORMATION  
For part ordering, please contact our Sales Department:  
47745 Fremont Blvd., Fremont, CA 94538, USA  
Tel: (510) 492-0990 Fax: (510) 492-0991  
PART NUMBER  
The order number for this device is a combination of the following:  
Device number, Package type and Operating temperature range  
PLL620-0X X X X X  
NONE= TUBE  
PART NUMBER  
R=TAPE AND  
NONE=NORMAL PACKAGE  
L=GREEN PACKAGE  
PACKAGE TYPE  
X=SSOP  
TEMPERATURE  
C=COMMERCIAL  
I=INDUSTRIAL  
Order Number  
PLL620-05OC  
Marking  
Package Option  
Order Number  
PLL620-08OC  
Marking  
Package Option  
P620-05OC  
P620-05OC  
P620-05OCL  
P620-05OCL  
P620-05QC  
P620-05QC  
P620-05QCL  
P620-05QCL  
P620-06QC  
P620-06QC  
P620-06QCL  
P620-06QCL  
P620-07OC  
P620-07OC  
P620-07OCL  
P620-07OCL  
TSSOP – Tube  
P620-08OC  
P620-08OC  
TSSOP – Tube  
PLL620-05OC-R  
PLL620-05OCL  
PLL620-05OCL-R  
PLL620-05QC  
TSSOP – Tape & Reel  
TSSOP – Tube, GREEN  
TSSOP – Tape & Reel, GREEN  
QFN – Tube  
PLL620-08OC-R  
PLL620-08OCL  
PLL620-08OCL-R  
PLL620-08QC  
TSSOP – Tape & Reel  
P620-08OCL TSSOP – Tube, GREEN  
P620-08OCL TSSOP – Tape & Reel, GREEN  
P620-08QC  
P620-08QC  
QFN – Tube  
PLL620-05QC-R  
PLL620-05QCL  
PLL620-05QCL-R  
PLL620-06QC  
QFN – Tape & Reel  
PLL620-08QC-R  
PLL620-08QCL  
PLL620-08QCL-R  
PLL620-09OC  
QFN – Tape & Reel  
QFN – Tube, GREEN  
QFN – Tape & Reel, GREEN  
QFN – Tube  
P620-08QCL QFN – Tube, GREEN  
P620-08QCL QFN – Tape & Reel, GREEN  
P620-09OC  
P620-09OC  
TSSOP – Tube  
PLL620-06QC-R  
PLL620-06QCL  
PLL620-06QCL-R  
PLL620-07OC  
QFN – Tape & Reel  
PLL620-09OC-R  
PLL620-09OCL  
PLL620-09OCL-R  
PLL620-09QC  
TSSOP – Tape & Reel  
QFN – Tube, GREEN  
QFN – Tape & Reel, GREEN  
TSSOP – Tube  
P620-09OCL TSSOP – Tube, GREEN  
P620-09OCL TSSOP – Tape & Reel, GREEN  
P620-09QC  
P620-09QC  
QFN – Tube  
PLL620-07OC-R  
PLL620-07OCL  
PLL620-07OCL-R  
TSSOP – Tape & Reel  
TSSOP – Tube, GREEN  
TSSOP – Tape & Reel, GREEN  
PLL620-09QC-R  
PLL620-09QCL  
PLL620-09QCL-R  
QFN – Tape & Reel  
P620-09QCL QFN – Tube, GREEN  
P620-09QCL QFN – Tape & Reel, GREEN  
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information  
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said  
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.  
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the  
express written approval of the President of PhaseLink Corporation.  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 8  

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