PLL620-80 [PLL]
Low Phase Noise XO (9.5-65MHz Output); 低相位噪声XO （ 9.5-65MHz输出）
| 型号： | PLL620-80 |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Low Phase Noise XO (9.5-65MHz Output) |
| 文件： | 总7页 (文件大小：813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
DIE CONFIGURATION
FEATURES
65 mil
•
•
•
•
19MHz to 65MHz crystal input.
Output range: 9.5MHz – 65MHz
Selectable OE Logic (enable high or enable low).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Supports 2.5V or 3.3V Power Supply.
Available in die form.
(1550,1475)
25
24 23
22 21
20
19
18
17
16
GNDBUF
CMOS
26
XIN
Die ID:
A2020-20B
•
•
15
14
LVDSB
PECLB
27
28
XOUT
N/C
13
12
VDDBUF
VDDBUF
DESCRIPTION
S2^
29
The PLL620-80 is a XO IC specifically designed to
work with fundamental or 3rd OT crystals between
19MHz and 65MHz. The selectable divide by two
feature extends the operation range from 9.5MHz to
65MHz. It requires very low current into the crystal
resulting in better overall stability. The OE logic
feature allows selection of enable high or enable low.
Furthermore, it provides selectable CMOS, PECL or
LVDS outputs.
11
PECL
OE
CTRL
30
31
10
9
LVDS
C502A
N/C
OE_SEL^
2
3
4
5
6
7
8
1
(0,0)
Y
X
OUTPUT SELECTION AND ENABLE
OUT_SEL1* OUT_SEL0*
Selected Output*
(Pad 18)
(Pad 25)
DIE SPECIFICATIONS
0
0
1
1
0
1
0
1
High Drive CMOS
Standard CMOS
LVDS
Name
Value
Size
62 x 65 mil
GND
Reverse side
Pad dimensions
Thickness
PECL (default)
80 micron x 80 micron
10 mil
OE_SELECT
(Pad 9)
OE_CTRL
(Pad 30)
State
0
Tri-state
0
1 (Default) Output enabled
0 (Default) Output enabled
BLOCK DIAGRAM
1 (Default)
1
Tri-state
OE
Q
Pads #9, #18 & #25: Bond to GND to set to “0”,
No connection results to “default” setting
through internal pull-up.
OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
Q
Oscillator
Amplifier
XIN
OUTPUT FREQUENCY SELECTOR
S2
XOUT
S2
Output
PLL620-80
0
Input/2
Input
1(Default)*
*Internally set to ‘Default’ through 60KΩ pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 1
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
-0.5
-0.5
-65
V
Output Voltage, dc
VO
TS
TA
TJ
V
Storage Temperature
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
-40
85
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
Crystal Loading Rating
Interelectrode Capacitance
Recommended ESR
FXIN
CL (xtal)
C0
Fundamental
19
65
MHz
pF
Die
8*
5
pF
RE
AT cut
30
Ω
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific
limits.
3. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded Outputs)
Operating Voltage
IDD
PECL/LVDS/CMOS
100/80/40
3.63
mA
V
VDD
2.97
@ 50% VDD (CMOS)
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
45
45
45
50
50
50
55
55
55
Output Clock Duty Cycle
Short Circuit Current
%
mA
±50
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 2
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
4. Jitter Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
20
UNITS
Period jitter RMS at 27MHz
2.3
18.5
2.3
With capacitive decoupling between
VDD and GND. Over 10,000 cycles
ps
Period jitter peak-to-peak at 27MHz
Accumulated jitter RMS at 27MHz
With capacitive decoupling between
VDD and GND. Over 1,000,000
cycles.
ps
ps
Accumulated jitter peak-to-peak at 27MHz
Random Jitter
24
25
“RJ” measured on Wavecrest SIA
2.3
3000
Measured on Wavecrest SIA 3000
5. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz @10kHz @100kHz UNITS
Phase Noise relative
to carrier
27MHz
-75
-100
-125
-140
-145
dBc/Hz
Note: Phase Noise measured on Agilent E5500
6. CMOS Output Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
IOH
IOL
IOH
IOL
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
30
30
10
10
mA
mA
mA
mA
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
2.4
1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 3
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
247
-50
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
∆VOD
VOH
355
454
50
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
0.9
1.125
0
VOL
V
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
Vout = VDD or GND
VDD = 0V
Power-off Leakage
IOXD
IOSD
uA
±1
±10
Output Short Circuit Current
-5.7
-8
mA
8. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
RL = 100 Ω
CL = 10 pF
(see figure)
Differential Clock Rise Time
Differential Clock Fall Time
tr
tf
0.2
0.2
0.7
0.7
1.0
1.0
ns
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50
50
Ω
Ω
VOD
VOS
VDIFF
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 4
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
9. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
Output Low Voltage
VOH
VOL
VDD – 1.025
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
VDD – 1.620
10. PECL Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Clock Rise Time
Clock Fall Time
tr
tf
@20/80% - PECL
@80/20% - PECL
0.6
0.5
1.5
1.5
ns
ns
PECL Levels Test Circuit
PECL Output Skew
OUT
VDD
OUT
50
50
Ω
Ω
2.0V
50%
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 5
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
PAD DESCRIPTIONS
Pad #
Name
Description
X (µm)
Y (µm)
1
2
3
4
5
6
7
8
GND
GND
248
361
109
109
109
109
109
109
109
109
Ground.
Ground.
Optional GND
GND
473
Optional Ground.
Ground.
587
GND
702
Ground.
Reserved
GNDBUF
GNDBUF
874
Reserved for future use.
Ground, buffer circuitry.
Ground, buffer circuitry.
1042
1171
This is the selector input to choose the OE control
logic. See the OE SELECTION AND ENABLE table
on page 1. Internal pull up.
9
OE_SEL
1400
125
10
11
12
13
14
15
16
17
LVDS
PECL
1400
1400
1400
1400
1400
1400
1400
1389
259
476
LVDS output.
PECL output.
VDDBUF
VDDBUF
PECLB
LVDSB
CMOS
616
Power supply, buffer circuitry.
Power supply, buffer circuitry.
Complementary PECL output.
Complementary LVDS output.
CMOS output.
716
871
1089
1227
1365
GNDBUF
Ground, buffer circuitry.
Selector input to choose the selected output type
(PECL, LVDS, CMOS). See the OUTPUT SELECTION
AND ENABLE table on page 1. Internal pull up.
18
OUTSEL1
1232
1365
19
20
21
22
23
24
Reserved
Not connected
VDD
1042
854
659
559
459
358
1365
1365
1365
1365
1365
1365
Reserved for future use.
Not Connected.
Power supply.
Optional VDD
VDD
Optional Power supply.
Power supply.
VDD
Power supply.
Selector input to choose the selected output type
(PECL, LVDS, CMOS). See the OUTPUT SELECTION
AND ENABLE table on page 1. Internal pull up.
25
OUTSEL0
194
1365
26
27
28
XIN
XOUT
109
109
109
1223
1017
858
Crystal input. See Crystal Specifications on page 3.
Crystal output. See Crystal Specifications on page 3.
Not Connected.
Not connected
Output Divide by Two selector pin, as presented on
the OUTPUT FREQUENCY SELECTOR Table on
page 1. Internal pull up.
29
S2
109
646
Used to enable/disable the output(s). See Output
30
31
OE_CTRL
109
109
397
181
Selection and Enable table on page 1.
Not connected
Not connected.
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 6
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL620-80 DC
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
PACKAGE TYPE
D=DIE
Order Number
PLL620-80DC
Marking
Package Option
P620-80DC
Die – Waffle Pack
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 7
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