PLL702-06SC-R [PLL]
Clock Generator for Printer Applications; 时钟发生器的打印机应用
| 型号： | PLL702-06SC-R |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Clock Generator for Printer Applications |
| 文件： | 总8页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL702-06
Clock Generator for Printer Applications
FEATURES
PIN CONFIGURATION
•
1 CPU Clock output with selectable frequencies (50,
XIN
XOUT
VDDA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS0T
66.67, 75, 80, 83.3, 90, 100,125 or 133 MHz).
1 Selectable 48, 30 or 12MHz USB Clock output.
Selectable Spread Spectrum (SST) for EMI reduction
on CPU clock.
FS1T
•
•
SS0^
SS1^
GNDA
GNDD
GNDCPU
CPU
VDDD
GNDUSB
VDDUSB
USB/USB_SELT*
VDDCPU
•
•
•
•
•
PowerPC compatible CPU Clock.
Advanced, low power, sub-micron CMOS processes.
14.31818MHz fundamental crystal input.
3.3V and/or 2.5V operation.
Available in 16-Pin 150mil SOP.
:
Note
^: Internal pull-up resistor
*: Bi-directional pin
: Tri-level Input
T
CPU CLOCK FREQUENCY TABLE
DESCRIPTION
The PLL702-06 is a low cost, low jitter, and high
FS1
FS0
CPU (MHz)
performance clock synthesizer for generic Printer
applications. It provides one CPU clock and a selectable
48, 30 or 12MHz (USB) output. The user can choose
among 9 different clock frequencies and 3-selectable down-
spread Spread Spectrum modulation to reduce EMI on
CPU clock. All frequencies are generated from a single low
cost 14.31818MHz crystal. CPU clock can be driven from
an independent 2.5V or 3.3V power supply.
0
0
0
M
1
50
66.67
75
0
M
M
M
1
0
80
M
1
83.33
90*
0
100
125
133*
1
1
M
1
*Notes: Actual CPU frequency for 90Mhz is 88.88Mhz, 133Mhz is 130.9Mhz
BLOCK DIAGRAM
Control
USB_SEL
Logic
VDDUSB
USB
XIN
XTAL
OSC
PLL
XOUT
VDDCPU
CPU
PLL
SST
SS(0:1)
FS(0:1)
Control
Logic
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/26/05 Page 1
PLL702-06
Clock Generator for Printer Applications
PIN DESCRIPTIONS
Name
XIN
Number
Type
Description
Crystal input to be connected to a 14.31818MHz fundamental crystal (CL =
20pF, parallel resonant mode). Load capacitors have been integrated on the
chip. No external Load capacitor is required.
1
2
I
XOUT
O
Crystal Output
VDDA
VDDD
GNDA
GNDD
3,4,11,12
5,6,8,10
P
P
3.3V power supply and GND.
VDDUSB
VDDCPU
GNDUSB
GNDCPU
CPU and USB outputs have separate power supply pins (VDD and GND).
VDDCPU can accept 3.3V and/or 2.5V power supply.
Bi-directional pin. Upon power-on, the value of USB_SEL is latched in and used
to select the USB output (see USB selection table below). After the input has
been latched-in, the pin serves as USB (48, 30 or 12 MHz) output. 0=15kΩ to
GND, M=leave open, 1=15kΩ to VDD_USB
USB /
USB_SEL
7
B
CPU clock signal output pin. The CPU clock frequency is selected as per the
frequency table on page 1, depending on the value of FS(0:1).
CPU
9
O
I
Bi-level input with internal Pull-up resistor for SST control (see Spread
Spectrum selection table on p.2). 0=connect to GND, 1=leave open (or to VDD).
SS(0:1)
FS(0:1)
13,14
15,16
Tri-level inputs for CPU clock frequency selection (see table on p.1). 0=connect
to GND, M=not connected, 1=connect to VDDA.
I
USB FREQUENCY TABLE
USB_SEL
USB
48 MHz
0
M
1
30 MHz
12 MHz
SPREAD SPECTRUM SELECTION TABLE
SS1
SS0
Spread Spectrum Modulation
0
0
1
1
0
1
0
1
OFF
- 0.50% – Down Spread
- 1.00% – Down Spread
- 1.25% – Down Spread
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 2
PLL702-06
Clock Generator for Printer Applications
FUNCTIONAL DESCRIPTION
Tri-level and two-level inputs
In order to reduce pin usage, the PLL702-06 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 =
Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are in
the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to GND.
Likewise, in order to connect to a logical “one”, the pin must be connected to VDD.
Internal to chip
VDD
External Circuitry
Rup
R
Power Up
Reset
RB
Clock Load
Bi-directional pin
EN
Output
Latch
RUP 4
/
Latched
Input
Jumper options
NOTE: Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.
BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP
Connecting a bi-directional pin
The PLL702-06 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs
have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can
be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in
order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-
up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin and
GND (by definition, a tri-level input has a default value of "M" (mid) if it is not connected). In order to connect a bi-directional pin to
a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up resistor.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 3
PLL702-06
Clock Generator for Printer Applications
Note: when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor
may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.
For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the
internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the pin
serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is
recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application
Diagram).
VDD Power Up Ramp Requirements:
At startup, the chip reads a lot of settings for operation according to the application’s requirements. Since reading the settings is
done only at startup and then frozen for the time of operation, it is important that the power-up environment is somewhat
controlled to facilitate proper reading of the settings. The important VDD pins are VDDA (Pin3) and VDDD (Pin4) and they should
apply to the following two-startup requirements:
•
•
•
VDDD should be equally fast or slower than VDDA. VDDD performs a chip reset when VDD has reached a certain level and
VDDA should have reached at least up to the same level as well to properly process the reset.
The VDD Power Up Ramp of VDDD and VDDA should pass through the section 1.8V to 2.5V no faster than 100µs and with
a continuously increasing slope. In this section the tri-level select inputs are read.
After VDD Power off, VDD should be allowed to go to 0V and stay there for at least 1ms before a new VDD Power on. It is
important that proper preconditions exist at every startup. Remaining charges in the chip or in circuit filter capacitors may
interfere with the preconditions so it is important that VDD has been at 0V for some time before each startup.
VDD off
3.3V
2.97V
2.5V
2.2V
1.8
V
VDD on
GND (0V)
Min 1ms
No
>100us
limit
Min 1s
Reset enable
Reset disable
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 4
PLL702-06
Clock Generator for Printer Applications
Electrical Specifications
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
VDD+0.5
VDD+0.5
150
V
Input Voltage, dc
-0.5
-0.5
-65
0
V
Output Voltage, dc
VO
TS
TA
TJ
V
Storage Temperature
°C
°C
°C
°C
kV
Ambient Operating Temperature*
Junction Temperature
70
125
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
260
2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied.
2. AC Specifications
PARAMETERS
Crystal Input Frequency
CONDITIONS
MIN.
TYP.
MAX.
UNITS
14.31818
28
MHz
kHz
ns
SST modulation sweep rate
Output Rise Time
0.8V to 2.0V with no load
2.0V to 0.8V with no load
At VDD/2
1.5
1.5
55
Output Fall Time
ns
Duty Cycle
45
50
%
Max. Absolute Period Jitter
Max. Jitter, cycle to cycle
Long term, No SST
Long term + Short term
180
150
ps
ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 5
PLL702-06
Clock Generator for Printer Applications
3. DC Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VDDA
VDDD
Nominal voltage is 3.3V
2.97
3.63
V
Operating Voltage
Nominal voltage is 2.5V
Nominal voltage is 3.3V
2.25
2.97
2.75
3.63
V
V
V
V
V
V
V
V
V
V
VDDUSB
VDDCPU
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
VIH
VIL
VDD/2
VDD/2
VDD/2 - 1
0.5
VIH
VIL
For all Tri-level input
For all Tri-level input
For all normal input
For all normal input
VDD-0.5
VIH
VIL
2
0.8
IOH = -25mA
VDD = 3.3V
VOH
VOL
2.4
IOL = 25mA
0.4
Output High Voltage At
CMOS Level
VOH
IOH = -8mA
VDD-0.4
25
V
Nominal Output Current
Operating Supply Current
Short-circuit Current
Iout
IDD
IS
mA
mA
mA
No Load
30
±100
4. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Parallel Fundamental
Mode
Crystal Resonator Frequency
FXIN
14.31818
21
MHz
Crystal Loading Rating
Recommended ESR
CL (xtal)
RE
pF
AT cut
30
Ω
Note: A detailed crystal specification document is also available for this part.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 6
PLL702-06
Clock Generator for Printer Applications
LAYOUT RECOMMENDATION
The following is the recommended layout for PhaseLink’s PLL702-06 in 16-pin SOIC package.
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to PL702-06 as short as
possible, as well as keeping all other traces as far
away from it as possible.
- Place the crystal as close as possible to both crystal
pins of the device. This will reduce the cross-talk
between the crystal and the other signals.
- Separate crystal pin traces from the other signals on
the PCB, but allow ample distance between the two
crystal pin traces.
- Place 0.01µF~0.1µF decoupling capacitors between
VDDs and GNDs (see above diagram), on the
component side of the PCB, close to the VDD pins. It
is not recommended to place these components on
the backside of the PCB. Going through vias will
reduce the signal integrity, causing additional jitter
and phase noise.
- It is highly recommended to keep the VDD and GND
traces as short as possible.
- When connecting long traces (> 1 inch) to a CMOS
output, it is important to design the traces as a
transmission line or ‘stripline’, to avoid reflections or
ringing. In this case, the CMOS output needs to be
matched to the trace impedance. Usually ‘striplines’
are designed for 50Ω impedance and CMOS outputs
usually have lower than 50Ω impedance so matching
can be achieved by adding a resistor in series with
the CMOS output pin to the ‘stripline’ trace.
- Please contact PhaseLink for the application note on
how to design outputs driving long traces or the
Gerber files for the PL702-06 layout.
- Please contact PhaseLink for a detailed crystal spec.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselin.com Rev.
10/26/05
PLL702-06
Clock Generator for Printer Applications
PACKAGE INFORMATION
16 PIN Narrow SOIC ( mm )
E
H
SOIC
Symbol
Min.
1.35
0.10
0.33
0.19
9.80
3.80
5.80
0.40
Max.
1.75
0.25
0.51
0.25
10.00
4.00
6.20
1.27
A
A1
B
D
C
D
E
H
L
A
A1
C
e
1.27 BSC
L
B
e
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL702-06 X X X X
NONE= TUBE
PART NUMBER
R=
TAPE AND REEL
NONE= NORMAL PACKAGE
L= GREEN PACKAGE
PACKAGE TYPE
S=SOP
TEMPERATURE
C=COMMERCIAL
Part / Order Number
Marking
Package Option
Temperature
PLL702-06SC-R
PLL702-06SC
P702-06SC
P702-06SC
P702-06SCL
P702-06SCL
SOP -Tape and Reel
SOP -Tubes
0 to +70ﾟC
0 to +70ﾟC
0 to +70ﾟC
0 to +70ﾟC
PLL702-06SCL-R
PLL702-06SCL
SOP -Tape and Reel Green
SOP –Tubes Green
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/26/05 Page 8
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