DM7300_技术文档

DM7300G Series Digital Power Manager

Data Sheet

Member of the

Family

Features

•

RoHS compliant for all six substances

•

Compatible with both lead-free and standard reflow

processes

•

Programs, controls, and manages up to 32 independent

dPOL converters via an industry standard I2C interface (both

100kHz and 400kHz)

•

JTAG IEEE 1149.1 compliant programming interface

Controls and monitors industry standard power supplies and

other peripheral devices (fans, etc)

•

Programs output voltage, protections, optimal voltage

positioning, turn-on and turn-off delays and slew rates,

switching frequency, interleave (phase shift), and feedback

loop compensation of the dPwer^TMPOL converters

Applications

•

Low voltage, high density systems utilizing dPwer^TM

Digital Intermediate Bus Architectures

•

User friendly GUI interface for programming, monitoring,

and performance simulation

Broadband, networking, optical, and wireless

communications systems

Four independent OK lines for flexible fault management

and fast fault propagation

Industrial computing, servers, and storage applications

Four interrupt inputs with programmable hot swap support

capabilities

Benefits

•

Intermediate bus voltage monitoring and protection

AC Fail input

•

Eliminates the need for external power management

components

Non-volatile system configuration data memory

1K Byte of user accessible non-volatile memory

Control of industry standard DC-DC front ends

Crowbar output to trigger the optional crowbar protection

Run-time counter

Communicates with the host system via the industry

standard I2C communication bus

Reduces board space, system cost, complexity, and time

to market

Small footprint semiconductor industry standard QFN64

package: 9x9mm

•

Wide industrial operating temperature range

Description

Power-One’s point-of-load converters are recommended for use with regulated bus converters in an Intermediate Bus

Architecture (IBA). The DM7300 is a fully programmable digital power manager that utilizes the industry-standard I²C

communication bus interface to control, manage, program and monitor up to 32 dP-series POL converters and 4

independent power devices. The DM7300 completely eliminates the need for external components for power

management and programming and monitoring of the dPwer^TMPOL converters and other industry standard power

and peripheral devices. Parameters of the DM7300 are programmable via the I²C bus and can be changed by a user at

any time during product development and deployment.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 1 of 36

1

Selection Chart

DPM Type

Number of dPwer^TMPOLs

and Auxiliary devices that

can be controlled

Active

Addresses

Number of

Groups

Number of

Interrupts

Number of

Parallel

Buses

Number of

Auxiliary

Devices

DM7304G

DM7308G

DM7316G

DM7332G

4

8

00…03

00…07

00…15

00…31

2

3

4

2

3

4

2

4

8

4

16

32

2

Ordering Information

DM

73

xx

G

–

yyyyy

–

zz

Packaging Option ¹⁾

:

B1 – 50pcs Tube

B2 – 10pcs Tube

R100 – 100pcs T&R

Product

family:

dPwer Power

Management

Devices

Series: Number of

RoHS compliance:

dPwer^TMPOLs and G - RoHS compliant

5-digit identifier

assigned by

Power-One for

each unique

configuration file

Digital

Power

Manager

Auxiliary devices:

04 – 4 devices

08 – 8 devices

16 – 16 devices

32 – 32 devices

for all six substances

______________________________________

1

Packaging option is used only for ordering and not included in the part number printed on the DPM label.

The evaluation board is available in only one configuration: DM7300-KIT-HKS

2

Example: DM7316G-12345-R100: A 100-piece reel of 16-node DPMs with preloaded configuration file code 12345. Each DPM

is labeled DM7316G-12345. Refer to Figure 1 for label marking information.

Line 1 : Part Number

Line 2 : Customer Config. Number,

(7 Char. Alpha Numeric)

Customer Config. Rev.

DM73xxG

(5 digits Plus Rev Letter)

xxxxx x

Line 3 : Firmware Rev.

xxx

xxxxxxx

(3 Char. Alpha Numeric)

Line 4 : Programming

(Location, Date, Batch Code)

Figure 1. Label Drawing

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 2 of 36

3

Standard 5-Digit Identifiers

DPM Type

DPM preloaded with default

configuration file

DPM configured for JTAG

programming

Packaging Options

DM7304G

DM7308G

DM7316G

DM7332G

65511

65515

65516

65517

65518

B1, B2, R100

65512

65513

65514

4

Reference Documents

•

DP7XXX / DP8XXX Point of Load Regulator Data Sheets

DM7300 Digital Power Manager. Programming Manual, Revision A09 or later

Graphical User Interface, Revision 6.3.5 or later

•

Programming DM7300 DPMs via JTAG Interface. Application Note

ZM00056-KIT USB to I²C Adapter Kit. User Manual

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 3 of 36

5

Absolute Maximum Ratings

Stresses beyond those listed may cause permanent damage to the DPM. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability. Functional operation of the DPM at absolute maximum

ratings or conditions beyond those indicated in the operational sections of this specification is not implied.

Parameter

Ambient Temperature Range

Storage Temperature (Ts)

Junction Temperature (T_J)

Input Voltage

Conditions/Description

Min

-40

-55

Max

85

Units

°C

150

°C

125

°C

VDD pin

Any pin other than VDD

DC

-0.3

-0.5

3.6

VDC

mA

Input Voltage

VDD+0.5

40

Pin Current

6

7

Mechanical Specifications

Parameter

Peak Reflow Temperature

Lead Plating

Conditions/Description

Min

Nom

Max

Units

40 sec maximum duration

260

°C

100% matte tin

3

Moisture Sensitivity Level

JEDEC J-STD-020C

Reliability Specifications

Parameter

Conditions/Description

Min

Nom

Max

Units

Demonstrated at 55°C,

60% Confidence Level

Failure Rate

2.26

FIT

Read-

Write

cycles

Non-Volatile Memory Endurance

-40°C to 85°C ambient

10,000

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 4 of 36

8

Electrical Specifications

Specifications apply at VDD from 3V to 3.6V, ambient temperature from -40°C to 85°C, and utilizing proper

decoupling as shown in Figure 3 unless otherwise noted.

8.1

Power Specifications

Parameter

Conditions/Description

Min

Nom

Max

Units

Input Supply Voltage

VDD pin

3.0

3.6

VDC

Hardware reset is triggered below this

threshold

Undervoltage Lockout

2.3

2.5

2.7

VDC

Input Supply Current

VREF voltage

VDD pin=3.3V

AREF pin

12

20

2.7

mA

VDC

MΩ

2.3

2.56

IBVS input voltage range

IBVS input resistance

GND

VREF

100

8.2

Feature Specifications

Parameter

Conditions/Description

Min

Nom

Max

Units

Intermediate Voltage Bus Protections

Overvoltage Protection

Threshold

With external 5.7:1 ratio divider

IBV

14.6

IBV

V

Undervoltage Protection

Threshold

0

With external 5.7; 1ratio divider.

Symmetrical relative to average

threshold value

Threshold Hysteresis

114

mV

Accuracy of Protection

Thresholds

Internal voltage reference, 1% resistive

divider

-10

-43

10

43

%V_TH

mV

Internal ADC Conversion Error

With external 5.7:1 ratio divider

Front End Enable (FE_EN)

Front End logic level enabled

Front End logic level disabled

Source Current, V_{FE_EN}=V_DD-0.5V

Sink Current, V_{FE_EN}=0.5V

Crowbar (CB)

V_{FE_EN}

Isrc

High

Low

5

mA

Isink

V_CB

Isrc

Isink

T_CB

Crowbar Enable

High

Low

Crowbar Disable

Source Current, V_CB=V_DD-0.5V

Sink Current, V_CB=0.5V

5

mA

ms

Duration of Enabling Pulse

1

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 5 of 36

8.3

Signal Specifications

Parameter

Conditions/Description

SYNC/DATA Line

Min

Nom

Max

Units

SDpu

SD pull up resistor

SD input low voltage threshold

SD input high voltage threshold

SD input hysteresis

5

kΩ

V

SDthrL

0.31·VDD

0.45·VDD

0.37

0.52·VDD

0.81·VDD

1.1

SDthrH

SDhys

V

SDsink

Freq_sd

SD sink capability (V_SD=0.5V)

Clock frequency

30

mA

kHz

450

22

550

% of clock

cycle

% of clock

cycle

Tsynq

T0

Sync pulse duration

28

78

Data=0 pulse duration

72

Interrupt Inputs (INT_N[3:0])

Pull up resistor

Rpu3

VthrL3

VthrH3

Vhys3

30

kΩ

V

Input low voltage threshold

Input high voltage threshold

Input hysteresis

0.31·VDD

0.45·VDD

0.37

0.52·VDD

0.81·VDD

1.1

V

ADDR[3:0], ACFAIL_N, RES_N, LCK_N, PG[3:0] Inputs

Rpu1

VthrL1

VthrH1

Pull up resistor

Input low voltage

Input high voltage

20

-0.5

50

kΩ

V

0.2·VDD

VDD+0.5

0.7·VDD

V

HRES_N Input

HRES_N pull up resistor (with series

diode, see note 1)

Rpu2

30

60

kΩ

VthrL2

VthrH2

HRES_N input low voltage

HRES_N input high voltage

-0.5

0.2·VDD

VDD+0.5

V

0.9·VDD

Inputs/Outputs (OK_A, OK_B, OK_C, OK_D)

OKpu

OKthrL

OKthrH

OKhys

OKsink

OK pull up resistor

5

kΩ

V

OK input low voltage threshold

OK input high voltage threshold

OK input hysteresis

0.31·VDD

0.45·VDD

0.37

0.52·VDD

0.81·VDD

1.1

V

OK sink capability (V_OK=0.5V)

30

mA

Enable Outputs (EN[3:0])

V_EN

EN logic level enabled

EN logic level disabled

High

Low

EN output high voltage

I_OH= -10 mA

EN output low voltage

I_OL= 5 mA

V_EN

H

VDD-0.6

V

V_EN

L

0.5

______________________________________

1

HRES_N Input - Because the input does not have an internal ESD protection diode connected to VDD, the user needs to add an external diode between the

HRES_N and VDD pins as shown in Figure 3.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 6 of 36

8.4

I²C Interface

Parameter

Conditions/Description

Input low voltage

Min

-0.5

Nom

Max

Units

V

ViL

ViH

Vhys

VoL

t_r

0.3·VDD

VDD+0.5

Input high voltage

0.7·VDD

0.05·VDD

0

V

Input hysteresis

V

Output low voltage, I_SINK=3mA

Rise time for SDA and SCL

Output fall time from ViHmin to ViLmax

Input current each I/O pin, 0.1V_DD<V_i<0.9V_DD

Capacitance for each I/O pin

SCL clock frequency

0.4

300

250

10

V

1

20+0.1C_b

ns

µA

pF

kHz

1

t_of

20+0.1C_b

Ii

-10

Ci

10

f_SCL

0

400

Standard-Mode I²C (f_SCL≤ 100kHz)

1

R_PU

t_HDSTA

t_LOW

External pull-up resistor

Hold time (repeated) START condition

Low period of the SCL clock

1

1000/C_b

kΩ

µs

ns

µs

4.0

4.7

4.0

4.7

0

t_HIGH

High period of the SCL clock

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTD

t_SUF

Setup time for a repeated START condition

Data hold time

3.45

Data setup time

250

4.0

4.7

Setup time for STOP condition

Bus free time between a STOP and START condition

Fast-Mode I²C (100kHz < f_SCL≤ 400kHz)

1

R_PU

t_HDSTA

t_LOW

External pull-up resistor

Hold time (repeated) START condition

Low period of the SCL clock

1

300/C_b

kΩ

µs

ns

µs

0.6

1.3

0.6

0

t_HIGH

High period of the SCL clock

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTD

t_SUF

Setup time for a repeated START condition

Data hold time

0.9

Data setup time

100

0.6

1.3

Setup time for STOP condition

Bus free time between a STOP and START condition

______________________________________

1

C_b– bus capacitance in pF, typically from 10pF to 400pF

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 7 of 36

t_o

f

t_HIG

H

t_LO

W

t_r

t_LO

W

SCL

SDA

t_SUSTA

t_HDST

A

t_HDDAt_SUDA

t_SUST

O

T

t_BU

F

Figure 2. I²C Timing Parameters

9

Typical Application

Figure 3. Typical Application Schematic of Multiple Output System with Digital Power Manager and I²C Interface

The schematic of a typical application of a DM7300 digital power manager (DPM) is shown in Figure 3. The system

includes four groups of dPwer Point Of Load converters (POLs). A group is defined as one or more POL converters

interconnected via OK pins. Grouping of the POLs enables users to program advanced fault management schemes

and define margining functions, monitoring, startup behavior, and reporting conventions.

All dPwer POL converters are connected to the DPM and to each other via a single-wire synchronization/data (SD)

line. The line provides synchronization of all POL converters to the master clock generated by the DPM and

simultaneously carries bidirectional data transfer between POL converters and the DPM. The DPM communicates via

the I2C bus with the host system and/or the Graphical User Interface.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 8 of 36

In this application, besides POL converters, the DPM also controls and monitors two auxiliary devices – a Voltage

Regulation Module (VRM) and a Low Dropout Regulator (LDO). While these devices are not dPwer compliant and

may not even be manufactured by Power-One, they are integrated into the system by communicating with the DPM

via their Enable pins connected to ENX outputs of the DPM. In addition, the DPM monitors status of the auxiliary

devices via its PGX inputs connected to Power Good and Error Flag outputs of the auxiliary devices. The DPM can

control and monitor four or more independent auxiliary devices.

The DPM can also trigger an optional crowbar circuit and provide undervoltage and overvoltage protections of the

intermediate bus voltage. In addition, the DPM can be controlled by a host system via the interrupt inputs, RES_N

and the ACFAIL_N inputs.

10

Description

The DM7300 series DPMs perform translation between the I2C interface connected to a host system or the Graphical

User Interface and the SD communication bus connected to dPOL converters. In addition, DPMs carry out

programming, monitoring, data storage, POL group management, hot-swap control, protection, and control and

monitoring of auxiliary devices.

The DPMs can be controlled via the GUI or directly via the I2C bus by using specific commands described in the

“DPM Programming Manual”.

10.1

DPM Memory

The DPM memory consists of RAM and non-volatile memory (Flash). The RAM is used for programming operations

and manipulation of the various blocks of configuration, setup, status, and monitoring registers. Non-volatile memory

is used to store programming and configuration data. Flash memory holds DPM set-up registers, POL set-up

registers, monitoring data, and user memory data. Setup registers for the DPM and the POL converters are protected

by CRCs that are checked during programming of POL converters and at the power-up of the DPM.

The LCK_N pin and the write protection register WP limit the write access to the memory blocks in the DPM and

POL converters. The WP register content is defaulted to write protect upon powering up the DPM.

10.1.1 Write Protection

There are hardware-based and software-based memory write protections. The hardware protection takes precedence

over the software protection.

10.1.1.1 Hardware Protection

The LCK_N pin enables the hardware memory write protection. If the pin is pulled low, the hardware lock is active

and the memory blocks are then read-only. I2C write commands to the DPM return an error code (0x00). The write

commands to the POL converters bypassing the DPM are also disabled. If the pin is left floating, the hardware lock is

disabled and the software write protection is active.

10.1.1.2 Software Protection

Software write protection allows users to protect the various memory blocks from being overwritten through the I2C

bus. At the power-up the WP register is defaulted to write protect.

Software write protection can be disabled by checking appropriate boxes in the Write Protection subsection of the

DPM/Program/Advanced dialog shown in Figure 4 or via the I2C bus by writing directly into the register. Write

protections are automatically restored when the DPM’s input power is recycled.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 9 of 36

Figure 4. GUI DPM Advanced Programming Dialog

10.1.2 DPM Registers

The DPM setup registers occupy 70 bytes and contain all necessary information to set up the DPM functionality,

define POL converters and Auxiliary Devices, group membership and behavior, margining, interrupt configurations,

etc. they DPM registers are listed in. The table relates to the DPM model number DM7332 capable of supporting up

to 32 POL converters. For other DPM models some of the registers and/or bits in the registers are not activated

depending on the number of supported POLs/Groups/Interrupts/Parallel Buses for the specific DPM. Writing into

an unsupported register or bit will have no effect, reading from an unsupported register or bit will return an error code

(0x00).

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 10 of 36

Table 1. DPM Setup Registers

Address Register

Name

Content

Register

Type

User

Access

Write

Protect

Initial Value

Offset¹

0x00

0x04

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x13

0x15

0x17

0x1B

0x1F

0x23

0x27

0x28

0x80

0x84

0x88

0x89

0x8B

0x8C

0x8D

0x8E

0x8F

0x91

0x95

0x96

GD1[3:0]

GD2[3:0]

GAC

GBC

GCC

Group Definition Register 1

Group Definition Register 2

Group A Configuration

Group B Configuration

Group C Configuration

Group D Configuration

Fault Propagation Configuration 1

Fault Propagation Configuration 2

Error Propagation Configuration

Interrupt Configuration 1

Interrupt Configuration 2

IBV Low threshold

Static

R/W

OTP

R/W

R

yes

0x00000000

yes

0x00

GDC

FPC1

Static

FPC2

EPC

IC1

IC2

IBL[1:0]

IBH[1:0]

ID[1:0]

PB1[3:0]

PB2[3:0]

PB3[3:0]

PB4[3:0]

PMC

Static

yes

IBV high threshold

yes

N/A

yes

0xFF

DPM Customer Identification

Parallel Bus Register 1

Parallel Bus Register 2

Parallel Bus Register 3

Parallel Bus Register 4

Power Manager Configuration

POL Identification Register

Run Time Counter

0xFFFF

0x00000000

0x00

Static

yes

Static

yes

PID[31:0]

RTC[3:0]

PPS[3:0]

EST

IBV[1:0]

STA

STB

STC

STD

REL[1:0]

PSS[3:0]

DPMS

WP

yes

Read only

0x00

Run time

Static

value at last shut-down

(4x) 0x00

0x00

POL Programming Status

Event Status

IB Voltage

R

0x00

Status of Group A

Status of Group B

Status of Group C

Status of Group D

R

DPM Software Release

POL Status Summary

DPM Status

According to DPM type

0x00

0x01

Run time

Volatile

R

R/W

Write Protection

0x00

______________________________________

1

Writing into memory locations beyond address offset 0x96 must be avoided

The static registers are saved in the non-volatile memory and used to store the system configuration data. The run-

time registers contain status information and are evaluated during run-time. The Write Protection register WP is a

volatile register that defaults to write protect at power-up.

10.1.3 POL Setup Registers

Since the POL converters contain only RAM, the data defining performance parameters for each POL and Auxiliary

Device, such as the output voltage, protection thresholds, feedback loop compensation, turn-on and turn-off delays,

fault management settings, etc., is stored in the POL setup registers in the DPM. The POL setup registers consist of

23 data bytes and 2 CRC bytes. The Auxiliary Device setup registers occupy the same amount of bytes as a POL

converter, but only 3 registers have meaningful data. The other registers should be filled with 0x00. The POL setup

registers are listed in Table 2. Register significance is different in some cases between the new DP and older ZY series

POLs which are still supported. Differences are in bold for the DP series devices.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 11 of 36

Table 2. POL Setup Registers

Address

Offset

Register

Content

Address

Offset

Register

Content

+)

DP7000 /

DP8000

POL

Z7000 /

Z8000 POL Device

Aux

00h

01h

02h

03h

04h

PC1_x

PC2_x

PC3_x

TC_x

Protection Configuration 1

Protection Configuration 2

Protection Configuration 3

Tracking Configuration

Interleave Configuration and Frequency

Selection

00h

01h

02h

03h

04h

PC1_x

PC2_x

PC3_x

TC_x

EC_x

Protection Configuration 1

Protection Configuration 2

Protection Configuration 3

Tracking Configuration

Interleave Configuration and Frequency

Selection

reserved

INT_x

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

DON_x

DOF_x

VLC

CLS_x

DCL_x

PC4

V1H

V1L

V2H

Turn-On Delay

Turn-Off Delay

Voltage Loop Configuration

Current Limit Set-point

Duty Cycle Limit

Protection Configuration Register 4

Output Voltage Setpoint 1 High

Output Voltage Setpoint 1 Low

Output Voltage Setpoint 2 High

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

DON_x

DOF_x

VOS_x

CLS_x

DCL_x

B1_x

B2_x

B3_x

C0L_x

EON_x

EOF_x

reserved

Turn-On Delay

Turn-Off Delay

Output Voltage Set-point

Current Limit Set-point

Duty Cycle Limit

Dig Controller Denominator z^-1Coefficient

Dig Controller Denominator z^-2Coefficient

Dig Controller Denominator z^-3Coefficient

Dig Controller Numerator z⁰Coefficient Low

Byte

0Eh

0Fh

10h

11h

12h

13h

14h

V2L

V3H

V3L

CP

Output Voltage Setpoint 2 Low

Output Voltage Setpoint 3 High

Output Voltage Setpoint 3 Low

Controller Proportional Coefficient

Controller Integral Coefficient

Controller Derivative Coefficient

0Eh

0Fh

10h

11h

12h

13h

14h

C0H_x

C1L_x

C1H_x

C2L_x

C2H_x

C3L_x

C3H_x

reserved

Dig Controller Numerator z⁰Coefficient High

Byte

Dig Controller Numerator z^-1Coefficient Low

Byte

Dig Controller Numerator z^-1Coefficient High

Byte

Dig Controller Numerator z^-2Coefficient Low

Byte

CI

Dig Controller Numerator z^-2Coefficient High

Byte

CD

CV

Dig Controller Numerator z^-3Coefficient Low

Byte

Controller Derivative Roll-Off

Coefficient

Dig Controller Numerator z^-3Coefficient High

Byte

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

reserved

MRH

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

reserved

Margining High Selection

Margining Low Selection

VOML_x ^#)reserved

Output Voltage Margining Low Value

Output Voltage Margining High Value

MRL

VOMH_x

reserved

#)

1Eh

1Fh

CRC0_x

Cyclic Redundancy Check Register 0

Cyclic Redundancy Check Register 1

1Eh

1Fh

CRC0_x ^#)

CRC1_x ^#)

CRC0_x

Cyclic Redundancy Check Register 0

Cyclic Redundancy Check Register 1

#)

CRC1_x

#)

⁺⁾x denotes the POL address

[0..31]

^#)not downloaded to the POL

______________________________________

x denotes the POL address [0..31]

^#)not downloaded to the POL during programming

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 12 of 36

10.1.4 Monitoring Data

The DPMs can retrieve current, temperature, output voltage, and status information from each of the POL converters

and status information only from Auxiliary Devices. Monitoring data is stored in RAM and can be accessed via the

I2C bus. Monitoring registers are read only.

The monitoring data consists of 5 Bytes for each POL converter and Auxiliary Device as shown in Table 3. When the

status monitoring is enabled, the ST registers get continuously updated. When the parametric monitoring is enabled,

the VOH, VOL, IO, and TMP registers get continuously updated. Scaling data from the registers is specific to each

DP and ZY series POL. Refer to the DM7300 Programming manual for calculation information.

Table 3: Monitoring Data Registers

POL Converter

Content

Auxiliary Device

Content

Status Register

Register

ST

VOH

VOL

IO

Status Register

Output Voltage High Byte

Output Voltage Low Byte

Output Current

ST

reserved

TMP

Temperature

10.1.5 User Memory

This non-volatile memory block is reserved for users’ notes and not related to other functions in the DPM. It can be

used to save user-specific information such as manufacturing data and location, serial number, application code,

configuration file version, warranty or repair information, etc. A total of 1024 Bytes organized in 4 pages is provided.

The user memory can be accessed via the GUI System Configuration window shown in Figure 8 or directly via the I2C

bus using specific commands. Content of the user memory is saved into the configuration file when the file is saved.

Note that this does not change the current DPM contents until the DPM is programmed with the file currently in

memory.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 13 of 36

Figure 5. User Memory Window

10.2

Auxiliary Devices

The DM7300 DPM includes all necessary circuitry to control and monitor four Auxiliary Devices. Virtually any device

which has an on/off input and a monitoring output can be an Auxiliary Device. Typical examples of Auxiliary

Devices include analog POL converters, linear regulators, and fans. Auxiliary Devices are controlled and monitored

via the Graphical User Interface.

The DPM treats Auxiliary Devices as dPwer™ POL converters: each Auxiliary Device has an address and is assigned

to one of the groups as shown in Figure 8 (device at addresses 03). Turn-on and off delays can be programmed, and

faults can be propagated from POL converters to the devices. Auxiliary Devices are controlled through standard

group turn-on and off commands and are fully synchronized with turn-on/off timing of POL converters.

Four enable outputs EN0…EN3 control the Auxiliary Devices. Four monitoring inputs PG0…PG3 read status of the

Auxiliary Devices. The enable outputs and monitoring inputs are paired together and permanently assigned to specific

pins of the DPM as shown in Figure 6. Adding an AUX device is done the same way as adding a POL, select an

uncommitted address and then the AUX device desired. In this example two AUX devices are already present.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 14 of 36

Figure 6. Auxiliary Device Type Window

Turn-on and turn-off delays can be programmed for each Auxiliary Device as shown in Figure 7. Timing of turn-on

and turn-off events can be synchronized between Auxiliary Devices and POL converters by programming appropriate

delays for specific types of devices.

Figure 7. Sequencing Tracking Window

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 15 of 36

10.3

DPM Functions

10.3.1 POL Programming

POL programming is the process of downloading the content of POL setup registers stored in DPM’s non-volatile

memory via the SD bus to the POL converters.

Programming of POL converters is performed upon power-up, or when the Program button is pressed in the GUI

System Configuration window shown in Figure 8, or when the specific command is sent directly via the I2C bus.

Figure 8. System Configuration Window

The programming is performed in several steps. Once the supply voltage on the VDD pins of the DPM exceeds the

UVLO protection threshold, the DPM will start copying setup registers from its non-volatile memory into RAM and

execute the cyclic redundancy check (CRC) to ensure integrity of the programming data. When the voltage on the

IBVS pin exceeds the IBV undervoltage protection threshold, the DPM will download POL setup registers to the

respective POL converter via the SD line. Every data transfer is protected by parity check and followed by the POL

acknowledgement and read data back procedure. If both acknowledgement and readback operations are successful,

the POL-specific bit in the POL Programming Status registers will be set. The DPM considers the POL converter to

be programmed, and continues programming the next POL converter.

Upon completion of the programming, the DPM will turn-on the POL converters, if the Auto Turn-On is enabled in

the POL Group configuration window shown in Figure 9 (topmost group of square buttons just below "Bus Voltages"

tab. Otherwise, the user will need to send the turn-on command via the I2C bus.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 16 of 36

Figure 9. POL Configuration Window

10.3.2 Programming Time

Total system programming time can be determined from the following equation:

T_PROGR= T_INIT+ n_POL×T_POL+ n_AD×T_AD

Where:

T_PROGR

-

time interval from the instant when the DPM supply voltage exceeds DPM’s UVLO threshold until the

DPM issues the turn-on command. If the Auto Power-Up is enabled, and the turn-on delay is set to zero,

the output voltages start ramping up at the end of T_PROGRinterval

T_INIT

T_POL

-

DPM initialization interval after the DPM supply voltage exceeds the UVLO threshold. T_INIT=11.5ms.

Time required for programming and verifying of one POL converter. T_POL=26.5ms.

Time required for programming and verifying of one Auxiliary Device. T_AD=7.5ms.

Number of POL converters in the system.

-

T_AD

-

n_POL

-

n_AD

-

Number of Auxiliary Devices in the system.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 17 of 36

The programming data (DPM and POL setup registers and the user memory) can be preloaded into DPMs by Power-

One or the DPMs can be programmed by the user via the GUI, I2C bus, or JTAG programming interface. The

DPMs can be programmed either before or after installation on a host board.

To modify POL converter settings, the user can directly access the registers of a POL converter via the I2C bus,

bypassing DPM’s POL setup registers. The I2C commands are translated by the DPM and converted into appropriate

SD commands to read / write from / into the registers of a POL converter. Writing into these registers is limited by

the hardware (LCK_N) and/or software write protections. Since POL converters do not have non-volatile memory,

data written directly into POL converter registers will be lost when the input voltage is removed.

10.4

Monitoring

10.4.1 POL Monitoring

dPwer^TMand Z-one™ POL converters continuously monitor their own performance parameters such as output

voltage, output current, and temperature. The monitored parameters are stored locally in the POL converters and

updated every 1ms. If monitoring feature is enabled, the DPM will be continuously copying status and parametric data

from POL converters into DPM’s monitoring data registers.

The monitoring is enabled by checking the appropriate Retrieve Monitoring bits in the GUI Group Configuration

window shown in Figure 9 or directly via the I2C bus by specific commands.

If the status monitoring is enabled, the status of each protection (overcurrent, overvoltage, etc.) is being reported. If

the parametric monitoring is enabled, then real-time values of voltage, current, and temperature are being reported.

Status and parametric monitoring data of a single POL converter and groups of POL converters can be examined in

the GUI IBS Monitoring Window shown in Figure 10 or directly via the I2C bus using specific commands. Status

data for each group of POL converters is presented in the Group Status block in the left top corner of the window.

Parametric data for individual POL converters is shown in Voltage [V], Current [A], and Temp [T] screens.

DPMs also monitor and report programming status of each POL converter and results of CRC operations.

10.4.2 Monitoring of Auxiliary Devices

The DPM can read status information of the Auxiliary Devices via the PG0…PG3 inputs. The PG0…PG3 are digital

3.3V compliant inputs with internal pull-up resistors. Logic high input on a PGX pin should correspond to normal

operation of an Auxiliary Device.

Status monitoring data of Auxiliary Devices is stored in the DPM and displayed in the IBS Monitoring Window shown

in Figure 10.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 18 of 36

Figure 10. IBS Monitoring Window

10.4.3 Run Time Counter

The DPM also monitors the duration of time that it has been in operation. The 4 bytes Run Time Counter is active

whenever the DPM is powered up. The count rate is 1 second. The counter is loaded into RAM upon power-up and

the new count state is periodically saved to the non-volatile memory. Contents of the counter can be examined in the

GUI IBS Monitoring Window shown in Figure 10 or directly via the I2C bus using specific commands.

10.4.4 IBV Monitoring

The DPM continuously monitors the intermediate bus voltage via the IBVS input and the built-in 10-bit ADC. The

digital representation of the bus voltage is stored in RAM and reported in the IBS Monitoring window shown in

Figure 10.

In addition, the DPM continuously compares the value of IBV to the Undervoltage and Overvoltage thresholds

programmed in the GUI Intermediate Bus Configuration Window shown in Figure 11.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 19 of 36

Figure 11. Intermediate Bus Configuration Window

The thresholds have a symmetric, fixed size hysteresis as shown in Figure 12

Figure 12: Undervoltage (IBL) and Overvoltage (IBH) Protections Hysteresis

When the IBV decreases below the IBL threshold minus the hysteresis, the DPM will pull OK lines low turning off all

POL converters. The POL converters will execute regular turn-off ramping their output voltages down according to

the turn-off delay and falling slew rate settings. In addition, the DPM will clear all bits in the POL Programming

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 20 of 36

Status registers and save the content of the Run Time Counter into the non-volatile memory. The IBV Low bit in the

IBS Monitoring Window will change to red. When the IBV recovers above the IBL threshold plus the hysteresis, the

DPM will first program all POL converters and then turn them on, if the Auto Turn-On is enabled in the POL Group

configuration window shown in Figure 9. Otherwise, the user will need to send the turn-on command via the I2C bus.

When the IBV exceeds the IBH threshold plus the hysteresis, the DPM will pull OK lines low turning off all POL

converters. The POL converters will execute regular turn-off ramping their output voltages down according to the

turn-off delay and falling slew rate settings. In addition, the DPM will save the contents of the Run Time Counter into

the non-volatile memory. If the IBV does not decrease below the IBH threshold minus the hysteresis within the next

50ms, the DPM will pull low the FE_EN output and clear all bits in the POL Programming Status registers. The IBV

High bit in the IBS Monitoring Window will change to red. If the IBV still does not change, in 50ms the DPM will

pull the CB pin high for 1ms to trigger an optional crowbar protection.

One second after the IBV decreases below the IBH threshold minus the hysteresis, the DPM will pull the FE_EN

high and program all POL converters. Upon completion of the programming process, the DPM will turn on the POL

converters, if the Auto Turn-On is enabled in the POL Group configuration window shown in Figure 9.

The propagation delay between the IBV increasing/decreasing above/below corresponding thresholds and the DPM

pulling down OK lines and triggering the turn-off process is approximately 1ms.

10.4.4.1 Voltage Reference

For the purposes of IBV monitoring the user can select either the DPM’s internal voltage reference or an external

2.5V voltage reference. The selection is made by clicking an appropriate radio button in the DPM Configuration/Bus

Voltages dialog as shown previously in Figure 11

.

he DPM’s internal 2.56V voltage reference guarantees 10% overall accuracy of the IBV protection thresholds. If the

accuracy is sufficient, the user does not need to make any changes to the schematic shown in Figure 3. If higher

accuracy of the IBV monitoring is desired, then a 2.5V external reference can be added as shown in Figure 13. The

GUI automatically changes values of the IBL and IBH thresholds when the reference selection is changed.

Note: If the Reference Voltage setting is changed during operation of the DPM, then the power to the DPM needs to be cycled

or the HRES_N pin needs to be pulled low and released

Figure 13. External Voltage Reference Connections

U1 and R1 are additional components. U1 is an industry standard 2.5V voltage reference such as TL431 or similar.

C1 is an existing component but its value changes depending on the type of voltage reference. Common voltage

reference part numbers and values of associated components are shown in Table 4.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 21 of 36

Table 4. Component Values For External Reference

TL431

TI

ZR431

Zetex

U1 Part Number

Manufacturer

Accuracy, %

R1, Ohms

0.5, 1, 2

100-620 510-2000

≥ 10 ≥ 0.01

C1, µF

Accuracy of the protection thresholds in the case of external reference is determined by the sum of accuracy of the

voltage reference, accuracy of the 10k/47k resistive divider shown in Figure 13, and conversion error of the internal

ADC specified in 8.2.

10.5

POL Group Management

POL converters and Auxiliary Devices can be arranged in up to four groups. A group of POL converters is defined as

a number of POL converters with interconnected OK pins. Auxiliary Devices are added to a group in the GUI,

without any external connections. A group can include from 1 to 32 POL converters, but a POL converter can be a

member of only one group. In addition, the OK lines can be connected to the DPM to facilitate propagation of faults

and errors between groups. One DPM can manage up to four independent groups: A, B, C, and D, depending on

model of the DPM.

Group management includes fault and error propagation, margining, turn-on and turn-off, monitoring setup, and

interrupt configuration.

10.5.1 Fault and Error Propagation

dP-series POL converters protect outputs by triggering either a fault or an error depending on the severity of the

problem (see POL converter datasheets). Fault propagation between POL converters belonging to the same group is a

programmable function of POL converters. The DPM allows propagating faults and errors between groups of POL

converters and, in case of an error, to a DC/DC front-end and an optional crowbar. The propagation delay for

fault/error propagations is less than 10µs.

To enable fault and error propagation, the respective bits needs to be checked in the GUI Fault and Error Propagation

window shown in Figure 14. Note that cross propagation of faults/errors (means fault in Group X propagates to Y

and vice versa) should be avoided.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 22 of 36

Figure 14. Fault and Error Propagation Window.

The fault propagation from POL converters to the auxiliary devices can be disabled by checking the bit in the Auxiliary

Device Fault Management window as shown in Figure 15. It is not possible to propagate a fault from an Auxiliary

Device to POL converters.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 23 of 36

Figure 15. Auxiliary Device Fault Management Window

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 24 of 36

When propagation is enabled, the faulty POL converter pulls its OK pin low. A low OK line initiates turn-off of other

POL converters in the group and signals the DPM to pull other OK lines low to initiate turn-off of other POL

converters as programmed.

The regular turn-off of a POL converter means that the output voltage is ramping down according to its turn-off delay

and falling slew rate settings. If a POL converter triggers an undervoltage or overtemperature fault, it will initiate the

regular turn-off. In the case of an overcurrent or tracking fault, the POL converter initiates the fast turn-off by

opening both high and low side switches instantaneously. If either output overvoltage or phase voltage errors are

triggered, the faulty POL converter initiates the fast turn-off and turns on its low side switch. In addition, when an

error is propagated, the DPM can generate commands to turn off a front end (a DC-DC converter generating the

intermediate bus voltage) and trigger an optional crowbar protection to accelerate removal of the intermediate bus

voltage (IBV).

Once the fault has recovered in the faulty POL converter, the other POL converters will turn on in a controlled

manner according to their turn-on delay and rising slew rate settings.

10.5.2 Margining

Margining can be executed separately for each group by clicking an appropriate radio button in the GUI IBS

monitoring window shown in Figure 10 or directly via the I²C bus by the margining command. All POL converters in

a group are margined in the same direction (up or down) by the percentage programmed individually for each POL

converter.

10.5.3 Turn-ON and Turn-Off

Automatic turn–on upon application of the input voltage is enabled by checking the Auto Turn-On bit in the GUI

Group Configuration window shown in Figure 9. Turn-on and turn-off of various groups during the operation is

controlled from the GUI IBS Monitoring window or directly via the I²C bus by specific commands.

10.5.4 Interrupt Configurations

The DPM has four interrupt inputs that can be programmed to:

•

Inhibit the operation of one or several Groups of POL converters when pulled low or

Act as a Group Reprogramming Trigger.

•

The two functions are mutually exclusive – an interrupt can be either programmed as an Inhibit or as a Group

Reprogramming Trigger.

The interrupts are programmed in the GUI Interrupt Configuration window shown in Figure 16 or directly via the I2C

bus by specific commands. In Figure 16 the Interrupt 0 is programmed as the inhibit for group A and the Interrupt 2

is programmed as the group C reprogramming trigger.

10.5.4.1 Group Inhibit

An interrupt input can be programmed to act as an inhibit on a single or multiple groups of POL converters. When

the interrupt input is pulled low, the DPM will pull the appropriate OK lines low. The affected POL converters will

execute regular turn-off ramping their output voltages down according to the turn-off delay and falling slew rate

settings. Once the interrupt is released, the POL converters will automatically turn-on according to their turn-on delay

and rising slew rates settings.

The inhibit function can be used for a variety of applications, such as

•

Hardware-based control of groups of POL converters and Auxiliary Devices

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 26 of 36

•

Delayed turn-on at power-up (Automatic Turn-On is enabled but the interrupts are held low during

power-up. Note that POL converters can be programmed even when an interrupt is held low.)

The interrupt inputs should be controlled with open collector devices. The propagation delay between the external

device pulling the interrupt input low and the DPM pulling down OK lines and triggering the turn-off process is

approximately 10µs. This option is set as part of DPM/Configure/Faults dialogs.

Figure 16. Interrupt Configuration Dialog

10.5.4.2 Group Reprogramming Trigger

An interrupt that is programmed as a group reprogramming trigger always acts only on one group of POL converters.

Interrupt 0 acts on Group A, Interrupt 1 acts on Group B and so on. The assignment is fixed and cannot be changed

by the user.

When the interrupt is pulled low, the DPM will program the group of POL converters. Upon completion of the

programming, the DPM will turn-on the POL converters, if the Auto Turn-On is enabled. When the interrupt input is

released, the DPM will pull the appropriate OK line low. The POL converters in the group will execute regular turn-

off ramping their output voltages down according to the turn-off delay and falling slew rate settings. In addition, the

DPM will clear all bits in the POL Programming Status registers.

The group reprogramming trigger is mostly used to support hot swap of boards and daughter cards that do not have a

DPM installed on them as shown in Figure 17.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 27 of 36

Mother Board or Back Plane

Group A Daugther Card

IBV GND SD

POL

Vox

POL

DM7300

SD

OK_A

INT0_N

Figure 17: INT0 Configured as Group A Reprogramming Trigger

In this configuration the Interrupt 0 (INT0_N) is configured as the group A reprogramming trigger. The DPM is

installed on a mother board or a backplane. A daughter card with a group of POL converters is being inserted in the

system during normal operation. At first, the long pins carrying power and the OK_A line signal make contact. Then

the short pins carrying the SD and interrupt signals make contact. Once the interrupt senses low input voltage, it will

command the DPM to program all POL converters in the group A. Upon completion of the programming, the DPM

will turn-on the POL converters, if the Auto Turn-On is enabled.

When the daughter card is being removed, the interrupt input is released as soon as the short pins break the contact.

The DPM will immediately pull the OK_A line low turning off all POL converters in the group A according to the

turn-off delay and falling slew rate settings.

10.6

Controls

10.6.1 ACFAIL_N and RES_N

The ACFAIL_N and RES_N are active low digital inputs. When one of the inputs is pulled low, the DPM will pull all

OK lines low turning off all the POL converters and the Auxiliary Devices in all groups. The POL converters will

execute regular turn-off ramping their output voltages down according to the turn-off delay and falling slew rate

settings. In addition, the DPM will clear all bits in the POL Programming Status Registers and save the contents of

the Run Time Counter into the non-volatile memory. The AC_FAIL in or RES_N in bit in the IBS Monitoring

Window will change to red. When the input is released, the DPM will first program all POL converters and then turn

them on, if the Auto Turn-On is enabled. Otherwise, the user will need to send the turn-on command via the I2C

bus.

The ACFAIL_N is typically connected to an AC-DC front end. Whenever the AC voltage disappears, the

ACFAIL_N signal will be set low. If there is no battery backup, it usually means the DC output will disappear after

20ms. If the turn-off delays and falling slew rates of each POL converter are set to the values such that all POL

converters will have fully turned off within the hold time of the AC-DC front end, then output voltage tracking during

turn-off is guaranteed.

The RES_N input has the same functionality as the ACFAIL_N input and can be connected to a simple turn on/off

switch or to a sensor that shuts the entire system down when it is activated.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 28 of 36

The ACFAIL_N and RES_N inputs should be controlled with open collector devices. The propagation delay between

the external device pulling the input low and the DPM pulling down OK lines and triggering the turn-off process is

approximately 1ms.

10.6.2 Front End Enable

The FE_EN pin is dedicated to the control of a DC-DC Front End. The Front End is typically used to convert the

48V into the intermediate bus voltage (IBV). If the DPM is powered from an auxiliary source, not from the IBV, it

can control the DC-DC Front End.

When FE_EN is internally pulled up to 3.3V, the Front End is enabled. The FE_EN output can provide up to 5mA

of current. When the FE_EN goes low, the Front End is disabled. The Front End can be enabled and disabled via

the GUI IBS Monitoring Window or directly via the I2C bus using specific commands.

The FE_EN pin should not be directly connected to the Enable pin of the DC-DC Front End. Typically, the Enable

pin is referenced to the primary side of the Front End that is isolated from the low voltage secondary side. In

addition, the Enable pin can be pulled up internally to a voltage potentially damaging to the DPM FE_EN output.

The best method is to interface the DPM with the Front End through an optocoupler as shown in Figure 18. This

configuration provides interface for negative logic front ends.

Front End

DPM

FE_EN

R

Enable

Q

3.3k

-VIN

GND

Figure 18. Interface Between DPM and DC-DC Front End

10.6.3 Crowbar

When the crowbar protection is enabled, the CB pin is internally pulled up to 3.3V for 1ms. It is capable of supplying

5mA to turn on a crowbar circuit.

10.6.4 HRES_N

The HRES_N is an active low digital input. When it is pulled low, the DPM will perform full hardware reset including

processor, memory, and communication interface. The POL converters and auxiliary devices will be turned off

although sequencing and tracking during the turn-off are not guaranteed. Communication with a host processor or

GUI (if established) will be lost. When the input is released, the DPM will first program all POL converters and then

turn them on, if the Auto Turn-On is enabled.

Unlike all other I/O pins on the DM7300 DPM, the HRES_N does not have an internal ESD protection diode

connected to VDD. Therefore, it is necessary to add the diode externally as shown in Figure 3.

The HRES_N function is intended as an emergency reset and except as indicated below, should not be used

in normal system operation.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 29 of 36

It is necessary to use an external reset circuit (see Fig. 3) to hold the HRES_N line low until the VDD supply reaches

steady state conditions. Power-One Inc. successfully tested the On-Semi voltage detector p/n NCP303LSN27T1

although other similar devices can also be utilized. Alternatively, the HW_RES pin can be connected to the output of a

CPLD (or similar device) and controlled via the system supervisory circuitry.

10.7

Communication Interfaces

10.7.1 I²C Interface

The DM7300 series DPMs have the industry standard I2C interface fully meeting the requirements of the I2C -Bus

Specification Version 2.1 from Philips Semiconductors. The I2C interface is working in the following configurations:

•

standard (100kbs) and fast (400kbs) data transfer rates

•

7-bit addressing: 4 MSBs fixed, 3 LSBs programmable by ADDR[2:0]. The address prefix of the DM7300 is

0x50. This allows encoding DPM addresses 0x50, 0x52, …, 0x5E (Bit0 is the read/write bit)

The DPM always acts as the I2C slave while the host processor always acts as the I2C master. Refer to the “DPM

Programming Manual” for the detailed description of the I2C communications.

Note: It is recommended to use Power-One’s ZM00056-KIT USB to I²C Adapter kit for the communication

between a DPM and a computer with the Power-One I²CGraphical User Interface

10.7.1.1 Watchdog Timer

In order to prevent occasional hanging of the I2C bus, a watchdog timer is started whenever an I2C command is

initiated. If the command is not executed before the watchdog times out, the DPM will assume that the I2C bus is in

an error condition (e.g. the SCL or SDA lines are pulled low continuously) and it will reset the I2C bus. The watchdog

timeout is 1000ms. Since the watchdog function is not a part of the standard I2C specifications, it can be disabled by

the user.

10.7.2 JTAG Interface

The DM7300 series DPMs feature the JTAG interface that can be used for programming the DPM with user-specific

configuration settings. JTAG boundary-scan capabilities are not currently supported.

JTAG-programmable DPMs have unique 5-digit identifiers listed in Table 6.

Table 6. JTAG Programmable DPM Part Numbers

Base Part Number

DM7304G

5- digit identifier

65515

DM7308G

65516

DM7316G

65517

DM7332G

65518

Only the DPM part numbers listed in the table can be programmed via the JTAG interface.

Note: The DPMs can be programmed via the JTAG only once. After initial programming via the JTAG, the DPMs may be

reprogrammed via I²C as necessary

10.7.2.1 SVF File

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 30 of 36

In order to program a DPM via the JTAG interface, the Serial Vector Format (SVF) file needs to be generated. Click

Generate SVF button in the System Configuration window shown in Figure 8. It will open the SVF Generator

window shown in Figure 19.

The window allows specifying the location of the target DPM in the JTAG chain and setting delays to generate the

appropriate Serial Vector Format file. The resulting file is used to program the DPMs through the JTAG interface.

Refer to “Programming DM7300 DPMs via JTAG Interface” Application Note for more details.

Figure 19. SVF File Generator Window

10.7.2.2 JTAG Instructions

DM7300 series DPMs support only BYPASS and IDCODE instructions defined by IEEE 1149.1.

SAMPLE/PRELOAD and EXTEST instructions are not currently supported. Summary of the supported

instructions is shown in Table 7.

Table 7. JTAG Instructions

Instruction

BYPASS

IDCODE

OPCODE

1111

Register

Bypass

Function

Places the 1-bit bypass register between the TDI and TDO pins,

which allows the BST data to pass synchronously through the DPM to

other devices in the JTAG chain

0001

JTAG ID

Selects the ID register and places it between the TDI and TDO

Note: The Instruction Register is 4-bit wide

10.7.2.3 Identification Register

Format and contents of the JTAG Identification Register are shown in Table 8.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 31 of 36

Table 8. JTAG ID Register

MSB

LSB

Bit

31

28 27

12 11

1

0

1

Description

Contents

Version

0000

Part Number

1001010100000010

Manufacturer’s Identity

00000011111

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 32 of 36

11

Pinout Table

Pin Name

Pin No.

Pin Type

Buffer Type

Pin Description

Notes

6, 25,

VDD

Supply

---

Positive Supply

42, 57, 60

8, 9, 26

38, 43, 58

VSS

SD

Supply

I/O

---

Ground

56

ST/OCPU

Sync-Data Line

OKA

OKB

OKC

OKD

11

13

20

53

I/O

ST/OCPU

OK Lines

FE_EN

CB

17

23

30

27

O

CMOS

ST/OC

Front-End Enable

Crowbar Trigger

I²C Interface

SDA

SCL

I/O

I²C Interface

ADDR0

ADDR1

ADDR2

IN0_N

IN1_N

IN2_N

IN3_N

TCK

TMS

TDO

TDI

EN0

47

46

45

41

40

37

36

31

32

33

34

5

I

STPU

I²C Interface Address

Interrupts

Leave open, if JTAG

interface is not utilized

JTAG Interface

EN1

EN2

EN3

PG0

PG1

PG2

PG3

7

O

I

CMOS

STPU

Auxiliary Device Enables

Auxiliary Device Power Good

55

50

54

52

51

49

RES_N

ACFAIL_N

LCK_N

18

16

61

I

STPU

System Soft Reset

AC-Fail Trigger

Write Protect Lock

See important usage

instructions in

paragraph 10.6.4

HRES_N

IBVS

4

I

STPU

Cold Reset

Intermediate Bus Voltage

Sense

48

I

A

AREF

IR

44

63

-

Analog Reference

Internal Reset

Connect to VSS via 10k

Leave floating

1, 2, 3, 10, 12,

14, 15, 19, 21,

22, 24, 28, 29,

35, 39, 59, 62, 64

nc

-

No Connect

Legend: I=input, O=output, I/O=input/output, P=power, ST=Schmitt-trigger, OCPU=open collector with pull-up, OC=open collector,

CMOS=CMOS output stage, STPU=Schmitt-trigger with pull-up, A=analog

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 33 of 36

12

Pins Description

ACFAIL_N, AC Fail Input (Pin 16): Schmitt-Trigger

input with internal pull-up resistor (active low). Pulling low

the input indicates to the DPM that an AC-DC front-end

has lost the mains and that a system shut down should

immediately be initiated.

IR, Internal Reset (Pin 63): Connect to VSS via a

10kOhm resistor.

LCK_N, Memory Lock (Pin 61): Active low input with

internal pull-up. When LCK_N is pulled low, all memory

within the DPM is write-protected. The write protection

cannot be disabled by software.

ADDR[0:2], I²C Address Inputs (Pins 47, 46, 45): Inputs

with internal pull-up resistor. The 3 bit encoded address

determines the DPM communication address for the I²C

interface.

OKA, OKB, OKC, OKD, Group OK Signals (Pins 11,

13, 20, 53): An open drain input/output with internal pull-

up resistor. Pulling low the OK input will indicate to the

DPM a fault in a Group, the DPM can also pull an OK line

low to disable a Group.

AREF, Analog Reference (Pin 44): An analog reference

which is used internally. A 10nF capacitor should be

connected as close as possible to the package between

AREF and VSS. See 10.4.4.1.

PG[0:3], Power Good (Pins 54, 52, 51, 49): Input with

internal pull-up resistor. The pin is used to read the status

of an Auxiliary Device.

CB, Crowbar Output (Pin 23): A CMOS output which is

used to trigger a crowbar (SCR) in case of overvoltage on

the Intermediate Voltage Bus.

RES_N, Active Low Reset In/Out (Pin 18): Input with

internal pull-up resistor. When pulled low a soft reset of the

system (sequenced turned off of all POLs and Auxiliary

Devices) is initiated. When released the whole system is

reprogrammed and started if necessary.

EN[0:3], Enable Outputs for Auxiliary Devices (Pins 5,

7, 55, 50): CMOS outputs to control Auxiliary Devices like

linear regulators, analog POLs, fans or other devices.

.FE_EN, Front-End Enable (Pin 17): A CMOS output

which is used to turn-on/off the DC/DC converter

generating the IBV.

SD, Sync Data Line (Pin 56): An open drain input /

output with internal pull-up resistor. Communication line to

distribute a master clock to all converters and at the same

time to communicate with all POLs.

HRES_N, Hardware Reset (Pin 4): Input with internal

pull-up resistor. When pulled low a cold start of the Digital

Power Manager is initiated. Refer to paragraph 10.6.4 for

important information regarding connections of this pin.

JTAG Interface (Pins 34, 33, 32, 31): Connect to a JTAG

IEEE-1149.1-compliant programmer supporting SVF files

or leave open, if not used.

IBVS, Intermediate Voltage Bus Sense (Pin 48): Analog

input to an internal ADC circuit to measure the

Intermediate Bus Voltage. The full scale range of the input

is 2.56V and the IBV should be scaled down by a factor of

5.7 for proper reporting of the IBV with the dPwer™ GUI.

VDD, Positive Supply (Pins 6, 25, 42, 57, 60): Supply

voltage. At least 4x100nF decoupling capacitors should be

connected between VDD and VSS pins. All VDD pins

must be connected.

VSS, Ground (Pins 8, 9, 26, 38, 43, 58): Ground.

Decoupling capacitors need to be connected as close as

possible to the pins. All VSS pins must be connected.

INT[0:3], Interrupts (Pins 41, 40, 37, 36): Four active low

inputs with internal pull-ups. Each of the inputs can be

configured for two functions: first, the interrupt input acts

on the OK line(s) to stop momentarily the operation of

group of POLs and Auxiliary Devices, second the interrupt

can be used as a hot swap trigger. In this function the

interrupt input triggers the programming of a group. When

released, POLs are assumed to be disconnected from the

DPM.

nc, No Connect (Pin 1, 2, 3, 10, 12, 14, 15, 19, 21, 22, 24,

28, 29, 35, 39, 59, 62, 64): All nc pins must remain floating.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 34 of 36

13

Mechanical Drawings

Figure 20. DM7300 Mechanical Drawing

Figure 21. DM7300 Terminals

mm

inch

MIN

0.80

0.0

NOM

-

MAX

1.00

0.05

MIN

0.032

0.000

NOM

MAX

0.040

0.002

A

-

J

A1

D/E

D1/E1

D2/E2

N

0.01

0.20 ref

9.00 BSC

8.75 BSC

4.70

0.008 ref

0.354 BSC

0.344 BSC

4.50

0.24

4.90

0.60

0.177 0.185 0.193

64

P

0.42

0.50 BSC

0.40

0.009 0.016 0.024

0.020 BSC

e

L

0.30

0.18

0.55

0.30

0.012 0.016 0.022

0.007 0.010 0.012

b

0.25

Notes

1. Compliant to JEDEC standard MO-220 variation VMMD-3

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 35 of 36

Figure 22. DM7300 Mechanical Drawing – Top View

1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not designed, intended for use in, or authorized for use as critical

components in life support systems, equipment used in hazardous environments, or nuclear control systems without the express written

consent of the respective divisional president of Power-One, Inc.

2. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on

the date manufactured. Specifications are subject to change without notice.

I²C is a trademark of Philips Corporation.

ZD-00896 Rev. 5.2, 9-Apr-13

www.power-one.com Page 36 of 36


型号：	DM7300
厂家：	POWER-ONE
描述：	DM7300G Series Digital Power Manager DM7300G系列数字电源管理器
文件：	总36页 (文件大小：1964K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DM7300 [POWER-ONE]

相关型号：

DM7304G

DM7308G

DM7308G-65512-B1

DM7316G

DM7316G-65513-B1

DM7316G-65513-R100

DM7332G

DM7332G-65514-B1

DM74

DM7400

DM7400CW

DM7400J