LNK408 [POWERINT]
LinkSwitch-PH LED Driver IC Family;
| 型号： | LNK408 |
| 厂家： | 
Power Integrations |
| 描述： | LinkSwitch-PH LED Driver IC Family |
| 文件： | 总20页 (文件大小：2314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LNK403-409/413-419
™
LinkSwitch-PH LED Driver IC Family
Single-Stage PFC, Primary-Side Constant Current Control
and TRIAC Dimming/Non-Dimming Options
Product Highlights
Dramatically Simplifies Off-line LED Drivers
•ꢀ Single-stage combination of power factor correction and
accurate constant-current (CC) output
•ꢀ Enables very long lifetime designs (no electrolytic capacitors)
•ꢀ Eliminates optocoupler and all secondary current control
circuitry
R
V
AC
IN
LinkSwitch-PH
CONTROL
D
S
V
•ꢀ Eliminates control loop compensation circuitry
•ꢀ Simple primary-side PWM dimming interface
•ꢀ Universal input voltage range
BP
R
FB
•ꢀ LNK403-409 optimized for flicker-free TRIAC dimming
EcoSmart™ – Energy Efficient
PI-6543-082211
•ꢀ Single-stage PFC combined with output CC control
•ꢀ Greatly increases efficiency, >90% achievable
•ꢀ Reduces component count
Figure 1. Typical Application Schematic.
•ꢀ No current sense resistors
•ꢀ Low standby power remote ON/OFF feature
(<50 mW at 230 VAC)
Output Power Table1,2
RV = 2 MW
RV = 4 MW
85-308 VAC
85-132 VAC
Product5
Accurate and Consistent Performance
•ꢀ Compensates for transformer inductance variations
•ꢀ Compensates for line input voltage variation
Minimum Maximum Minimum
Maximum
Output
Output
Output
Output
Power3
Power4
Power3
Power4
•ꢀ Frequency jittering greatly reduces EMI filter size and cost
LNK403/413E/L
LNK404/414E/L
LNK405/415E/L
LNK406/416E/L
LNK407/417E/L
LNK408/418E/L
LNK409/419E/L
2.5 W
2.5 W
3.8 W
4.5 W
5.5 W
6.8 W
8.0 W
4.5 W
5.5 W
7.0 W
8.0 W
10 W
6.5 W
6.5 W
8.5 W
10 W
12 W
16 W
18 W
12 W
15 W
18 W
22 W
25 W
35 W
50 W
Advanced Protection and Safety Features
•ꢀ Auto-restart for short-circuit protection
•ꢀ Open circuit fault detection mode
•ꢀ Automatic thermal shutdown restart with hysteresis
•ꢀ Meets high voltage creepage requirement between DRAIN and
all other signal pins both on PCB and at package
13.5 W
20 W
Green Package
•ꢀ Halogen free and ROHS compliant package
Table 1. Output Power Table.
Notes:
1. Continuous power in an open frame with adequate heat sinking at device local
ambient of 70 °C.
2. Power level calculated on typical LED string voltage with efficiency >80%.
3. Minimum output power with CBP = 10 mF.
Applications
•ꢀ Off-line LED driver
4. Maximum output power with CBP = 100 mF. LNK4x3EG CBP = 10 mF.
5. Package: eSIP-7C, eSIP-7F.
Description
The LinkSwitch-PH dramatically simplifies implementation of LED
drivers requiring long lifetime, high efficiency, PF >0.9, and TRIAC
dimming capability (LNK403-409). The single-stage combined
power factor and constant-current controller eliminates a switching
stage and the electrolytic bulk capacitor. The advanced primary-
side control used by the LinkSwitch-PH device provides accurate
constant current control while eliminating the need for an
optocoupler and current sensing circuits.
LinkSwitch-PH incorporates a 725 V power FET, a continuous-
mode PWM controller, a high voltage switched current source for
self biasing, frequency jittering, protection circuitry including
cycle-by-cycle current limit and hysteretic thermal shutdown.
eSIP-7F (L Package)
eSIP-7C (E Package)
Figure 2. Package Options.
www.powerint.com
August 2011
LNK403-409/413-419
DRAIN (D)
5.9 V
BYPASS (BP)
REGULATOR
BYPASS
CAPACITOR
SELECT
SOFT-START
TIMER
HYSTERETIC
THERMAL
SHUTDOWN
+
-
FAULT
PRESENT
ILIM
MI
5.9 V
5.0 V
AUTO-RESTART
COUNTER
BYPASS PIN
UNDERVOLTAGE
Gate
Driver
1 V
VOLTAGE
MONITOR (V)
SenseFet
LEB
STOP
LOGIC
JITTER
CLOCK
Comparator
OSCILLATOR
-
+
FBOFF
DCMAX
3-VT
OCP
UV/OV
LINE
+
-
SENSE
CURRENT LIMIT
COMPARATOR
ILIM
IV
FEEDBACK (FB)
PFC/CC
CONTROL
VSENSE
VBG
MI
IFB
FBOFF
DCMAX
FEEDBACK
SENSE
IS
REFERENCE
BLOCK
REFERENCE (R)
VBG
6.4 V
PI-5431-102610
SOURCE (S)
Figure 3. Functional Block Diagram.
VOLTAGE MONITOR (V) Pin:
Pin Functional Description
This pin interfaces with an external input line peak detector,
consisting of a rectifier, filter capacitor and resistors. The
applied current is used to control stop logic for line under-
voltage (UV), overvoltage (OV), provide feed-forward to control
the output current and the remote ON/OFF function.
DRAIN (D) Pin:
This pin is the power FET drain connection. It also provides
internal operating current for both start-up and steady-state
operation.
SOURCE (S) Pin:
Exposed Pad
(Backside) Internally
Connected to
This pin is the power FET source connection. It is also the
ground reference for the BYPASS, FEEDBACK, REFERENCE and
VOLTAGE MONITOR pins.
SOURCE Pin
E Package (eSIP-7C)
L Package (eSIP-7F)
(Top View)
BYPASS (BP) Pin:
This is the connection point for an external bypass capacitor for
the internally generated 5.9 V supply. This pin also provides
output power selection through choice of the BYPASS pin
capacitor value.
7 D
5 S
4 BP
3 FB
2 V
1 R
3
5
1
R
FEEDBACK (FB) Pin:
Exposed Pad
(backside) Internally
Connected to
SOURCE Pin (see
eSIP-7C Package
Drawing)
FB S
The FEEDBACK pin is used for output voltage feedback. The
current into the FEEDBACK pin is directly proportional to the
output voltage. The FEEDBACK pin also includes circuitry to
protect against open load and overload output conditions.
2
4
7
D
Lead Bend Outward
from Drawing
V BP
(Refer to eSIP-7F Package
Outline Drawing)
PI-5432-082411
Figure 4. Pin Configuration.
REFERENCE (R) Pin:
This pin is connected to an external precision resistor and is
used to configure for dimming (LNK403-409) and non-TRIAC
dimming (LNK413-419) modes of operation.
2
Rev. D 08/11
www.powerint.com
LNK403-409/413-419
the line undervoltage and overvoltage thresholds of the
VOLTAGE MONITOR pin. For non-dimming or PWM dimming
applications with LNK413-419, the external resistor should be a
24.9 kW 1%, for high-line and universal input voltage designs,
and 49.9 kW 1% for low-line input voltage designs. For phase
angle AC dimming with LNK403-409, the external resistor
should be a 49.9 kW 1%. One percent resistors are
Functional Description
A LinkSwitch-PH device monolithically integrates a controller and
high-voltage power FET into one package. The controller
implements both high power factor and a constant current
output in a single stage. The LinkSwitch-PH controller consists
of an oscillator, feedback (sense and logic) circuit, 5.9 V regulator,
hysteretic over-temperature protection, frequency jittering,
cycle-by-cycle current limit, auto-restart, inductance correction,
power factor and constant current control.
recommended as the resistor tolerance directly affects the
output tolerance. Other resistor values should not be used.
BYPASS Pin Capacitor Power Gain Selection
FEEDBACK Pin Current Control Characteristics
LinkSwitch-PH devices have the capability to tailor the internal
gain to either full or a reduced output power setting. This allows
selection of a larger device to minimize dissipation for both
thermal and efficiency reasons. The power gain is selected with
the value of the BYPASS pin capacitor. The full power setting is
selected with a 100 mF capacitor and the reduced power setting
(for higher efficiency) is selected with a 10 mF capacitor. The
BYPASS pin capacitor sets both the internal power gain as well
as the over-current protection (OCP) threshold. Unlike the
larger devices, the LNK4x3 power gain is not programmable.
Use a 10 mF capacitor for the LNK4x3.
The figure shown below illustrates the operating boundaries of
the FEEDBACK pin current. Above IFB(SKIP) switching is disabled
and below IFB(AR) the device enters into auto-restart.
IFB(SKIP)
Skip-Cycle
CC Control
Region
IFB
Switching Frequency
The switching frequency is 66 kHz. To further reduce the EMI
level, the switching frequency is jittered (frequency modulated)
by approximately 1 kHz.
IFB(DCMAXR)
Soft-Start
The controller includes a soft-start timing feature which inhibits
the auto-restart protection feature for the soft-start period (tSOFT
to distinguish start-up into a fault (short-circuit) from a large
output capacitor. At start-up the LinkSwitch-PH clamps the
maximum duty cycle to reduce the output power. The total
)
Soft-Start and
CC Fold-Back
Region
soft-start period is tSOFT
.
Remote ON/OFF and EcoSmart
The VOLTAGE MONITOR pin has a 1 V threshold comparator
connected at its input. This voltage threshold is used for
remote ON/OFF control. When a signal is received at the
VOLTAGE MONITOR pin to disable the output (VOLTAGE
MONITOR pin tied to ground through an optocoupler photo-
IFB(AR)
Auto-Restart
DC10
Maximum Duty Cycle
DCMAX
PI-5433-060410
transistor) the LinkSwitch-PH will complete its current switching
cycle before the internal power FET is forced off.
Figure 5. FEEDBACK Pin Current Characteristic.
The FEEDBACK pin current is also used to clamp the maximum
duty cycle to limit the available output power for overload and
open-loop conditions. This duty cycle reduction characteristic
also promotes a monotonic output current start-up
characteristic to prevent over-shoot.
The remote ON/OFF feature can also be used as an eco-mode
or power switch to turn off the LinkSwitch-PH and keep it in a
very low power consumption state for indefinite long periods.
When the LinkSwitch-PH is remotely turned on after entering
this mode, it will initiate a normal start-up sequence with
soft-start the next time the BYPASS pin reaches 5.9 V. In the
worst case, the delay from remote on to start-up can be equal
to the full discharge/charge cycle time of the BYPASS pin. This
reduced consumption remote off mode can eliminate expensive
and unreliable in-line mechanical switches.
REFERENCE Pin
The REFERENCE pin is tied to ground (SOURCE) via an
external resistor. The value selected sets the internal
references, determining the operating mode for dimming
(LNK403-409) and non-dimming (LNK413-419) operation and
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Rev. D 08/11
LNK403-409/413-419
Over-Current Protection
The current limit circuit senses the current in the power FET.
When this current exceeds the internal threshold (ILIMIT), the power
FET is turned off for the remainder of that cycle. A leading edge
blanking circuit inhibits the current limit comparator for a short
time (tLEB) after the power FET is turned on. This leading edge
blanking time has been set so that current spikes caused by
capacitance and rectifier reverse recovery will not cause
premature termination of the power FET conduction.
D
S
V
CONTROL
BP
R
FB
Line Under/Overvoltage Protection
This device includes both line under- and overvoltage detection
to limit the minimum start-up and maximum operating voltage
detected through the VOLTAGE MONITOR pin. An external peak
detector consisting of a diode and capacitor are required to
provide input line peak voltage to the VOLTAGE MONITOR pin
through a resistor. At power up, IUV+ keeps the LinkSwitch-PH
off until the input line voltage reaches the undervoltage threshold.
At power down, IUV- prevents restart attempts after the output
goes out of regulation.
PI-5435-052510
Figure 6. Remote ON/OFF VOLTAGE MONITOR pin Control
5.9 V Regulator/Shunt Voltage Clamp
The internal 5.9 V regulator charges the bypass capacitor
connected to the BYPASS pin to 5.9 V by drawing a current
from the voltage on the DRAIN pin whenever the power FET is
off. The BYPASS pin is the internal supply voltage node. When
the power FET is on, the device operates from the energy
stored in the bypass capacitor. Extremely low power
consumption of the internal circuitry allows LinkSwitch-PH
to operate continuously from current it takes from the DRAIN
pin. A bypass capacitor value of 10 or 100 mF is sufficient for
both high frequency decoupling and energy storage. In
addition, there is a 6.4 V shunt regulator clamping the BYPASS
pin at 6.4 V when current is provided to the BYPASS pin
through an external resistor. This facilitates powering of
LinkSwitch-PH externally through a bias winding to increase
operating efficiency. It is recommended that the BYPASS pin is
supplied current from the bias winding for normal operation.
The same resistor used for UV also sets line overvoltage (OV)
shutdown threshold which, once exceeded, forces the
LinkSwitch-PH to stop switching (after completion of the current
switching cycle). Once the line voltage returns to normal, the
device resumes normal operation. A small amount of hysteresis
is provided on the OV threshold to prevent noise triggering.
When the power FET is off, the rectified DC high voltage surge
capability is increased to the voltage rating of the power FET
(725 V), due to the absence of the reflected voltage and leakage
spikes on the drain.
Hysteretic Thermal Shutdown
The thermal shutdown circuitry senses the controller die
temperature. The threshold is set at 142 °C typical with a 75 °C
hysteresis. When the die temperature rises above this threshold
(142 °C) the power FET is disabled and remains disabled until
the die temperature falls by 75 °C, at which point the power FET
is re-enabled.
Auto-Restart
In the event of an open-loop fault (open FEEDBACK pin resistor
or broken path to feedback winding), output short-circuits or an
overload condition the controller enters into the auto-restart
mode. The controller annunciates both short-circuit and
open-loop conditions once the FEEDBACK pin current falls
below the IFB(AR) threshold after the soft-start period. To
minimize the power dissipation under this fault condition the
shutdown/auto-restart circuit turns the power supply on (same
as the soft-start period) and off at an auto-restart duty cycle of
typically DCAR for as long as the fault condition persists. If the
fault is removed during the auto-restart off-time, the power
supply will remain in auto-restart until the full off-time count is
completed. Special consideration must be made to appropriately
size the output capacitor to ensure that after the soft-start
period (tSOFT) the FEEDBACK pin current is above the IFB(AR)
threshold to ensure successful power-supply start-up.
After the soft-start time period, auto-restart is activated only
Safe Operating Area (SOA) Protection
The device also features a safe operating area (SOA) protection
mode which disables FET switching for 40 cycles in the event
the peak switch current reaches the ILIMIT threshold and the
switch on-time is less than tON(SOA). This protection mode
protects the device under short-circuited LED conditions and at
start-up during the soft-start period when auto-restart protection
is inhibited. The SOA protection mode remains active in normal
operation.
when the FEEDBACK pin current falls below IFB(AR)
.
4
Rev. D 08/11
www.powerint.com
LNK403-409/413-419
Input Stage
Application Example
Fuse F1 provides protection from component failures while RV1
provides a clamp during differential line surges, keeping the
peak drain voltage of U1 below the 725 V rating of the internal
power FET. Bridge rectifier BR1 rectifies the AC line voltage.
EMI filtering is provided by L1-L3, C1, R16 and R17 together with
the safety rated Y class capacitor (C7) that bridges the safety
isolation barrier between primary and secondary. Resistor R16
and R17 act to damp any resonances formed between L1, L2,
C1 and the AC line impedance. A small bulk capacitor (C2) is
required to provide a low impedance source for the primary
switching current. The maximum value of C1 and C2 is limited in
order to maintain a power factor of greater than 0.9.
14 W TRIAC Dimmable High Power Factor LED Driver
Design Example
The circuit schematic in Figure 7 shows a TRIAC dimmable high
power-factor LED driver based on LNK406EG from the
LinkSwitch-PH family of devices. It was optimized to drive an
LED string at a voltage of 28 V with a constant current of 0.5 A
( 5%) ideal for PAR lamp retro-fit applications. The design
operates over a universal input voltage range of 90 VAC to
265 VAC but provides the specified output current tolerance
over a line voltage range of 90 VAC to 132 VAC (this is configurable
for high-line only applications by simple component value changes).
LinkSwitch-PH Primary
To provide peak line voltage information to U1 the incoming
rectified AC peak charges C3 via D2. This is then fed into the
VOLTAGE MONITOR pin of U1 as a current via R2 and R3. This
sensed current is also used by the device to set the line input
overvoltage and undervoltage protection thresholds. Resistor
R1 provides a discharge path for C3 with a time constant much
longer than that of the rectified AC to prevent generation of line
frequency ripple.
The key goals of this design were compatibility with standard
leading edge TRIAC AC dimmers, very wide dimming range
(1000:1, 500 mA:0.5 mA), high efficiency (>85%) and high power
factor (>0.9). The design is fully protected from faults such as
no-load, overload and output short-circuit conditions and over
temperature.
Circuit Description
The LinkSwitch-PH device (U1) integrates the power FET,
controller and start-up functions into a single package reducing
the component count versus typical implementations. Configured
as part of an isolated continuous conduction mode flyback
converter, U1 provides high power factor via its internal control
algorithm together with the small input capacitance of the
design. Continuous conduction mode operation results in
reduced primary peak and RMS current. This both reduces
EMI noise, allowing simpler, smaller EMI filtering components and
improves efficiency. Output current regulation is maintained
without the need for secondary side sensing which eliminates
current sense resistors and improves efficiency.
The VOLTAGE MONITOR pin current and the FEEDBACK pin
current are used internally to control the average output LED
current. For TRIAC phase-dimming applications a 49.9 kW
resistor (R4) is used on the REFERENCE pin and 4 MW (R2+R3)
on the VOLTAGE MONITOR pin to provide a linear relationship
between input voltage and the output current and maximizing
the dimming range. Resistor R4 also sets the internal line input
undervoltage and overvoltage protection thresholds.
C8
C10
R15
20 kΩ
330 µF 330 µF
28 V, 500 mA
50 V
50 V
11
1
FL1
L3
1000 µH
D8
MBRS4201T3G
R1
D2
DL4007
VR1
P6KE200A
FL2
3
240 kΩ
R9
750 kΩ
1%
1/2 W
RTN
R18
510 Ω
1 W
D3
UF4007
R8
150 Ω
C5
D6
DL4936
R7
10 kΩ
22 µF
50 V
BR1
2KBP06M
600 V
R16
1 kΩ
2
R2
2 MΩ
1%
R10
750 kΩ
1%
T1
RM8
F1
3.15 A
L
R3
2 MΩ
1%
D4
UF4002
L1
1000 µH
C3
C2
C1
C11
D5
90 - 265
VAC
1 µF
400 V
100 nF
47 nF
220 nF
630 V
RV1
275 VAC
1N4148
630 V
275 VAC
L2
R5
3 kΩ
1000 µH
R6
162 kΩ
1%
D
S
V
D7
VR2
ZMM5245B-7
15 V
N
D1
CONTROL
LinkSwitch-PH
U1
LNK406EG
BAV21WS-7-F
DL4002
BP
R17
1 kΩ
VR3
ZMM5259B-7
39 V
R12
Q3
MMBT3904
R
FB
15 Ω
1%
Q2
IRFR310
C6
15 nF
50 V
R4
Q1
FMMT558
49.9 kΩ
C12
1 µF
50 V
C13
100 nF
50 V
C4
10 µF
16 V
R13
130 Ω
1/2 W
1%
R19
1 kΩ
R11
2.4 MΩ
R20
10 kΩ
C7
2.2 nF
250 VAC
PI-5997-061510
Figure 7. Schematic of an Isolated, TRIAC Dimmable, High Power Factor, Universal Input, 14 W LED Driver.
5
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Rev. D 08/11
LNK403-409/413-419
Diode D3 and VR1 clamp the drain voltage to a safe level due to
the effects of leakage inductance. Diode D4 is necessary to
prevent reverse current from flowing through U1 for the period
of the rectified AC input voltage that the voltage across C2 falls
to below the reflected output voltage (VOR).
40% of the mean value. For designs where lower ripple is
desirable the output capacitance value can be increased. A
small pre-load is provided by R15 which limits the output
voltage under no-load conditions.
TRIAC Phase Dimming Control Compatibility
The requirement to provide output dimming with low cost,
TRIAC-based, leading edge phase dimmers introduces a
number of trade-offs in the design.
Diode D6, C5, R7 and R8 create the primary bias supply from
an auxiliary winding on the transformer. Capacitor C4 provides
local decoupling for the BYPASS pin of U1 which is the supply
pin for the internal controller. During start-up C4 is charged to
~6 V from an internal high-voltage current source tied to the
device DRAIN pin. This allows the part to start switching at
which point the operating supply current is provided from the
bias supply via R5. Capacitor C4 also selects the output power
mode (10 mF for reduced power was selected to reduce
dissipation in U1 and increase efficiency).
Due to the much lower power consumed by LED based lighting
the current drawn by the overall lamp is below the holding
current of the TRIAC within the dimmer. This can cause
undesirable behaviors such as limited dimming range and/or
flickering as the TRIAC fires inconsistently. The relatively large
impedance the LED lamp presents to the line allows significant
ringing to occur due to the inrush current charging the input
capacitance when the TRIAC turns on. This too can cause
similar undesirable behavior as the ringing may cause the
TRIAC current to fall to zero and turn off.
Feedback
The bias winding voltage is proportional to the output voltage
(set by the turns ratio between the bias and secondary
windings). This allows the output voltage to be monitored
without secondary side feedback components. Resistor R6
converts the bias voltage into a current which is fed into the
FEEDBACK pin of U1. The internal engine within U1 combines
the FEEDBACK pin current, VOLTAGE MONITOR pin current
and drain current information to provide a constant output
current over a 1.5:1 output voltage variation (LED string voltage
variation of 25%) at a fixed line input voltage.
To overcome these issues two circuits, the Active Damper and
Passive Bleeder, are incorporated. The drawback of these
circuits is increased dissipation and therefore reduced efficiency
of the supply. For non-dimming applications these components
can simply be omitted.
The Active Damper consists of components R9, R10, R11, R12,
D1, Q1, C6, VR2, Q2 in conjunction with R13. This circuit limits
the inrush current that flows to charge C2 when the TRIAC
turns on by placing R13 in series for the first 1 ms of the TRIAC
conduction. After approximately 1 ms, Q2 turns on and shorts
R13. This keeps the power dissipation on R13 low and allows a
larger value during current limiting. Resistor R9, R10, R11 and
C6 provide the 1 ms delay after the TRIAC conducts. Transistor
Q1 discharges C6 when the TRIAC is not conducting and VR2
clamps the gate voltage of Q2 to 15 V.
To limit the output voltage at no-load an output overvoltage
protection circuit is set by D7, C12, R20, VR3, C13, Q3 and R19.
Should the output load be disconnected then the bias voltage
will increase until VR3 conducts, turning on Q3 and reducing
the current into the FEEDBACK pin. When this current drops
below 20 mA the part enters auto-restart and switching is
disabled for 1500 ms allowing time for the output and bias
voltages to fall.
Output Rectification
The Passive Bleeder circuit is comprised of C11 and R18. This
helps to keep the input current above the TRIAC holding current
while the input current corresponding to the effective driver
resistance increases during each AC half-cycle.
The transformer secondary winding is rectified by D8 and
filtered by C8 and C10. A Schottky barrier diode was selected
for efficiency and the combined value of C8 and C10 were
selected to give peak-to-peak and LED ripple current equal to
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LNK403-409/413-419
7 W High Power Factor Non-Dimmable LED Driver
Design Example with Enhanced Line Regulation
pin provides excellent line regulation over the entire 90 VAC to
265 VAC input range.
The circuit schematic in Figure 7 shows a high power-factor
LED driver based on a LNK413EG from the LinkSwitch-PH
family of devices. It was optimized to drive an LED string at a
voltage of 21 V with a constant current of 0.33 A, ideal for
PAR20/PAR30 lamp retro-fit applications. The design operates
over the universal input voltage range of 90 VAC to 265 VAC
and is a non-dimming application. A non-dimming application
has tighter output current variation with changes in the line
voltage than a dimming application. It’s key to note that, although
not specified for dimming, no circuit damage will result if the
end user does operate the design with a phase controlled
dimmer.
The VOLTAGE MONITOR pin current is also used by the device
to set the line input overvoltage and undervoltage protection
thresholds.
Diode D1 and VR1 clamp the drain voltage to a safe level due to
the effects of leakage inductance. A Zener clamp was selected
for lowest component count and highest efficiency. Diode D5 is
necessary to prevent reverse current from flowing through U1
during the period when the AC input voltage is lower than the
reflected output voltage (VOR). A space efficient RM6 core was
selected for this design. The RM core geometry helps
minimizes audible noise but requires the use of flying leads to
meet safety spacing requirements.
Circuit Description
Diode D3, C6, R5, R9 and R18 create the primary bias supply
from an auxiliary winding on the transformer. Resistor R5
provides filtering of leakage inductance generated voltage
spikes to improve tracking of the bias and output voltages. It
also forms a pole with C6 at ~100 Hz. Resistors R9 and R18
act as a small load to ensure that the bias voltage collapses
during output short-circuit when U1 enters auto-restart
operation to protect the supply.
Input Stage
Fuse F1 provides protection from component failures while RV1
provides a clamp during differential line surges, keeping the
peak drain voltage of U1 below the 725 V rating of the internal
power FET. Bridge rectifier BR1 rectifies the AC line voltage.
EMI filtering is provided by L1-L3, C2 together with the safety
rated Y class capacitor (C7) that bridges the safety isolation
barrier between primary and secondary. Resistor R2 and R3
act to damp any resonances formed between L1, L2, C2 and
the AC line impedance. A small bulk capacitor (C3) is required
to provide a low impedance source for the primary switching
current. The maximum value of C2 and C3 is limited in order to
maintain a power factor of greater than 0.9.
Output overvoltage and load disconnection protection is
provided by D8, C14, R24, VR3, C15, R23 and Q2. Should the
output LED load become disconnected the output voltage will
rise causing an associated rise in the bias winding voltage
across C14. Once this exceeds the voltage rating of VR3, Q2
turns on pulling down the FEEDBACK pin of U1 and initiating
auto-restart operation. Once in auto-restart the low duty cycle
of operation (~3%) together with the small pre-load on the
output prevents the output voltage rising to a high level. Once
the output load is reconnected normal operation resumes.
LinkSwitch-PH Primary
To provide peak line voltage information to U1 the incoming
rectified AC peak charges C8 via D6. This is then fed into the
VOLTAGE MONITOR pin of U1 as a current via R4, R7 and R8.
The VOLTAGE MONITOR pin current and the FEEDBACK pin
current are used internally to control the average output LED
current. The combined value of R4, R7 and R8 (3.909 MW)
and R11, R12 (1.402 MW) connected to the VOLTAGE MONITOR
Capacitor C12 provides local decoupling for the BYPASS pin of
U1 which is the supply pin for the internal controller. During
C5
C4
R6
20 kΩ
150 µF 150 µF
21 V, 330 mA
35 V
35 V
FL1
1
FL2
L3
1000 µH
D2
MBRS4201T3G
D6
DL4007
VR1
P6KE200A
FL3
6
RTN
D1
UF4007
R5
75 Ω
C6
D3
DL4936
22 µF
R4
50 V
2 MΩ
BR1
DF06S-E3/45
600 V
2
R2
1%
1 kΩ
R18
R9
T1
RM6
R7
1 MΩ
1%
F1
3.15 A
10 kΩ 10 kΩ
L
D5
L1
R8
909 kΩ
1%
C3
100 nF
400 V
C8
1 µF
400 V
ES1D
1000 µH
C2
90 - 265
VAC
22 nF
D4
RV1
275 VAC
1N4148
275 VAC
L2
1000 µH
R10
3 kΩ
D
S
V
R15
150 kΩ
D8
R11
1.0 MΩ
1%
N
CONTROL
BAV21WS-7-F
LinkSwitch-PH
U1
LNK413EG
BP
R3
1 kΩ
VR3
ZMM5259B-7
39 V
Q2
MMBT3904
R
FB
R12
402 kΩ
1%
R19
24.9 kΩ
1%
C14
1 µF
50 V
C15
100 nF
50 V
C12
R24
10 kΩ
R23
1 kΩ
10 µF
10 V
C7
2.2 nF
250 VAC
PI-5991-101210
Figure 8. Schematic of an Isolated, Non-Dimmable, High Power Factor, Universal Input, 7 W LED Driver.
7
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Rev. D 08/11
LNK403-409/413-419
start-up C4 is charged to ~6 V from an internal high-voltage
current source tied to the device DRAIN pin. Once the bias
voltage has risen into regulation the operating supply current is
provided via R10. Diode D4 prevents U1 from charging C6
during start-up which would increase the start-up delay time.
100 mF BYPASS pin capacitor for all but the LNK4x3 which has
only one power setting. In all cases in order to obtain the best
output current tolerance maintain the device temperature below
100 °C
Maximum Input Capacitance
Feedback
To achieve high power factor, the capacitance used in both the
EMI filter and for decoupling the rectified AC (bulk capacitor)
must be limited in value. The maximum value is a function of
the output power of the design and reduces as the output
power reduces. For the majority of designs limit the total
capacitance to less than 200 nF with a bulk capacitor value of
100 nF. Film capacitors are recommended compared to
ceramic types as they minimize audible noise with operating
with leading edge phase dimmers. Start with a value of 10 nF
for the capacitance in the EMI filter and increase in value until
there is sufficient EMI margin.
The bias winding voltage is proportional to the output voltage
(set by the turns ratio between the bias and secondary
windings). This allows the output voltage to be monitored
without secondary side feedback components. Resistor R15
converts the bias voltage into a current which is fed into the
FEEDBACK pin of U1. The internal engine within U1 combines
the FEEDBACK pin current, VOLTAGE MONITOR pin current
and drain current information to provide a constant output
current over a 2:1 output voltage range.
Output Rectification
The transformer secondary winding is rectified by D2 and
filtered by C4 and C5. A Schottky barrier diode was selected
for efficiency and the combined value of C4 and C5 were
selected to give an acceptable LED ripple current. For designs
where lower ripple is desirable the output capacitance value
can be increased. A small pre-load is provided by R6 which
limits the output voltage under no-load conditions.
REFERENCE Pin Resistance Value Selection
The LinkSwitch-PH family contains phase dimming devices,
LNK403-409, and non-dimming devices, LNK413-419. The
non-dimmable devices use a 24.9 kW 1% REFERENCE pin
resistor in high-line and universal input voltage designs and
49.9 kW 1% in low-line input voltage designs, for best output
current tolerance (over AC input voltage changes). The dimmable
devices use 49.9 kW 1% to achieve the widest dimming range.
Key Application Considerations
VOLTAGE MONITOR Pin Resistance Network Selection
For widest AC phase angle dimming range with LNK403-409,
use a 4 MW resistor connected to the line voltage peak detector
circuit. Make sure that the resistor’s voltage rating is sufficient
for the peak line voltage. If necessary use multiple series
connected resistors.
Power Table
The data sheet power table (Table 1) represents the minimum
and maximum practical continuous output power based on the
following conditions:
1. Efficiency of 80%
2. Device local ambient of 70 °C
3. Sufficient heat sinking to keep the device temperature
below 100 °C
For best line regulation, use a series combination of resistors
that equals 3.909 MW connected to the line voltage peak
detector. In addition, connect a 1 MW in series with a 402 kW
resistor (1.402 MW total) from the VOLTAGE MONITOR pin to
SOURCE pin. Use 1% tolerance resistors for good accuracy.
Line regulation can be further improved by using the PIXls
spreadsheet’s fine tuning section. See the LinkSwitch-PH
Application Note for more information.
4. For minimum output power column
•ꢀ Reflected output voltage (VOR) of 120 V
•ꢀ FEEDBACK pin current of 135 mA
•ꢀ BYPASS pin capacitor value of 10 mF
5. For maximum output power column
•ꢀ Reflected output voltage (VOR) of 65 V
•ꢀ FEEDBACK pin current of 165 mA
•ꢀ BYPASS pin capacitor value of 100 mF
(LNK4x3EG = 10 mF)
Primary Clamp and Output Reflected Voltage VOR
A primary clamp is necessary to limit the peak drain to source
voltage. A Zener clamp requires the fewest components and
board space and gives the highest efficiency. RCD clamps are
also acceptable however the peak drain voltage should be
carefully verified during start-up and output short-circuit as the
clamping voltage varies with significantly with the peak drain
current.
Note that input line voltages above 85 VAC do not change the
power delivery capability of LinkSwitch-PH devices.
Device Selection
Select the device size by comparing the required output power
to the values in Table 1. For thermally challenging designs, e.g.
incandescent lamp replacement, where either the ambient
temperature local to the LinkSwitch-PH device is high and/or
there is minimal space for heat sinking use the minimum output
power column. This is selected by using a 10 mF BYPASS pin
capacitor and results in a lower device current limit and
therefore lower conduction losses. For open frame design or
designs where space is available for heat sinking then refer to
the maximum output power column. This is selected by using a
For the highest efficiency, the clamping voltage should be
selected to be at least 1.5 times the output reflected voltage,
VOR, as this keeps the leakage spike conduction time short.
When using a Zener clamp in a universal input or high-line only
application, a VOR of less than 135 V is recommended to allow
for the absolute tolerances and temperature variations of the
Zener. This will ensure efficient operation of the clamp circuit
and will also keep the maximum drain voltage below the rated
breakdown voltage of the FET. An RCD (or RCDZ) clamp
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LNK403-409/413-419
provides tighter clamp voltage tolerance than a Zener clamp.
The RCD clamp is more cost effective than the Zener clamp but
requires more careful design to ensure that the maximum drain
voltage does not exceed the power FET breakdown voltage.
These VOR limits are based on the BVDSS rating of the internal
FET, a VOR of 60 V to 100 V is typical for most designs, giving
the best PFC and regulation performance.
PI-5983-060810
350
250
150
50
0.35
Voltage
Current
0.25
0.15
0.05
-0.05
-0.15
-0.25
0.5
50
100
150
200
250
300
350
400
-50
Series Drain Diode
-150
-250
An ultra-fast or Schottky diode in series with the drain is
necessary to prevent reverse current flowing through the
device. The voltage rating must exceed the output reflected
voltage, VOR. The current rating should exceed two times the
average primary current and have a peak rating equal to the
maximum drain current of the selected LinkSwitch-PH device.
-350
-0.35
Conduction Angle (°)
PI-5984-060810
350
300
250
200
150
100
50
0.35
0.3
Line Voltage Peak Detector Circuit
Voltage
Current
LinkSwitch-PH devices use the peak line voltage to regulate the
power delivery to the output. A capacitor value of 1 mF to 4.7 mF
is recommended to minimize line ripple and give the highest
power factor (>0.9), smaller values are acceptable but result in
lower PF and higher line current distortion.
0.25
0.2
0.15
0.1
Operation with Phase Controlled Dimmers
Dimmer switches control incandescent lamp brightness by not
conducting (blanking) for a portion of the AC voltage sine wave.
This reduces the RMS voltage applied to the lamp thus
reducing the brightness. This is called natural dimming and the
LinkSwitch-PH LNK403-409 devices when configured for
dimming utilize natural dimming by reducing the LED current as
the RMS line voltage decreases. By this nature, line regulation
performance is purposely decreased to increase the dimming
range and more closely mimic the operation of an incandescent
lamp. Using a 49.9 kW REFERENCE pin resistance selects
natural dimming mode operation.
0.05
0
0
50
100
0
150
200
250
300
350
400
Conduction Angle (°)
Figure 9. (a) Ideal Input Voltage and Current Waveforms for a Leading Edge
TRIAC Dimmer at 90° Conduction Angle. (b) Resultant Waveforms
Following Rectification of TRIAC Dimmer Output.
Figure 10 shows undesired rectified bus voltage and current
with the TRIAC turning off prematurely and restarting.
Leading Edge Phase Controlled Dimmers
The requirement to provide flicker-free output dimming with low
cost, TRIAC-based, leading edge phase dimmers introduces a
number of trade-offs in the design.
If the TRIAC is turning off before the end of the half-cycle
erratically or alternate half AC cycles have different conduction
angles then flicker will be observed in the LED light due to
variations in the output current. This can be solved by including
a bleeder and damper circuit.
Due to the much lower power consumed by LED based lighting
the current drawn by the overall lamp is below the holding
current of the TRIAC within the dimmer. This causes undesirable
behaviors such as limited dimming range and/or flickering. The
relatively large impedance the LED lamp presents to the line
allows significant ringing to occur due to the inrush current
charging the input capacitance when the TRIAC turns on. This
too can cause similar undesirable behavior as the ringing may
cause the TRIAC current to fall to zero and turn off.
Dimmers will behave differently based on manufacturer and
power rating, for example a 300 W dimmer requires less
dampening and requires less power loss in the bleeder than a
600 W or 1000 W dimmer due to different drive circuits and
TRIAC holding current specifications. Line voltage also has a
significant impact as at high-line for a given output power the
input current and therefore TRIAC current is lower but the peak
inrush current when the input capacitance charges is higher
creating more ringing. Finally multiple lamps in parallel driven
from the same dimmer can introduce more ringing due to the
increased capacitance of parallel units. Therefore when testing
dimmer operation verify on a number of models, different line
voltages and with both a single driver and multiple drivers in
parallel.
To overcome these issues two circuits, the Active Damper and
Passive Bleeder, are incorporated. The drawback of these
circuits is increased dissipation and therefore reduced efficiency
of the supply so for non-dimming applications these
components can simply be omitted.
Figure 9(a) shows the line voltage and current at the input of a
leading edge TRIAC dimmer with Figure 9(b) showing the
resultant rectified bus voltage. In this example, the TRIAC
conducts at 90 degrees.
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LNK403-409/413-419
PI-5985-102810
PI-5986-060810
350
0.35
0.3
350
250
150
50
0.35
0.25
0.15
0.05
-0.05
-0.15
-0.25
Voltage
Current
Voltage
Current
300
250
200
150
100
50
0.25
0.2
0
50
100
150
200
250
300
350
-50
0.15
0.1
-150
-250
0.05
-350
-0.35
0
0
50
100
0
150
Conduction Angle (°)
Figure 10. Example of Phase Angle Dimmer Showing Erratic Firing.
200
250
300
350
400
Conduction Angle (°)
Figure 11. Ideal Dimmer Output Voltage and Current Waveforms for a Trailing Edge
Dimmer at 90° Conduction Angle.
Audible Noise Considerations for Use With
Leading Edge Dimmers
Start by adding a bleeder circuit. Add a 0.44 mF capacitor and
510 W 1 W resistor (components in series) across the rectified
bus (C11 and R18 in Figure 7). If this results in satisfactory
operation reduce the capacitor value to the smallest that results
in acceptable performance to reduce losses and increase
efficiency.
Noise created when dimming is typically created by the input
capacitors, EMI filter inductors and the transformer. The input
capacitors and inductors experience high di/dt and dv/dt every
AC half-cycle as the TRIAC fires and an inrush current flows to
charge the input capacitance. Noise can be minimized by
selecting film vs ceramic capacitors, minimizing the capacitor
value and selecting inductors that are physically short and wide.
If the bleeder circuit does not maintain conduction in the TRIAC,
then add an active damper as shown in Figure 7. This consists
of components R9, R10, R11, R12, D1, Q1, C6, VR2, Q2 in
conjunction with R13. This circuit limits the inrush current that
flows to charge C2 when the TRIAC turns on by placing R13 in
series for the first 1 ms of the TRIAC conduction. After
approximately 1 ms, Q2 turns on and shorts R13. This keeps
the power dissipation on R13 low and allows a larger value to
be used during current limiting. Increasing the delay before Q2
turns on by increasing the values of resistors R9 and R10 will
improve dimmer compatibility but cause more power to be
dissipated across R13. Monitor the AC line current and voltage
at the input of the power supply as you make the adjustments.
Increase the delay until the TRIAC operates properly but keep
the delay as short as possible for efficiency.
The transformer may also create noise which can be minimized
by avoiding cores with long narrow legs (high mechanical
resonant frequency). For example, RM cores produce less
audible noise than EE cores for the same flux density. Reducing
the core flux density will also reduce the noise. Reducing the
maximum flux density (BM) to 1500 Gauss usually eliminates
any audible noise but must be balanced with the increased core
size needed for a given output power.
Thermal and Lifetime Considerations
Lighting applications present thermal challenges to the driver.
In many cases the LED load dissipation determines the working
ambient temperature experienced by the drive so thermal
evaluation should be performed with the driver inside the final
enclosure. Temperature has a direct impact on driver and LED
lifetime. For every 10 °C rise in temperature, component life is
reduced by a factor of 2. Therefore it is important to properly
heat sink and verify the operating temperatures of all devices.
As a general rule the greater the power dissipated in the bleeder
and damper circuits, the more dimmer types will work with the
driver.
Trailing Edge Phase Controlled Dimmers
Figure 11 shows the line voltage and current at the input of the
power supply with a trailing edge dimmer. In this example, the
dimmer conducts at 90 degrees. Many of these dimmers use
back-to-back connected power FETs rather than a TRIAC to
control the load. This eliminates the holding current issue of
TRIACs and since the conduction begins at the zero crossing,
high current surges and line ringing are minimized. Typically
these types of dimmers do not require damping and bleeder
circuits.
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LNK403-409/413-419
Layout Considerations
components that connect to the SOURCE pin should follow the
same rules as the BYPASS pin capacitor. It is critical that the
main power FET switching currents return to the bulk capacitor
with the shortest path as possible. Long high current paths
create excessive conducted and radiated noise.
Primary Side Connections
Use a single point (Kelvin) connection at the negative terminal of
the input filter capacitor for the SOURCE pin and bias returns.
This improves surge capabilities by returning surge currents
from the bias winding directly to the input filter capacitor. The
BYPASS pin capacitor should be located as close to the
BYPASS pin and connected as close to the SOURCE pin as
possible. The SOURCE pin trace should not be shared with the
main power FET switching currents. All FEEDBACK pin
Secondary Side Connections
The output rectifier and output filter capacitor should be as
close as possible. The transformer’s output return pin should
have a short trace to the return side of the output filter capacitor.
Clamp
Bulk Capacitor
LNK403EG
FL1
6
1
R14
Input EMI Filter
2
VR1
R2
C2
Transformer
D1
C3
C8
L3
5
U1
C9
4
3
F1
T1
L1
L2
C7
C12
L
RV1
N
C5
R3
Output
VR3
C4
V
Filter
R24
C14
Capacitors
R16
C6
Copper Area for
Heat Sinking
R10
D8
V
BYPASS Pin
Capacitor
PI-5987-060110
Figure 12. RD-193 7 W Layout Example, Top Layer.
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Rev. D 08/11
LNK403-409/413-419
R13
D7
D6
R12
D1
D5
R17
D1
R5
S
D3
C13
R20
R7
S
R4
VR2
BR1
Output
Rectifier
D2
R9
Bridge Rectifier
F1
B3
R6
R18
Active Damper
MOSFET
PI-5988-060110
Figure 13. RD-193 7 W Layout Example, Bottom Layer.
Quick Design Checklist
Maximum Drain Voltage
Verify that the peak VDS does not exceed 725 V under all
operating conditions including start up and fault conditions.
Maximum Drain Current
Measure the peak drain current under all operation conditions
including start up and fault conditions. Look for signs of
transformer saturation (usually occurs at highest operating
ambient temperatures). Verify that the peak current is less that
stated for the Absolute Maximum Rating in the data sheet.
Thermal Check
At maximum output power, both minimum and maximum line
voltage and ambient temperature; verify that temperature
specifications are not exceeded for the LinkSwitch-PH,
transformer, output diodes, output capacitors and drain clamp
components.
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LNK403-409/413-419
Absolute Maximum Ratings(1,4)
Lead Temperature(3) ................................................................260 °C
Storage Temperature …………………................... -65 to 150 °C
Operating Junction Temperature(2).........................-40 to 150 °C
DRAIN Pin Peak Current(5): LNK403, LNK413...................1.37 A
LNK404, LNK414...................2.08 A
LNK405, LNK415 ...................2.72 A
LNK406, LNK416.................. 4.08 A
LNK407, LNK417 .................. 5.44 A
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
2. Normally limited by internal circuitry.
3. 1/16 in. from case for 5 seconds.
4. Absolute Maximum Ratings specified may be applied, one
at a time without causing permanent damage to the
product. Exposure to Absolute Maximum Ratings for
extended periods of time may affect product reliability.
5. Peak DRAIN current is allowed while the DRAIN voltage is
simultaneously less than 400 V. See also Figure 17.
LNK408, LNK418.................. 6.88 A
LNK409, LNK419 ................... 7.73 A
DRAIN Pin Voltage ………………………................ -0.3 to 725 V
BYPASS Pin Voltage ……………………… ................. -0.3 to 9 V
BYPASS Pin Current ………………………..................... 100 mA
VOLTAGE MONITOR Pin Voltage …....................………-0.3 to 9 V
FEEDBACK Pin Voltage …….. .................................. -0.3 to 9 V
REFERENCE Pin Voltage .......................................... -0.3 to 9 V
Thermal Resistance
Thermal Resistance: eSIP Package:
Notes:
(qJA) ....................................................105 °C/W(1)
(qJC) ............................................... ...........2 °C/W(2)
1. Free Standing with no heat sink.
2. Measured at back surface tab.
Conditions
SOURCE = 0 V; TJ = -20 °C to 125 °C
(Unless Otherwise Specified)
Parameter
Symbol
Min
Typ
Max
Units
Control Functions
Average
TJ = 25 °C
62
66
9
70
Switching Frequency
fOSC
fM
kHz
kHz
Peak-Peak Jitter
Frequency Jitter
Modulation Rate
TJ = 25 °C
See Note B
1
LNK403, LNK413
-5.0
-9.6
-4.2
-8.0
-3.4
-6.4
LNK404, LNK414
VBP = 0 V,
TJ = 25 °C
ICH1
LNK405-409,
LNK415-419
-15
-11.9
-8.8
BYPASS Pin
Charge Current
mA
LNK403, LNK413
LNK404, LNK414
-1.6
-4.2
-1.2
-3.5
-0.6
-2.8
VBP = 5 V,
TJ = 25 °C
ICH2
LNK405-409,
LNK415-419
-8.2
-6.4
-4.6
6.1
6.7
Charging Current
Temperature Drift
See Note A
0.5
5.9
%/°C
BYPASS Pin Voltage
VBP
0 °C < TJ < 100 °C
0 °C < TJ < 100 °C
5.7
V
V
BYPASS Pin Voltage
Hysteresis
VBP(H)
0.85
BYPASS Pin
Shunt Voltage
IBP = 2 mA
0 °C < TJ < 100 °C
VBP(SHUNT)
tSOFT
6.0
40
6.4
V
TJ = 25 °C
VBP = 5.9 V
Soft-Start Time
ms
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Rev. D 08/11
LNK403-409/413-419
Conditions
SOURCE = 0 V; TJ = -20 °C to 125 °C
(Unless Otherwise Specified)
Parameter
Symbol
Min
Typ
Max
Units
Control Functions (cont.)
0 °C < TJ < 100 °C
FET Not Switching
ICD2
ICD1
1.0
0.9
1.3
1.5
1.6
Drain Supply Current
mA
0 °C < TJ < 100 °C
FET Switching at fOSC
2.25
VOLTAGE MONITOR Pin
RR = 24.9 kW
TJ = 25 °C
21.0
22.8
22.5
24.5
18.5
15.0
4
24.0
26.2
Line Brown-In
Threshold Current
IUV+
mA
mA
mA
RR = 49.9 kW
RR = 24.9 kW
TJ = 25 °C
Line Brown-Out
Threshold Current
IUV-
RR = 49.9 kW
RR = 24.9 kW
TJ = 25 °C
1
5
Line Brown-In/Out
Hysteresis
IUV(H)
RR = 49.9 kW
9.4
TJ = 25 °C
RR = 24.9 kW
RR = 49.9 kW
Threshold
Hysteresis
107
112
4
117
Line Overvoltage
Threshold
IOV
mA
VOLTAGE MONITOR Pin
Voltage
0 °C < TJ < 100 °C
VV
2.75
170
0.5
3.0
3.25
210
V
mA
V
IUV- < IV < IOV
VOLTAGE MONITOR Pin
Short-Circuit Current
VV = 5 V
TJ = 25 °C
IV(SC)
190
Remote ON/OFF
Threshold
VV(REM)
TJ = 25 °C
FEEDBACK Pin
FEEDBACK Pin Current
at Onset of Maximum
Duty Cycle
IFB(DCMAXR)
0 °C < TJ < 100 °C
0 °C < TJ < 100 °C
85
mA
FEEDBACK Pin Current
Skip Cycle Threshold
IFB(SKIP)
DCMAX
VFB
220
90
mA
%
V
IFB(DCMAXR) < IFB < IFB(SKIP)
0 °C < TJ < 100 °C
Maximum Duty Cycle
FEEDBACK Pin Voltage
99.9
2.62
480
IFB = 150 mA
2.08
2.40
400
0 °C < TJ < 100 °C
FEEDBACK Pin
Short-Circuit Current
VFB = 5 V
TJ = 25 °C
IFB(SC)
320
10
mA
DC10
DC40
DC60
IFB = IFB(AR), TJ = 25 °C, See Note B
IFB = 40 mA, TJ = 25 °C
Duty Cycle Reduction
20
36
%
IFB = 60 mA, TJ = 25 °C
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Conditions
SOURCE = 0 V; TJ = -20 °C to 125 °C
(Unless Otherwise Specified)
Parameter
Auto-Restart
Symbol
Min
Typ
Max
Units
TJ = 25 °C
VBP = 5.9 V
Auto-Restart ON-Time
tAR
40
ms
%
Auto-Restart
Duty Cycle
DCAR
tON(SOA)
TJ = 25 °C
3.1
SOA Minimum Switch
ON-Time
TJ = 25 °C
See Note B
1.75
17.5
ms
FEEDBACK Pin
Current During
Auto-Restart
IFB(AR)
0 °C < TJ < 100 °C
mA
REFERENCE Pin
REFERENCE Pin
Voltage
VR
IR
1.215
48.45
1.245
49.70
1.275
50.95
V
RR = 24.9 kW
0 °C < TJ < 100 °C
REFERENCE Pin
Current
mA
Current Limit/Circuit Protection
di/dt = 174 mA/ms
di/dt = 174 mA/ms
di/dt = 225 mA/ms
di/dt = 320 mA/ms
di/dt = 350 mA/ms
di/dt = 426 mA/ms
di/dt = 133 mA/ms
di/dt = 195 mA/ms
di/dt = 192 mA/ms
di/dt = 240 mA/ms
di/dt = 335 mA/ms
di/dt = 380 mA/ms
di/dt = 466 mA/ms
LNK404, LNK414
LNK405, LNK415
LNK406, LNK416
LNK407, LNK417
LNK408, LNK418
LNK409, LNK419
LNK403, LNK413
LNK404, LNK414
LNK405, LNK415
LNK406, LNK416
LNK407, LNK417
LNK408, LNK418
LNK409, LNK419
1.02
1.24
1.50
1.77
2.39
3.26
0.75
0.81
1.00
1.19
1.18
1.44
1.74
2.06
2.77
3.79
0.85
0.94
1.16
1.38
1.66
2.01
2.73
Full Power
Current Limit
(CBP = 100 mF)
ILIMIT(F)
A
TJ = 25 °C
Reduced Power
Current Limit
(CBP = 10 mF)
ILIMIT(R)
A
TJ = 25 °C
1.42
1.73
2.35
Minimum ON-Time
Pulse
tLEB + tIL(D)
tLEB
TJ = 25 °C
300
150
500
700
500
ns
ns
ns
°C
°C
Leading Edge
Blanking Time
TJ = 25 °C
See Note B
TJ = 25 °C
See Note B
Current Limit Delay
tIL(D)
150
142
75
Thermal Shutdown
Temperature
135
150
Thermal Shutdown
Hysteresis
BYPASS Pin Power-Up
Reset Threshold
Voltage
VBP(RESET)
0 °C < TJ < 100 °C
2.25
3.5
4.25
V
15
www.powerint.com
Rev. D 08/11
LNK403-409/413-419
Conditions
SOURCE = 0 V; TJ = -20 °C to 125 °C
(Unless Otherwise Specified)
Parameter
Symbol
Min
Typ
Max
Units
Output
TJ = 25 °C
9.00
13.50
5.40
8.35
4.10
6.30
2.80
4.10
2.00
3.10
1.60
2.40
1.40
2.1
10.35
15.5
6.25
9.7
LNK403, LNK413
ID = 100 mA
TJ = 100 °C
TJ = 25 °C
LNK404, LNK414
ID = 100 mA
TJ = 100 °C
TJ = 25 °C
4.7
LNK405, LNK415
ID = 150 mA
TJ = 100 °C
7.3
TJ = 25 °C
3.2
LNK406, LNK416
ON-State Resistance
RDS(ON)
W
ID = 150 mA
TJ = 100 °C
4.75
2.3
TJ = 25 °C
LNK407, LNK417
ID = 200 mA
TJ = 100 °C
3.6
TJ = 25 °C
1.85
2.8
LNK408, LNK418
ID = 250 mA
TJ = 100 °C
TJ = 25 °C
1.6
LNK409, LNK419
ID = 350 mA
TJ = 100 °C
2.45
VBP = 6.4 V
VDS = 560 V
TJ = 100 °C
OFF-State Drain
Leakage Current
IDSS
50
mA
VBP = 6.4 V
TJ = 25 °C
Breakdown Voltage
BVDSS
725
36
V
V
Minimum Drain
Supply Voltage
TJ < 100 °C
Rise Time
Fall Time
tR
tF
100
50
ns
ns
Measured in a Typical Flyback
NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with increas-
ing temperature and a positive temperature coefficient corresponds to a decrease in magnitude with increasing temperature.
B. Guaranteed by characterization. Not tested in production.
16
Rev. D 08/11
www.powerint.com
LNK403-409/413-419
Typical Performance Characteristics
10000
300
200
100
Scaling Factors:
Scaling Factors:
LNK403, LNK413 0.18
LNK404, LNK414 0.28
LNK405, LNK415 0.38
LNK406, LNK416 0.56
LNK407, LNK417 0.75
LNK408, LNK418 1.00
LNK409, LNK419 1.16
LNK403, LNK413 0.18
LNK404, LNK414 0.28
LNK405, LNK415 0.38
LNK406, LNK416 0.56
LNK407, LNK417 0.75
LNK408, LNK418 1.00
LNK409, LNK419 1.16
1000
100
0
0
0
100 200 300 400 500 600
0
100 200 300 400 500 600 700
DRAIN Pin Voltage (V)
DRAIN Voltage (V)
Figure 14. Drain Capacitance vs. Drain Pin Voltage.
Figure 15. Power vs. Drain Voltage.
5
4
1.2
1
0.8
0.6
0.4
0.2
3
Scaling Factors:
LNK403, LNK413 0.18
LNK404, LNK414 0.28
LNK405, LNK415 0.38
LNK406, LNK416 0.56
LNK407, LNK417 0.75
LNK408, LNK418 1.00
LNK409, LNK419 1.16
2
1
LNK408 TCASE = 25 °C
LNK408 TCASE = 100 °C
0
0
0
2
4
6
8
10 12 14 16 18 20
0
100 200 300 400 500 600 700 800
DRAIN Voltage (V)
DRAIN Voltage (V)
Figure 16. Drain Current vs. Drain Voltage.
Figure 17. Maximum Allowable Drain Current vs. Drain Voltage.
17
www.powerint.com
Rev. D 08/11
LNK403-409/413-419
eSIP-7C (E Package)
C
2
0.403 (10.24)
0.397 (10.08)
0.264 (6.70)
Ref.
0.081 (2.06)
0.077 (1.96)
A
B
Detail A
2
0.290 (7.37)
Ref.
0.325 (8.25)
0.320 (8.13)
0.198 (5.04) Ref.
0.519 (13.18)
Ref.
0.207 (5.26)
0.187 (4.75)
Pin #1
I.D.
0.016 (0.41)
Ref.
0.140 (3.56)
0.120 (3.05)
3
4
0.047 (1.19)
0.118 (3.00)
SIDE VIEW
0.070 (1.78) Ref.
0.033 (0.84)
0.028 (0.71)
0.010 M 0.25 M C A B
6×
0.100 (2.54)
0.050 (1.27)
0.016 (0.41)
0.011 (0.28)
3
6×
0.020 M 0.51 M C
FRONT VIEW
BACK VIEW
0.100 (2.54)
10° Ref.
All Around
0.050 (1.27)
0.050 (1.27)
0.020 (0.50)
0.060 (1.52)
Ref.
0.021 (0.53)
0.019 (0.48)
PIN 1
0.048 (1.22)
0.046 (1.17)
0.019 (0.48) Ref.
0.155 (3.93)
0.059 (1.50)
0.378 (9.60)
Ref.
0.023 (0.58)
0.027 (0.70)
PIN 7
END VIEW
0.059 (1.50)
Notes:
DETAIL A
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.100 (2.54)
0.100 (2.54)
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but including
any mismatch between the top and bottom of the plastic
body. Maximum mold protrusion is 0.007 [0.18] per side.
MOUNTING HOLE PATTERN
(not to scale)
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches (mm).
PI-4917-061510
18
Rev. D 08/11
www.powerint.com
LNK403-409/413-419
eSIP-7F (L Package)
C
2
0.403 (10.24)
0.397 (10.08)
0.081 (2.06)
0.077 (1.96)
A
0.264 (6.70) Ref.
0.198 (5.04) Ref.
B
Detail A
0.325 (8.25)
0.320 (8.13)
0.290 (7.37)
2
Ref.
3
0.490 (12.45) Ref.
0.016 (0.41)
0.011 (0.28)
6×
0.020 M 0.51 M C
0.173 (4.40)
0.163 (4.15)
1
7
7
1
0.084 (2.14)
0.047 (1.19) Ref.
Pin 1 I.D.
0.089 (2.26)
0.079 (2.01)
0.070 (1.78) Ref.
3
4
0.100 (2.54)
0.050 (1.27)
0.033 (0.84)
0.028 (0.71)
0.129 (3.28)
0.122 (3.08)
6×
0.010 M 0.25 M C A B
BOTTOM VIEW
Exposed pad hidden
SIDE VIEW
TOP VIEW
Exposed pad up
Notes:
1. Dimensioning and tolerancing per ASME
Y14.5M-1994.
1
7
0.021 (0.53)
0.019 (0.48)
0.020 (0.50)
0.023 (0.58)
0.060 (1.52) Ref.
2. Dimensions noted are determined at the
outermost extremes of the plastic body
exclusive of mold flash, tie bar burrs, gate
burrs, and interlead flash, but including
any mismatch between the top and bottom
of the plastic body. Maximum mold
protrusion is 0.007 [0.18] per side.
3. Dimensions noted are inclusive of plating
thickness.
0.019 (0.48) Ref.
0.378 (9.60)
Ref.
0.048 (1.22)
0.046 (1.17)
0.027 (0.70)
END VIEW
DETAIL A (Not drawn to scale)
4. Does not include inter-lead flash or
protrusions.
5. Controlling dimensions in inches (mm).
PI-5204-061510
Part Ordering Information
• LinkSwitch Product Family
• PH Series Number
• Package Identifier
E
L
eSIP-7C
eSIP-7F
• Package Material
GREEN: Halogen Free and RoHS Compliant
LNK 409
E G
G
19
www.powerint.com
Rev. D 08/11
Revision
Notes
Date
06/09/10
08/06/10
11/10
A
B
C
D
Initial Release.
Updated Power Table.
Added Non-Dimming Parts and Related Text.
Added L Package.
08/11
For the latest updates, visit our website: www.powerint.com
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Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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