TOP223G [POWERINT]
Three-terminal Off-line PWM Switch; 三端离线式PWM开关
| 型号： | TOP223G |
| 厂家： | 
Power Integrations |
| 描述： | Three-terminal Off-line PWM Switch |
| 文件： | 总20页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
TOP221-227
®
TOP S w it c h -II Family
Three-terminal Off-line PWM Switch
Product Highlights
AC
IN
• Lowest cost, lowest component count switcher solution
• Cost competitive with linears above 5W
• Very low AC/DC losses – up to 90% efficiency
• Built-in Auto-restart and Current limiting
• Latching Thermal shutdown for system level protection
• Implements Flyback, Forward, Boost or Buck topology
• Works with primary or opto feedback
• Stable in discontinuous or continuous conduction mode
• Source connected tab for low EMI
D
S
CONTROL
C
TOP S w it c h
• Circuit simplicity and Design Tools reduce time to market
PI-1951-091996
Description
Figure 1. Typical Flyback Application.
The second generation TOPSwitch-II family is more cost
effective and provides several enhancements over the first
generationTOPSwitchfamily. TheTOPSwitch-IIfamilyextends
the power range from 100W to 150W for 100/115/230 VAC
input and from 50W to 90W for 85-265 VAC universal input.
This brings TOPSwitch technology advantages to many new
applications, i.e. TV, Monitor, Audio amplifiers, etc. Many
significant circuit enhancements that reduce the sensitivity to
board layout and line transients now make the design even
easier. The standard 8L PDIP package option reduces cost in
lower power, high efficiency applications. The internal lead
frame of this package uses six of its pins to transfer heat from
the chip directly to the board, eliminating the cost of a heat sink.
TOPSwitch incorporates all functions necessary for a switched
modecontrolsystemintoathreeterminalmonolithicIC:power
MOSFET, PWM controller, high voltage start up circuit, loop
compensation and fault protection circuitry.
OUTPUT POWER TABLE
TO-220 (Y) Package1
8L PDIP (P) or 8L SMD (G) Package2
3
Single Voltage Input3
Wide Range Input
85 to 265 VAC
.
Single Voltage Input
Wide Range Input
85 to 265 VAC
PART
ORDER
NUMBER
PART
ORDER
NUMBER
100/115/230 VAC ±15%
100/115/230 VAC ±15%
4,6
4,6
5,6
5,6
PMAX
PMAX
PMAX
PMAX
TOP221Y
TOP222Y
TOP223Y
TOP224Y
TOP225Y
TOP226Y
TOP227Y
7 W
TOP221P or TOP221G
TOP222P or TOP222G
TOP223P or TOP223G
TOP224P or TOP224G
9 W
6 W
12 W
15 W
25 W
30 W
10 W
15 W
20 W
25 W
15 W
30 W
45 W
60 W
75 W
90 W
50 W
75 W
100 W
125 W
150 W
Notes: 1. Package outline: Y03A 2. Package Outline: P08A or G08A 3. 100/115 VAC with doubler input 4. Assumes appropriate heat
sinking to keep the maximum TOPSwitch junction temperature below 100˚ C. 5. Soldered to 1 sq. in.( 6.45 cm2), 2 oz. copper clad
(610 gm/m2) 6. P
is the maximum practical continuous power output level for conditions shown. The continuous power capability
in a given applicatMioAnX depends on thermal environment, transformer design, efficiency required, minimum specified input voltage, input
storage capacitance, etc. 7. Refer to key application considerations section when using TOPSwitch-II in an existing TOPSwitch design.
December 1997
TOP221-227
V
C
0
1
CONTROL
DRAIN
INTERNAL
SUPPLY
Z
C
SHUTDOWN/
AUTO-RESTART
SHUNT REGULATOR/
ERROR AMPLIFIER
+
-
÷ 8
-
5.7 V
4.7 V
5.7 V
+
+
-
V
I
LIMIT
I
FB
THERMAL
SHUTDOWN
S
R
Q
POWER-UP
RESET
Q
CONTROLLED
TURN-ON
GATE
DRIVER
OSCILLATOR
D
MAX
CLOCK
SAW
S
Q
Q
-
LEADING
EDGE
+
R
BLANKING
PWM
COMPARATOR
MINIMUM
ON-TIME
DELAY
R
E
SOURCE
PI-1935-091696
Figure 2. Functional Block Diagram.
Pin Functional Description
Tab Internally
DRAIN Pin:
Connected to Source Pin
Output MOSFET drain connection. Provides internal bias
current during start-up operation via an internal switched high-
voltage current source. Internal current sense point.
DRAIN
SOURCE
CONTROL Pin:
CONTROL
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. It is also used as the
connection point for the supply bypass and auto-restart/
compensation capacitor.
TO-220 (YO3A)
1
8
7
6
5
SOURCE
SOURCE
SOURCE
CONTROL
SOURCE (HV RTN)
SOURCE (HV RTN)
SOURCE (HV RTN)
DRAIN
2
3
4
SOURCE Pin:
Y package – Output MOSFET source connection for high
voltage power return. Primary side circuit
common and reference point.
P and G package – Primary side control circuit common and
reference point.
DIP-8 (P08A)
SMD-8 (G08A)
PI-2084-052198
SOURCE (HV RTN) Pin: (P and G package only)
Output MOSFET source connection for high voltage power return.
Figure 3. Pin Configuration.
C
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TOP221-227
TOP S w it c h Family Functional Description
TOPSwitch is a self biased and protected linear control current-
to-duty cycle converter with an open drain output. High
efficiencyisachievedthrough theuseofCMOSandintegration
of the maximum number of functions possible. CMOS process
significantly reduces bias currents as compared to bipolar or
discrete solutions. Integration eliminates external power
resistors used for current sensing and/or supplying initial start-
up bias current.
Auto-restart
I
B
D
MAX
Slope = PWM Gain
During normal operation, the duty cycle of the internal output
MOSFET decreases linearly with increasing CONTROL pin
current as shown in Figure 4. To implement all the required
control, bias, and protection functions, the DRAIN and
CONTROL pins each perform several functions as described
D
MIN
I
2.0
6.0
CD1
I
(mA)
C
PI-2040-050197
Figure 4. Relationship of Duty Cycle to CONTROL Pin Current.
below. Refer to Figure 2 for a block diagram and to Figure 6 for
timing and voltage waveforms of the TOPSwitch integrated
circuit.
I
C
Charging C
T
5.7 V
4.7 V
V
C
0
Off
V
IN
0
DRAIN
Switching
(a)
I
CD2
Discharging C
I
I
T
C
CD1
Discharging C
Charging C
T
T
5.7 V
4.7 V
V
C
8 Cycles
95%
0
5%
Off
Off
Off
V
IN
0
DRAIN
Switching
Switching
(b)
C is the total external capacitance
T
connected to the CONTROL pin
PI-1956-092496
Figure 5. Start-up Waveforms for (a) Normal Operation and (b) Auto-restart.
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TOP221-227
TOP S w it c h Family Functional Description (cont.)
Control Voltage Supply
and MOSFET gate drive current.
CONTROL pin voltage VC is the supply or bias voltage for the
controller and driver circuitry. An external bypass capacitor
closely connected between the CONTROL and SOURCE pins
is required to supply the gate drive current. The total amount
of capacitance connected to this pin (CT) also sets the auto-
restart timing as well as control loop compensation. VC is
regulated in either of two modes of operation. Hysteretic
regulation is used for initial start-up and overload operation.
Shunt regulation is used to separate the duty cycle error signal
from the control circuit supply current. During start-up,
CONTROLpin currentissuppliedfromahigh-voltageswitched
current source connected internally between the DRAIN and
CONTROLpins. Thecurrentsourceprovidessufficientcurrent
to supply the control circuitry as well as charge the total
external capacitance (CT).
Oscillator
The internal oscillator linearly charges and discharges the
internal capacitance between two voltage levels to create a
sawtoothwaveformforthepulsewidthmodulator. Theoscillator
setsthepulsewidthmodulator/currentlimitlatchatthebeginning
of each cycle. The nominal frequency of 100 kHz was chosen
to minimize EMI and maximize efficiency in power supply
applications. Trimming of the current reference improves
oscillator frequency accuracy.
Pulse Width Modulator
The pulse width modulator implements a voltage-mode control
loop by driving the output MOSFET with a duty cycle inversely
proportional to the current into the CONTROL pin which
generates a voltage error signal across RE. The error signal
across RE is filtered by an RC network with a typical corner
frequency of 7 kHz to reduce the effect of switching noise. The
filtered error signal is compared with the internal oscillator
sawtooth waveform to generate the duty cycle waveform. As
the control current increases, the duty cycle decreases. A clock
signal from the oscillator sets a latch which turns on the output
MOSFET. The pulse width modulator resets the latch, turning
off the output MOSFET. The maximum duty cycle is set by the
symmetry of the internal oscillator. The modulator has a
minimum ON-time to keep the current consumption of the
TOPSwitchindependentoftheerrorsignal. Notethataminimum
current must be driven into the CONTROL pin before the duty
cycle begins to change.
The first time VC reaches the upper threshold, the high-voltage
current source is turned off and the PWM modulator and output
transistorareactivated,asshowninFigure5(a). Duringnormal
operation (when the output voltage is regulated) feedback
control current supplies the VC supply current. The shunt
regulator keeps VC at typically 5.7 V by shunting CONTROL
pin feedback current exceeding the required DC supply current
through the PWM error signal sense resistor RE. The low
dynamic impedance of this pin (ZC) sets the gain of the error
amplifier when used in a primary feedback configuration. The
dynamic impedance of the CONTROL pin together with the
externalresistanceandcapacitancedeterminesthecontrolloop
compensation of the power system.
IftheCONTROLpinexternalcapacitance(CT)shoulddischarge
to the lower threshold, then the output MOSFET is turned off
and the control circuit is placed in a low-current standby mode.
The high-voltage current source turns on and charges the
external capacitance again. Charging current is shown with a
negative polarity and discharging current is shown with a
positive polarity in Figure 6. The hysteretic auto-restart
comparator keeps VC within a window of typically 4.7 to 5.7 V
by turning the high-voltage current source on and off as shown
in Figure 5(b). The auto-restart circuit has a divide-by-8
counter which prevents the output MOSFET from turning on
again until eight discharge-charge cycles have elapsed. The
counter effectively limits TOPSwitch power dissipation by
reducing the auto-restart duty cycle to typically 5%. Auto-
restart continues to cycle until output voltage regulation is
again achieved.
Gate Driver
The gate driver is designed to turn the output MOSFET on at a
controlledratetominimizecommon-modeEMI. Thegatedrive
current is trimmed for improved accuracy.
Error Amplifier
The shunt regulator can also perform the function of an error
amplifierinprimaryfeedbackapplications. Theshuntregulator
voltageisaccuratelyderivedfromthetemperaturecompensated
bandgap reference. The gain of the error amplifier is set by the
CONTROL pin dynamic impedance. The CONTROL pin
clamps external circuit signals to the VC voltage level. The
CONTROL pin current in excess of the supply current is
separated by the shunt regulator and flows through RE as a
voltage error signal.
Cycle-By-Cycle Current Limit
Bandgap Reference
The cycle by cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limitcomparatorcomparestheoutputMOSFETON-statedrain-
source voltage, VDS(ON) with a threshold voltage. High drain
current causes VDS(ON) to exceed the threshold voltage and turns
All critical TOPSwitch internal voltages are derived from a
temperature-compensated bandgap reference. This reference
is also used to generate a temperature-compensated current
sourcewhichistrimmedtoaccuratelysettheoscillatorfrequency
C
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TOP221-227
V
IN
V
IN
0
DRAIN
V
OUT
0
0
I
OUT
1
1
2
2
8
8
1
1
2
2
8
8
1
1
• • •
• • •
• • •
• • •
V
V
C
C(reset)
0
0
I
C
1
3
1
1
2
PI-2030-042397
Figure 6. Typical Waveforms for (1) Normal Operation, (2) Auto-restart, and (3) Power Down Reset.
the output MOSFET off until the start of the next clock cycle.
The current limit comparator threshold voltage is temperature
compensatedtominimizevariationoftheeffectivepeakcurrent
limit due to temperature related changes in output MOSFET
When the fault condition is removed, the power supply output
becomes regulated, VC regulation returns to shunt mode, and
normal operation of the power supply resumes.
RDS(ON)
.
Overtemperature Protection
Temperature protection is provided by a precision analog
circuit that turns the output MOSFET off when the junction
temperature exceeds the thermal shutdown temperature
(typically 135 °C). Activating the power-up reset circuit by
removingandrestoringinputpowerormomentarilypullingthe
CONTROL pin below the power-up reset threshold resets the
latch and allows TOPSwitch to resume normal power supply
operation. VC is regulated in hysteretic mode and a 4.7 V to
5.7V(typical)sawtoothwaveformispresentontheCONTROL
pin when the power supply is latched off.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that current
spikescausedbyprimary-sidecapacitancesandsecondary-side
rectifier reverse recovery time will not cause premature
termination of the switching pulse.
Thecurrentlimitcanbelowerforashortperiodaftertheleading
edge blanking time as shown in Figure 12. This is due to
dynamic characteristics of the MOSFET. To avoid triggering
thecurrentlimitinnormaloperation,thedraincurrentwaveform
should stay within the envelope shown.
High-voltage Bias Current Source
ThiscurrentsourcebiasesTOPSwitchfromtheDRAINpinand
charges the CONTROL pin external capacitance (CT) during
start-up or hysteretic operation. Hysteretic operation occurs
during auto-restart and overtemperature latched shutdown.
The current source is switched on and off with an effective duty
cycle of approximately 35%. This duty cycle is determined by
the ratio of CONTROL pin charge (IC) and discharge currents
(ICD1 and ICD2). This current source is turned off during normal
operation when the output MOSFET is switching.
Shutdown/Auto-restart
To minimize TOPSwitch power dissipation, the shutdown/
auto-restart circuit turns the power supply on and off at an auto-
restart duty cycle of typically 5% if an out of regulation
condition persists. Loss of regulation interrupts the external
current into the CONTROL pin. VC regulation changes from
shuntmodetothehystereticauto-restartmodedescribedabove.
C
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TOP221-227
L1
3.3µH
D2
UF5401
+5V
C2
C3
+
330 µF
100 µF
R3
47K
C1
2.2 nF
1KV
VR1
10V
10V
RTN
D1
UF4005
R2
100 Ω
D3
IN4148
R1
10 Ω
Wide-Range
DC Input
T1
+
U1
C4
100 µF
16V
D
TOP221P
TOP S w it c h -II
CONTROL
C
U2
PC817A
12V Non-Isolated
C5
47 µF
10V
S
-
-
PI-2115-111797
Figure 7. Schematic Diagram of a 4W TOPSwitch-II Stand-by Power Supply using an 8 lead PDIP.
Application Examples
Following are just two of the many possible TOPSwitch
implementations. RefertotheDataBookandDesignGuidefor
additional examples.
vary from 100V to 380V DC which corresponds to the full
universal AC input range. The TOP221 is packaged in a 8 pin
power dip package.
4W Stand-by Supply using 8 Lead PDIP
The output voltage (5V) is directly sensed by the zener diode
(VR1)andtheoptocoupler(U2). Theoutputvoltageisdetermined
by the sum of the zener voltage and the voltage drop across the
LEDoftheoptocoupler(thevoltagedropacrossR1isnegligible).
The output transistor of the optocoupler drives the CONTROL
pinoftheTOP221. C5bypassestheCONTROLpinandprovides
control loop compensation and sets the auto-restart frequency.
Figure 7 shows a 4W stand-by supply. This supply is used in
appliances where certain stand-by functions (e.g. real time
clock, remote control port) must be kept active even while the
main power supply is turned off.
The 5V secondary is used to supply the stand-by function and
the 12V non-isolated output is used to supply power for the
PWM controller of the main power supply and other primary
side functions.
Thetransformer’sleakageinductancevoltagespikesaresnubbed
by R3 and C1 through diode D1. The bias winding is rectified
and filtered by D3 and C4 providing a non-isolated 12V output
which is also used to bias the collector of the optocoupler’s
output transistor. The isolated 5V output winding is rectified by
D2 and filtered by C2, L1 and C3.
For this application the input rectifiers and input filter are sized
for the main supply and are not shown. The input DC rail may
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TOP221-227
L1
D2
3.3 µH
MUR420
+12V
C2
C3
VR1
330 µF
35 V
220 µF
35 V
P6KE200
RTN
D1
BYV26C
BR1
400 V
L2
22 mH
D3
1N4148
R1
100 Ω
C1
47 µF
400 V
C4
0.1 µF
U1
TOP224P
C6
R2
D
S
0.1 µF
220 Ω
T1
TOP S w it c h -II
CONTROL
250 VAC
C
U2
PC817A
R3
6.8 Ω
F1
3.15 A
VR2
1N5241B
11 V
C7
1 nF
250 VAC
Y1
J1
C5
47 µF
L
N
PI-2019-033197
Figure 8. Schematic Diagram of a 20W Universal Input TOPSwitch-II Power Supply using an 8 lead PDIP.
20W Universal Supply using 8 Lead PDIP
Figure8showsa12V, 20Wsecondaryregulatedflybackpower
supply using the TOP224P in an eight lead PDIP package and
operating from universal 85 to 265 VAC input voltage. This
example demonstrates the advantage of the higher power 8 pin
leadframe used with the TOPSwitch-II family. This low cost
package transfers heat directly to the board through six source
pins,eliminatingtheheatsinkandtheassociatedcost. Efficiency
is typically 80% at low line input. Output voltage is directly
sensed by optocoupler U2 and Zener diode VR2. The output
voltage is determined by the Zener diode (VR2) voltage and the
voltagedropsacrosstheoptocoupler(U2)LEDandresistorR1.
Other output voltages are possible by adjusting the transformer
turns ratio and value of Zener diode VR2.
leading-edge voltage spikes caused by transformer leakage
inductance. The power secondary winding is rectified and
filtered by D2, C2, L1, and C3 to create the 12V output voltage.
R2 and VR2 provide a slight pre-load on the 12V output to
improve load regulation at light loads. The bias winding is
rectified and filtered by D3 and C4 to create a TOPSwitch bias
voltage. L2 and Y1-safety capacitor C7 attenuate common
mode emission currents caused by high voltage switching
waveforms on the DRAIN side of the primary winding and the
primary to secondary capacitance. Leakage inductance of L2
with C1 and C6 attenuates differential-mode emission currents
caused by the fundamental and harmonics of the trapezoidal or
triangular primary current waveform. C5 filters internal
MOSFET gate drive charge current spikes on the CONTROL
pin, determines the auto-restart frequency, and together with
R1 and R3, compensates the control loop.
AC power is rectified and filtered by BR1 and C1 to create the
high voltage DC bus applied to the primary winding of T1. The
other side of the transformer primary is driven by the integrated
TOPSwitch-II high-voltage MOSFET. D1 and VR1 clamp
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TOP221-227
Key Application Considerations
• Short interruptions of AC power may cause TOPSwitch to
enter the 8-count auto-restart cycle before starting again.
This is because the input energy storage capacitors are not
completelydischargedandtheCONTROLpincapacitance
has not discharged below the internal power-up reset
voltage.
General Guidelines
• Keep the SOURCE pin length very short. Use a Kelvin
connection to the SOURCE pin for the CONTROL pin
bypass capacitor. Use single point grounding techniques at
the SOURCE pin as shown in Figure 9.
• In some cases, minimum loading may be necessary to keep
a lightly loaded or unloaded output voltage within the
desired range due to the minimum ON-time.
• Minimize peak voltage and ringing on the DRAIN voltage
at turn-off. Use a Zener or TVS Zener diode to clamp the
DRAIN voltage below the breakdown voltage rating of
TOPSwitch under all conditions, including start-up and
overload. The maximum recommended clamp Zener
voltage for the TOP2XX series is 200V and the
corresponding maximum reflected output voltage on the
primary is 135V. Please see Step 4: AN-16 in the Data
Book and Design Guide.
ReplacingTOPSwitch with TOPSwitch-II
There is no external latching shutdown function in TOPSwitch-
II. Otherwise, the functionality of the TOPSwitch-II devices is
same as that of the TOPSwitch family. However, before
considering TOPSwitch-II as a 'drop in' replacement in an
existing TOPSwitch design, the design should be verified as
described below.
• The transformer should be designed such that the rate of
change of drain current due to transformer saturation is
within the absolute maximum specification (∆ID in 100ns
before turn off as shown in Figure 13). As a guideline, for
most common transformer cores, this can be achieved by
maintaining the Peak Flux Density (at maximum Ilimit
current) below 4200 Gauss (420mT). The transformer
spreadsheets Rev. 2.1 (or later) for continuous and Rev.1.0
(or later) for discontinuous conduction mode provide the
necessary information.
The new TOPSwitch-II family offers more power capability
than the original TOPSwitch family for the same MOSFET
RDS(ON). Therefore, the original TOPSwitch design must be
reviewed to make sure that the selected TOPSwitch-II
replacement device and other primary components are not over
stressed under abnormal conditions.
The following verification steps are recommended:
• Do not plug TOPSwitch into a “hot” IC socket during test.
External CONTROL pin capacitance may be charged to
excessive voltage and cause TOPSwitch damage.
• Checkthetransformerdesigntomakesurethatitmeetsthe
∆ID specification as outlined in the General Guidelines
section above.
• While performing TOPSwitch device tests, do not exceed
maximum CONTROL pin voltage of 9 V or maximum
CONTROL pin current of 100 mA.
• Thermal: Higher power capability of the TOPSwitch-II
would in many instances allow use of a smaller MOSFET
device (higher RDS(ON)) for reduced cost. This may affect
TOPSwitchpowerdissipationandpowersupplyefficiency.
Therefore thermal performance of the power supply must
be verified with the selected TOPSwitch-II device.
• Under some conditions, externally provided bias or supply
current driven into the CONTROL pin can hold the
TOPSwitch in one of the 8 auto-restart cycles indefinitely
and prevent starting. To avoid this problem when doing
bench evaluations, it is recommended that the VC power
supply be turned on before the DRAIN voltage is applied.
TOPSwitch can also be reset by shorting the CONTROL
pin to the SOURCE pin momentarily.
• Clamp Voltage: Reflected and Clamp voltages should be
verified not to exceed recommended maximums for the
TOP2XXSeries:135VReflected/200VClamp. Pleasesee
Step 4: AN-16 in the Data Book and Design Guide and
readme.txt file attached to the transformer design
spreadsheets.
• CONTROL pin currents during auto-restart operation are
much lower at low input voltages (< 36 V) which increases
the auto-restart cycle time (see the IC vs. DRAIN Voltage
Characteristic curve).
•AgencyApproval:MigratingtoTOPSwitch-IImayrequire
agency re-approval.
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TOP221-227
TO-220 PACKAGE
Bias/Feedback
Return
High Voltage
Return
Kelvin-connected
auto-restart/bypass capacitor C5
and/or compensation network
Do not bend SOURCE pin.
Keep it short.
S
D
C
Bend DRAIN pin
forward if needed
for creepage.
C5
PC Board
Bias/Feedback
Input
Kelvin-connected
auto-restart/bypass
capacitor C5
and/or compensation
network
High-voltage Return
C5
Bias/Feedback Input
Bias/Feedback Return
TOP VIEW
DIP-8/SMD-8 PACKAGE
Bias/Feedback
Return
SOURCE
SOURCE
High Voltage
Return
C5
CONTROL
DRAIN
Kelvin-connected
Bias/Feedback
Input
auto-restart/bypass capacitor C5
and/or compensation network
TOP VIEW
PI-2021-041798
Figure 9. Recommended TOPSwitch Layout.
Design Tools
Alldatasheets, applicationliteratureandup-to-dateversionsof
theTransformerDesignSpreadsheetscanbedownloadedfrom
our web site at www.powerint.com. A diskette of the
Transformer Design Spreadsheets may also be obtained by
sending in the completed form provided at the end of this data
sheet.
The following tools available from Power Integrations greatly
simplify TOPSwitch based power supply design.
•DataBookandDesignGuideincludesextensiveapplication
information
• Excel Spreadsheets for Transformer Design - Use of this
toolisstronglyrecommendedforallTOPSwitchdesigns.
• Reference design boards – Production viable designs that
are assembled and tested.
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TOP221-227
ABSOLUTE MAXIMUM RATINGS1
Operating Junction Temperature(3) ................ -40 to 150 °C
Lead Temperature(4) ................................................ 260 °C
Thermal Impedance: Y Package (θJA)(5) .................70 °C/W
(θJC)(6) ...................2 °C/W
DRAIN Voltage ............................................ -0.3 to 700 V
DRAIN Current Increase (∆ID) in 100 ns except during
blanking time ......................................... 0.1 x ILIMIT(MAX)
(2)
CONTROL Voltage ..................................... - 0.3 V to 9 V
CONTROL Current ...............................................100 mA
Storage Temperature ..................................... -65 to 125 °C
Notes:
P/G Package:
(θJA) .........45 °C/W(7); 35 °C/W(8)
(θJC)(6)...............................5 °C/W
5. Free standing with no heatsink.
1. All voltages referenced to SOURCE, TA = 25 °C.
2. Related to transformer saturation – see Figure 13.
3. Normally limited by internal circuitry.
4. 1/16" from case for 5 seconds.
6. Measured at tab closest to plastic interface or source pin.
7. Soldered to 0.36 sq. inch (232 mm2), 2 oz. (610 gm/m2) copper clad.
8. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 gm/m2) copper clad.
Conditions
(Unless Otherwise Specified)
See Figure 14
Parameter
Symbol
Min
Typ Max
Units
SOURCE = 0 V; Tj = -40 to 125 °C
CONTROL FUNCTIONS
Output
fOSC
IC = 4 mA, Tj = 25 ˚C
90
64
100
67
110
70
kHz
%
Frequency
Maximum
Duty Cycle
DMAX
IC = ICD1 + 0.4 mA, See Figure 10
Minimum
Duty Cycle
0.7
1.7
2.7
DMIN
%
IC = 10 mA, See Figure 10
IC = 4 mA, Tj = 25 ˚C
See Figure 4
PWM
Gain
%/mA
%/mA/˚C
mA
-21
-16
-0.05
2.0
-11
PWM Gain
Temperature Drift
See Note A
External
Bias Current
See Figure 4
IB
0.8
10
3.3
22
IC = 4 mA, Tj = 25 ˚C
See Figure 11
Dynamic
Impedance
ZC
Ω
15
Dynamic Impedance
Temperature Drift
%/˚C
0.18
SHUTDOWN/AUTO-RESTART
VC = 0 V
Tj = 25 ˚C
-2.4
-2
-1.9
-1.5
-1.2
-0.8
CONTROL Pin
Charging Current
IC
mA
VC = 5 V
Charging Current
Temperature Drift
See Note A
%/˚C
0.4
C
10
12/97
TOP221-227
Conditions
(Unless Otherwise Specified)
See Figure 14
Parameter
Symbol
Min
Typ Max
Units
SOURCE = 0 V; Tj = -40 to 125°C
SHUTDOWN/AUTO-RESTART (cont.)
Auto-restart
VC(AR)
S1 open
S1 open
S1 open
5.7
4.7
1.0
V
V
Threshold Voltage
UV Lockout
Threshold Voltage
4.4
0.6
5.0
Auto-restart
Hysteresis Voltage
V
TOP221-222
TOP223-227
2
2
5
5
9
8
Auto-restart
S1 open
%
Hz
Duty Cycle
Auto-restart
Frequency
1.2
S1 open
CIRCUIT PROTECTION
di/dt = 40 mA/µs,
TOP221Y
TOP221P
TOP222Y
0.23
0.45
0.90
0.25
0.50
1.00
0.28
0.55
1.10
Tj = 25°C
di/dt = 80 mA/µs,
Tj = 25°C
di/dt = 160 mA/µs,
Tj = 25°C
TOP222P
TOP223Y
TOP223P
TOP224Y
TOP224P
TOP225Y
Self-protection
Current Limit
di/dt = 240 mA/µs,
Tj = 25°C
ILIMIT
A
1.35
1.80
1.50
2.00
1.65
2.20
di/dt = 320 mA/µs,
Tj = 25°C
di/dt = 400 mA/µs,
Tj = 25°C
TOP226Y
TOP227Y
2.25
2.70
2.50
3.00
2.75
3.30
di/dt = 480 mA/µs,
Tj = 25°C
0.75 x
ILIMIT(MIN)
≤ 85 VAC
(Rectified Line Input)
Initial Current
Limit
IINIT
See Figure 12
Tj = 25˚C
A
0.6 x
265 VAC
ILIMIT(MIN)
(Rectified Line Input)
IC = 4 mA,
Tj = 25˚C
Leading Edge
Blanking Time
tLEB
ns
180
C
11
12/97
TOP221-227
Conditions
(Unless Otherwise Specified)
See Figure 14
Parameter
Symbol
Min
Typ Max
Units
SOURCE = 0 V; Tj = -40 to 125 °C
CIRCUIT PROTECTION (cont.)
Current Limit
IC = 4 mA
tILD
ns
°C
V
100
135
Delay
Thermal Shutdown
Temperature
125
2.0
IC = 4 mA
S2 open
Power-up Reset
Threshold Voltage
VC(RESET)
3.3
4.3
OUTPUT
TOP221
Tj = 25 °C
31.2
51.4
15.6
25.7
36.0
60.0
18.0
30.0
ID = 25 mA
TOP222
Tj = 100 °C
Tj = 25 °C
Tj = 100 °C
Tj = 25 °C
Tj = 100 °C
Tj = 25 °C
Tj = 100 °C
Tj = 25 °C
Tj = 100 °C
Tj = 25 °C
ID = 50 mA
TOP223
7.8
9.0
ID = 100 mA
TOP224
12.9
15.0
ON-State
RDS(ON)
Ω
5.2
8.6
3.9
6.4
3.1
5.2
2.6
4.3
6.0
10.0
4.5
7.5
3.6
6.0
3.0
5.0
Resistance
ID = 150 mA
TOP225
ID = 200 mA
TOP226
ID = 250 mA
TOP227
Tj = 100 °C
Tj = 25 °C
Tj = 100 °C
ID = 300 mA
See Note B
OFF-State
IDSS
Current
µA
250
VDS = 560 V, TA = 125 °C
See Note B
Breakdown
BVDSS
V
700
ID = 100 µA, TA = 25 °C
Voltage
Rise
Time
tr
ns
ns
100
50
Measured in a Typical Flyback
Converter Application.
Fall
Time
tf
C
12
12/97
TOP221-227
Conditions
(Unless Otherwise Specified)
See Figure 14
Parameter
Symbol
Min
Typ Max
Units
SOURCE = 0 V; Tj = -40 to 125 °C
OUTPUT (cont.)
DRAIN Supply
Voltage
V
V
See Note C
IC = 4 mA
36
Shunt Regulator
Voltage
VC(SHUNT)
5.5
5.7
6.0
Shunt Regulator
Temperature Drift
±50
ppm/˚C
Output
TOP221-224
TOP225-227
0.6
0.7
1.2
1.4
1.6
1.8
ICD1
ICD2
MOSFET Enabled
CONTROL Supply/
Discharge Current
mA
Output MOSFET Disabled
0.5
0.8
1.1
NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in
magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in
magnitude with increasing temperature.
B. The breakdown voltage and leakage current measurements can be accomplished as shown in Figure 15 by using
the following sequence:
i. The curve tracer should initially be set at 0 V. The base output should be adjusted through a voltage sequence
of 0 V, 6.5 V, 4.3 V, and 6.5 V, as shown. The base current from the curve tracer should not exceed 100 mA. This
CONTROL pin sequence interrupts the Auto-restart sequence and locks the TOPSwitch internal MOSFET in the
OFF State.
ii. The breakdown and the leakage measurements can now be taken with the curve tracer. The maximum
voltage from the curve tracer must be limited to 700 V under all conditions.
C. It is possible to start up and operate TOPSwitch at DRAIN voltages well below 36 V. However, the CONTROL pin
charging current is reduced, which affects start-up time, auto-restart frequency, and auto-restart duty cycle. Refer
to the characteristic graph on CONTROL pin charge current (IC) vs. DRAIN voltage for low voltage operation
characteristics.
C
13
12/97
TOP221-227
120
100
80
t
2
t
60
1
HV
90%
90%
40
Dynamic
Impedance
1
=
t
t
DRAIN
VOLTAGE
1
2
Slope
D =
20
10%
0
0 V
0
2
4
6
8
10
CONTROL Pin Voltage (V)
PI-2039-043097
Figure 10. TOPSwitch Duty Cycle Measurement.
Figure 11. TOPSwitch CONTROL Pin I-V Characteristic.
t
(Blanking Time)
LEB
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
100 nS
I
@ 85VAC
tLEB
INIT(MIN)
∆ID
I
@ 265VAC
INIT(MIN)
DRAIN
CURRENT
I
I
@ 25 ˚C
@ 25 ˚C
LIMIT(MAX)
LIMIT(MIN)
0
0 A
0
1
2
3
4
5
6
7
8
Time (us)
PI-2031-042397
Figure 12. Self-protection Current Limit Envelope.
Figure 13. Example of ∆ID on Drain Current Waveform with
Saturated Transformer.
C
14
12/97
TOP221-227
470 Ω
5 W
S2
D
S
CONTROL
470 Ω
C
TOP S w it c h
S1
40 V
0.1 µF
47 µF
0-50 V
NOTES: 1. This test circuit is not applicable for current limit or output characteristic measurements.
2. For P package, short all SOURCE and SOURCE (HV RTN) pins together.
PI-1964-110696
Figure 14. TOPSwitch General Test Circuit.
Curve
Tracer
C
B
E
D
S
CONTROL
C
TOP S w it c h
6.5V
4.3V
NOTE: This CONTROL pin sequence interrupts the Auto-restart sequence and
locks the TOPSwitch internal MOSFET in the OFF State.
PI-2109-092397
Figure 15. Breakdown Voltage and Leakage Current Measurement Test Circuit.
C
15
12/97
TOP221-227
BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS
The following precautions should be followed when testing
TOPSwitch by itself outside of a power supply. The schematic
shown in Figure 14 is suggested for laboratory testing of
TOPSwitch.
Auto-restart mode, there is onlya 12.5% chance that the control
pin oscillation will be in the correct state (DRAIN active state)
so that the continuous DRAIN voltage waveform may be
observed. It is recommended that the VC power supply be
turnedonfirstandtheDRAINpowersupplysecondifcontinuous
drainvoltagewaveformsaretobeobserved. The12.5%chance
ofbeinginthecorrectstateisduetothe8:1counter. Temporarily
shorting the CONTROL pin to the SOURCE pin will reset
TOPSwitch, which then will come up in the correct state.
When the DRAIN supply is turned on, the part will be in the
Auto-restart mode. The CONTROL pin voltage will be
oscillating at a low frequency from 4.7 to 5.7 V and the DRAIN
isturnedoneveryeighthcycleoftheCONTROLpinoscillation.
If the CONTROL pin power supply is turned on while in this
Typical Performance Characteristics
BREAKDOWN vs. TEMPERATURE
FREQUENCY vs. TEMPERATURE
1.1
1.2
1.0
0.8
0.6
0.4
0.2
1.0
0.9
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Junction Temperature (°C)
Junction Temperature (°C)
CURRENT LIMIT vs. TEMPERATURE
I vs. DRAIN VOLTAGE
C
1.2
2
V
= 5 V
C
1.0
0.8
0.6
0.4
0.2
1.6
1.2
0.8
0.4
0
0
-50 -25
0
25 50 75 100 125 150
0
20
40
60
80
100
Junction Temperature (°C)
DRAIN Voltage (V)
C
16
12/97
TOP221-227
Typical Performance Characteristics (cont.)
OUTPUT CHARACTERISTICS
3
C
vs. DRAIN VOLTAGE
OSS
1000
TCASE=25˚C
TCASE=100˚C
Scaling Factors:
TOP227 1.00
TOP226 0.83
TOP225 0.67
TOP224 0.50
TOP223 0.33
TOP222 0.17
TOP221 0.09
2
100
Scaling Factors:
TOP227 1.00
1
TOP226 0.83
TOP225 0.67
TOP224 0.50
TOP223 0.33
TOP222 0.17
TOP221 0.09
0
10
0
2
4
6
8
10
0
200
400
600
DRAIN Voltage (V)
DRAIN Voltage (V)
DRAIN CAPACITANCE POWER
500
Scaling Factors:
TOP227 1.00
TOP226 0.83
TOP225 0.67
TOP224 0.50
TOP223 0.33
400
TOP222 0.17
TOP221 0.09
300
200
100
0
0
200
400
600
DRAIN Voltage (V)
C
17
12/97
TOP221-227
Free TOPSwitch Flyback Transformer Design Spreadsheets
To receive your free copy of the latest version of the spreadsheets on a 3 1/2" IBM compatible floppy (Excel 4.0 format), please visit
our Website at www.powerint.com or fill out this form completely and mail/fax it to us at the address/phone number noted below.
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Country:_________________________________________________________________________________________________
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EndApplication:____________________________________________________________________________________________
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InputVoltage:____________________________________________________________________________________________
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❏ the end product of my company
❏ is incorporated as part of an end product. If so, please specify the end product_____________________________________
To qualify for this free offer, this form must be filled out completely.
Fax or mail this request to:
Free Flyback Transformer Design Spreadsheet Program Offer
Power Integrations, Inc.
477 N. Mathilda Avenue
Sunnyvale, CA 94086
Attn: Customer Service
Fax: 408-523-9365
C
18
12/97
TOP221-227
P08A
Plastic DIP-8
D S .004 (.10)
DIM
inches
mm
8
5
-E-
A
B
C
G
H
0.370-0.385
0.245-0.255
0.125-0.135
0.015-0.040
0.120-0.135
9.40-9.78
6.22-6.48
3.18-3.43
0.38-1.02
3.05-3.43
B
J1 0.060 (NOM) 1.52 (NOM)
J2
K
L
0.014-0.022
0.010-0.012
0.090-0.110
0.030 (MIN)
0.300-0.320
0.300-0.390
0.300 BSC
0.36-0.56
0.25-0.30
2.29-2.79
0.76 (MIN)
7.62-8.13
7.62-9.91
7.62 BSC
M
N
P
1
4
A
-D-
-F-
M
J1
N
Q
Notes:
C
1. Package dimensions conform to JEDEC
specification MS-001-AB for standard dual
in-line (DIP) package .300 inch row spacing
(PLASTIC) 8 leads (issue B, 7/85)..
2. Controlling dimensions are inches.
3. Dimensions shown do not include mold
flash or other protrusions. Mold flash or
protrusions shall not exceed .006 (.15) on
any side.
H
K
G
Q
J2
4. D, E and F are reference datums on the
molded body.
L
P
PI-2076-031197
G08A
Plastic SMD-8
D S .004 (.10)
DIM
inches
mm
8
5
-E-
A
B
C
G
H
0.370-0.385
0.245-0.255
0.125-0.135
0.004-0.012
0.036-0.044
9.40-9.78
6.22-6.48
3.18-3.43
0.10-0.30
0.91-1.12
E S .010 (.25)
P
B
J1 0.060 (NOM) 1.52 (NOM)
J2
J3
J4
K
0.048-0.053
0.032-0.037
0.007-0.011
0.010-0.012
0.100 BSC
0.030 (MIN)
0.372-0.388
0-8˚
1.22-1.35
0.81-0.94
0.18-0.28
0.25-0.30
2.54 BSC
0.76 (MIN)
9.45-9.86
0-8˚
1
4
L
L
A
-D-
M
P
M
J1
α
C
Notes:
K
1. Package dimensions conform to JEDEC
specification MS-001-AB (issue B, 7/85)
except for lead shape and size.
2. Controlling dimensions are inches.
3. Dimensions shown do not include mold
flash or other protrusions. Mold flash or
protrusions shall not exceed .006 (.15) on
any side.
-F-
.004 (.10)
J3
J4
.010 (.25) M A S
α
G
H
J2
4. D, E and F are reference datums on the
molded body.
PI-2077-071597
C
19
12/97
TOP221-227
Y03A
Plastic TO-220/3
mm
DIM
inches
11.68-12.19
10.16-10.54
5.99-6.60
6.10 - REF.
13.21-14.22
.71-.97
A
B
C
D
E
F
.460-.480
.400-.415
.236-.260
.240 - REF.
.520-.560
.028-.038
.045-.055
.090-.110
.165-.185
.045-.055
.095-.115
.015-.020
.705-.715
.146-.156
.103-.113
J
B
K
P
Notes:
C
1. Package dimensions conform to
JEDEC specification TO-220 AB for
standard flange mounted, peripheral
lead package; .100 inch lead spacing
(Plastic) 3 leads (issue J, March 1987)
2. Controlling dimensions are inches.
3. Pin numbers start with Pin 1, and
continue from left to right when
viewed from the top.
4. Dimensions shown do not include
mold flash or other protrusions. Mold
flash or protrusions shall not exceed
.006 (.15 mm) on any side.
O
1.14-1.40
2.29-2.79
4.19-4.70
1.14-1.40
2.41-2.92
.38-.51
G
H
J
A
N
K
L
L
M
N
O
P
D
5. Position of terminals to be
measured at a position .25 (6.35 mm)
from the body.
17.91-18.16
3.71-3.96
2.62-2.87
E
6. All terminals are solder plated.
F
M
G
H
PI-1848-050696
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it
convey any license under its patent rights or the rights of others.
PI Logo and TOP S w it c h are registered trademarks of Power Integrations, Inc.
©Copyright 1998, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086 http://www.powerint.com
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Power Integrations, Inc.
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Holdings, Inc.
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C
20
12/97
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