TOP265VG [POWERINT]
Integrated Off-Line Switcher with EcoSmart Technology for Highly Efficient Power Supplies; 集成离线式开关与EcoSmart技术的高效率电源
| 型号： | TOP265VG |
| 厂家： | 
Power Integrations |
| 描述： | Integrated Off-Line Switcher with EcoSmart Technology for Highly Efficient Power Supplies |
| 文件： | 总36页 (文件大小：2991K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TOP264-271
®
TOPSwitch-JX Family
®
Integrated Off-Line Switcher with EcoSmart Technology
for Highly Efficient Power Supplies
Product Highlights
+
EcoSmart® - Energy Efficient
• Energy efficient over entire load range
• No-load consumption below 100 mW at 265 VAC
AC
IN
DC
OUT
-
• Up to 750 mW standby output power for 1 W input at 230 VAC
D
S
V
High Design Flexibility for Low System Cost
• Multi-mode PWM control maximizes efficiency at all loads
• 132 kHz operation reduces transformer and power supply size
• 66 kHz option for highest efficiency requirements
• Accurate programmable current limit
CONTROL
C
TOPSwitch-JX
X
F
• Optimized line feed-forward for line ripple rejection
• Frequency jittering reduces EMI filter cost
• Fully integrated soft-start for minimum startup stress
• 725 V rated MOSFET
PI-5578-090309
Figure 1. Typical Flyback Application.
• Simplifies meeting design derating requirements
Extensive Protection Features
• Auto-restart limits power delivery to <3% during overload faults
• Output short-circuit protection (SCP)
• Output over-current protection (OCP)
• Heat transfer to both PCB and heat sink
• Optional external heat sink provides thermal impedance
equivalent to a TO-220
• eSIP®-7C package:
• Output overload protection (OPP)
• Vertical orientation for minimum PCB footprint
• Simple heat sink mounting using clip provides thermal
impedance equivalent to a TO-220
• Extended creepage to DRAIN pin
• Heat sink is connected to SOURCE for low EMI
• Output overvoltage protection (OVP)
• User programmable for hysteretic/latching shutdown
• Simple fast AC reset
• Primary or secondary sensed
• Line undervoltage (UV) detection prevents turn-off glitches
• Line overvoltage (OV) shutdown extends line surge withstand
• Accurate thermal shutdown with large hysteresis (OTP)
Description
TOPSwitch-JX cost effectively incorporates a 725 V power
MOSFET, high voltage switched current source, multi-mode
PWM control, oscillator, thermal shutdown circuit, fault
protection and other control circuitry onto a monolithic device.
Advanced Package Options
• eDIP™-12 package:
• Low profile horizontal orientation for ultra-slim designs
Output Power Table
PCB Copper Area1
Metal Heat Sink1
230 VAC 15%4
85-265 VAC
230 VAC 15% 4
Adapter2
85-265 VAC
Product5
Product5
Open
Open
Open
Open
Adapter2
Adapter2
Adapter2
Frame3
Frame3
Frame3
Frame3
TOP264VG
21 W
22.5 W
24 W
27.5 W
30 W
32 W
34 W
36 W
34 W
12 W
15 W
17 W
22.5 W
TOP264EG/VG
TOP265EG/VG
TOP266EG/VG
TOP267EG/VG
TOP268EG/VG
TOP269EG/VG
TOP270EG/VG
TOP271EG/VG
30 W
40 W
60 W
62 W
20 W
26 W
40 W
55 W
70 W
80 W
93 W
118 W
43 W
57 W
86 W
103 W
112 W
120 W
140 W
177 W
TOP265VG
TOP266VG
TOP267VG
TOP268VG
TOP269VG
TOP270VG
TOP271VG
36 W
39 W
44 W
48 W
51 W
55 W
59 W
25 W
28.5 W
32 W
36 W
37.5 W
41 W
81 W
119 W
137 W
148 W
162 W
190 W
244 W
19 W
85 W
21.5 W
22.5 W
24.5 W
26 W
105 W
128 W
147 W
177 W
43 W
Table 1. Output Power Table.
Notes:
1. See Key Application Considerations section for more details.
2. Minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 °C ambient temperature.
3. Minimum continuous power in an open frame design at +50 °C ambient temperature.
4. 230 VAC or 110/115 VAC with doubler.
5. Packages: E: eSIP-7C, V: eDIP-12. See Part Ordering Information section.
www.powerint.com
March 2010
TOP264-271
Section List
Functional Block Diagram ....................................................................................................................................... 3
Pin Functional Description ...................................................................................................................................... 3
TOP264-271 Functional Description ........................................................................................................................ 4
CONTROL (C) Pin Operation.................................................................................................................................... 5
Oscillator and Switching Frequency.......................................................................................................................... 5
Pulse Width Modulator ............................................................................................................................................ 5
Maximum Duty Cycle ............................................................................................................................................... 6
Error Amplifier .......................................................................................................................................................... 6
On-Chip Current Limit with External Programmability ............................................................................................... 6
Line Undervoltage Detection (UV)............................................................................................................................. 6
Line Overvoltage Shutdown (OV).............................................................................................................................. 7
Hysteretic or Latching Output Overvoltage Protection (OVP)..................................................................................... 7
Line Feed-Forward with DCMAX Reduction ................................................................................................................ 8
Remote ON/OFF ..................................................................................................................................................... 8
Soft-Start................................................................................................................................................................. 9
Shutdown/Auto-Restart (for OCP, SCP, OPP)......................................................................................................... 10
Hysteretic Over-Temperature Protection (OTP) ....................................................................................................... 10
Bandgap Reference ............................................................................................................................................... 10
High-Voltage Bias Current Source.......................................................................................................................... 10
Typical Uses of FREQUENCY (F) Pin ...................................................................................................................... 12
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins .......................................... 13
Application Examples .............................................................................................................................................. 15
Low No-load, High Efficiency, 65 W, Universal Input Adapter Power Supply ..................................................................... 15
Very low No-load, High Efficiency, 30 W, Universal Input, Open Frame, Power Supply..............................................................17
Key Application Considerations .............................................................................................................................. 18
TOPSwitch-JX vs.TOPSwitch-HX........................................................................................................................ . 18
TOP264-271 Design Considerations ..................................................................................................................... 18
TOP264-271 Layout Considerations ...................................................................................................................... 20
Quick Design Checklist .......................................................................................................................................... 21
Design Tools .......................................................................................................................................................... 21
Product Specifications and Test Conditions .......................................................................................................... 23
Typical Performance Characteristics .................................................................................................................... 30
Package Outlines .................................................................................................................................................... 34
Part Ordering Information ........................................................................................................................................ 35
2
Rev. B 03/10
www.powerint.com
TOP264-271
DRAIN (D)
0
1
VC
CONTROL (C)
INTERNAL
SUPPLY
ZC
-
SHUNT REGULATOR/
ERROR AMPLIFIER
+
-
+
SOFT START
5.8 V
4.8 V
-
KPS(UPPER)
INTERNAL UV
COMPARATOR
5.8 V
+
-
IFB
+
V
I (LIMIT)
CURRENT
LIMIT
ADJUST
KPS(LOWER)
-
÷ 16
ON/OFF
+
SHUTDOWN/
AUTO-RESTART
EXTERNAL CURRENT
LIMIT (X)
CURRENT LIMIT
COMPARATOR
VBG + VT
VOLTAGE
MONITOR (V)
STOP LOGIC
HYSTERETIC
THERMAL
SHUTDOWN
SOURCE (S)
1 V
CONTROLLED
TURN-ON
GATE DRIVER
V
OVP OV/
UV
STOP SOFT
LINE
SENSE
DCMAX
START
DCMAX
DMAX
OSCILLATOR
WITH JITTER
CLOCK
S
R
Q
FREQUENCY (F)
66k/132k
F REDUCTION
LEADING
EDGE
BLANKING
F REDUCTION
SOFT START
IFB
IPS(UPPER)
IPS(LOWER)
OFF
PWM
KPS(UPPER)
KPS(LOWER)
PI-4511-012810
SOURCE (S)
Figure 2. Functional Block Diagram (E and V Package).
Pin Functional Description
DRAIN (D) Pin:
SOURCE (S) Pin:
Output MOSFET source connection for high voltage power return.
Primary side control circuit common and reference point.
High-voltage power MOSFET DRAIN pin. The internal start-up
bias current is drawn from this pin through a switched high-
voltage current source. Internal current limit sense point for
drain current.
NO CONNECTION (NC) Pin:
Internally not connected, floating potential pin.
CONTROL (C) Pin:
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. It is also used as the
connection point for the supply bypass and auto-restart/
compensation capacitor.
E Package (eSIP-7C)
V Package (eDIP-12)
S 12
1 V
Exposed Pad
(Hidden)
Internally
Connected to
SOURCE Pin
EXTERNAL CURRENT LIMIT (X) Pin:
S 11
S 10
S 9
2 X
Input pin for external current limit adjustment remote
ON/OFF and device reset. A connection to SOURCE pin
disables all functions on this pin.
3 C
4 F
S 8
5 NC
S 7
6 D
VOLTAGE MONITOR (V) Pin:
Input for OV, UV, line feed forward with DCMAX reduction, output
overvoltage protection (OVP), remote ON/OFF. A connection to
the SOURCE pin disables all functions on this pin.
1 2 3 4 5
V X C F S
7
D
FREQUENCY (F) Pin:
Input pin for selecting switching frequency 132 kHz if connected
to SOURCE pin and 66 kHz if connected to CONTROL pin.
PI-5568-083109
Figure 3. Pin Configuration (Top View).
3
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Rev. B 03/10
TOP264-271
VUV = IUV × RLS + VV (IV = IUV
)
)
Auto-Restart
+
V
OV = IOV × RLS + VV (IV = IOV
78
For RLS = 4 MΩ
Slope = PWM Gain
4 MΩ
RLS
VUV = 102.8 VDC
VOV = 451 VDC
DCMAX@100 VDC = 76%
DCMAX@375 VDC = 41%
DC
Input
Voltage
D
S
V
CONTROL
C
For RIL = 12 kΩ
ILIMIT = 61%
X
CONTROL
Current
See Figure 35 for
other resistor values
(RIL) to select different
ILIMIT values.
RIL
12 kΩ
-
100
55
Figure 4. Package Line Sense and Externally Set Current Limit.
TOP264-271 Functional Description
Like TOPSwitch-HX, TOP264-271 is an integrated switched
mode power supply chip that converts a current at the control
input to a duty cycle at the open drain output of a high voltage
25
power MOSFET. During normal operation the duty cycle of the
power MOSFET decreases linearly with increasing CONTROL
pin current as shown in Figure 5.
CONTROL
Current
Full Frequency Mode
In addition to the three terminal TOPSwitch features, such as
the high voltage start-up, the cycle-by-cycle current limiting,
loop compensation circuitry, auto-restart and thermal shut-
down, the TOP264-271 incorporates many additional functions
that reduce system cost, increase power supply performance
and design flexibility. A patented high voltage CMOS technology
allows both the high-voltage power MOSFET and all the low
voltage control circuitry to be cost effectively integrated onto a
single monolithic chip.
132
66
Low
Frequency
Mode
Variable
Frequency
Mode
Multi-Cycle
Modulation
Jitter
30
CONTROL
IC03 ICOFF
ICD1 IB
IC01
IC02
Current
Three terminals, FREQUENCY, VOLTAGE-MONITOR, and
EXTERNAL CURRENT LIMIT have been used to implement
some of the new functions. These terminals can be connected
to the SOURCE pin to operate the TOP264-271 in a TOPSwitch-
like three terminal mode. However, even in this three terminal
mode, the TOP264-271 offers many transparent features that do
not require any external components:
PI-5665-110609
Figure 5. Control Pin Characteristics (Multi-Mode Operation).
6. Hysteretic over-temperature shutdown ensures thermal fault
protection.
7. Packages with omitted pins and lead forming provide large
drain creepage distance.
1. A fully integrated 17 ms soft-start significantly reduces or
eliminates output overshoot in most applications by sweeping
both current limit and frequency from low to high to limit the
peak currents and voltages during start-up.
2. A maximum duty cycle (DCMAX) of 78% allows smaller input
storage capacitor, lower input voltage requirement and/or
higher power capability.
3. Multi-mode operation optimizes and improves the power
supply efficiency over the entire load range while maintaining
good cross regulation in multi-output supplies.
4. Switching frequency of 132 kHz reduces the transformer size
with no noticeable impact on EMI.
8. Reduction of the auto-restart duty cycle and frequency to
improve the protection of the power supply and load during
open loop fault, short circuit, or loss of regulation.
9. Tighter tolerances on I2f power coefficient, current limit
reduction, PWM gain and thermal shutdown threshold.
The VOLTAGE-MONITOR (V) pin is usually used for line sensing
by connecting a 4 MW resistor from this pin to the rectified DC
high voltage bus to implement line overvoltage (OV), under-
voltage (UV) and dual-slope line feed-forward with DCMAX
reduction. In this mode, the value of the resistor determines the
OV/UV thresholds and the DCMAX is reduced linearly with a dual
slope to improve line ripple rejection. In addition, it also
provides another threshold to implement the latched and
5. Frequency jittering reduces EMI in the full frequency mode at
high load condition.
4
Rev. B 03/10
www.powerint.com
TOP264-271
hysteretic output overvoltage protection (OVP). The pin can
also be used as a remote ON/OFF using the IUV threshold.
MOSFET off and puts the control circuitry in a low current
standby mode. The high-voltage current source turns on and
charges the external capacitance again. A hysteretic internal
supply undervoltage comparator keeps VC within a window of
typically 4.8 V to 5.8 V by turning the high-voltage current
source on and off as shown in Figure 7. The auto-restart circuit
has a divide-by-sixteen counter, which prevents the output
MOSFET from turning on again until sixteen discharge/charge
cycles have elapsed. This is accomplished by enabling the
output MOSFET only when the divide-by-sixteen counter
reaches the full count (S15). The counter effectively limits
TOP264-271 power dissipation by reducing the auto-restart
duty cycle to typically 2%. Auto-restart mode continues until
output voltage regulation is again achieved through closure of
the feedback loop.
The EXTERNAL CURRENT LIMIT (X) pin can be used to reduce
the current limit externally to a value close to the operating peak
current, by connecting the pin to SOURCE through a resistor.
This pin can also be used as a remote ON/OFF input.
The FREQUENCY (F) pin sets the switching frequency in the full
frequency PWM mode to the default value of 132 kHz when
connected to SOURCE pin. A half frequency option of 66 kHz
can be chosen by connecting this pin to the CONTROL pin
instead. Leaving this pin open is not recommended.
CONTROL (C) Pin Operation
The CONTROL pin is a low impedance node that is capable of
receiving a combined supply and feedback current. During
normal operation, a shunt regulator is used to separate the
feedback signal from the supply current. CONTROL pin voltage
VC is the supply voltage for the control circuitry including the
MOSFET gate driver. An external bypass capacitor closely
connected between the CONTROL and SOURCE pins is
required to supply the instantaneous gate drive current. The
total amount of capacitance connected to this pin also sets the
auto-restart timing as well as control loop compensation.
When rectified DC high voltage is applied to the DRAIN pin
during start-up, the MOSFET is initially off, and the CONTROL
pin capacitor is charged through a switched high voltage
current source connected internally between the DRAIN and
CONTROL pins. When the CONTROL pin voltage VC reaches
approximately 5.8 V, the control circuitry is activated and the
soft-start begins. The soft-start circuit gradually increases the
drain peak current and switching frequency from a low starting
value to the maximum drain peak current at the full frequency
over approximately 17 ms. If no external feedback/supply
current is fed into the CONTROL pin by the end of the soft-start,
the high voltage current source is turned off and the CONTROL
pin will start discharging in response to the supply current
drawn by the control circuitry. If the power supply is designed
properly, and no fault condition such as open loop or shorted
output exists, the feedback loop will close, providing external
CONTROL pin current, before the CONTROL pin voltage has
had a chance to discharge to the lower threshold voltage of
approximately 4.8 V (internal supply undervoltage lockout
threshold). When the externally fed current charges the CONTROL
pin to the shunt regulator voltage of 5.8 V, current in excess of
the consumption of the chip is shunted to SOURCE through an
NMOS current mirror as shown in Figure 2. The output current
of that NMOS current mirror controls the duty cycle of the
power MOSFET to provide closed loop regulation. The shunt
regulator has a finite low output impedance ZC that sets the gain
of the error amplifier when used in a primary feedback
configuration. The dynamic impedance ZC of the CONTROL pin
together with the external CONTROL pin capacitance sets the
dominant pole for the control loop.
Oscillator and Switching Frequency
The internal oscillator linearly charges and discharges an
internal capacitance between two voltage levels to create a
triangular waveform for the timing of the pulse width modulator.
This oscillator sets the pulse width modulator/current limit latch
at the beginning of each cycle.
The nominal full switching frequency of 132 kHz was chosen to
minimize transformer size while keeping the fundamental EMI
frequency below 150 kHz. The FREQUENCY pin, when shorted
to the CONTROL pin, lowers the full switching frequency to
66 kHz (half frequency), which may be preferable in some cases
such as noise sensitive video applications or a high efficiency
standby mode. Otherwise, the FREQUENCY pin should be
connected to the SOURCE pin for the default 132 kHz.
To further reduce the EMI level, the switching frequency in the
full frequency PWM mode is jittered (frequency modulated) by
approximately 2.5 kHz for 66 kHz operation or 5 kHz for
132 kHz operation at a 250 Hz (typical) rate as shown in Figure 6.
The jitter is turned off gradually as the system is entering the
variable frequency mode with a fixed peak drain current.
Pulse Width Modulator
The pulse width modulator implements multi-mode control by
driving the output MOSFET with a duty cycle inversely
proportional to the current into the CONTROL pin that is in
excess of the internal supply current of the chip (see Figure 5).
The feedback error signal, in the form of the excess current, is
filtered by an RC network with a typical corner frequency of
7 kHz to reduce the effect of switching noise in the chip supply
current generated by the MOSFET gate driver.
To optimize power supply efficiency, four different control
modes are implemented. At maximum load, the modulator
operates in full frequency PWM mode; as load decreases, the
modulator automatically transitions, first to variable frequency
PWM mode, then to low frequency PWM mode. At light load,
the control operation switches from PWM control to multi-cycle-
modulation control, and the modulator operates in multi-cycle-
modulation mode. Although different modes operate differently
to make transitions between modes smooth, the simple
relationship between duty cycle and excess CONTROL pin
current shown in Figure 5 is maintained through all three PWM
When a fault condition such as an open loop or shorted output
prevents the flow of an external current into the CONTROL pin,
the capacitor on the CONTROL pin discharges towards 4.8 V.
At 4.8 V, auto-restart is activated, which turns the output
5
www.powerint.com
Rev. B 03/10
TOP264-271
Maximum Duty Cycle
The maximum duty cycle, DCMAX, is set at a default maximum
value of 78% (typical). However, by connecting the VOLTAGE-
MONITOR to the rectified DC high voltage bus through a resistor
with appropriate value (4 MW typical), the maximum duty cycle
can be made to decrease from 78% to 40% (typical) when input
line voltage increases from 88 V to 380 V, with dual gain slopes.
fOSC
+
Switching
Frequency
fOSC
-
4 ms
Error Amplifier
VDRAIN
The shunt regulator can also perform the function of an error
amplifier in primary side feedback applications. The shunt
regulator voltage is accurately derived from a temperature-
compensated bandgap reference. The CONTROL pin dynamic
impedance ZC sets the gain of the error amplifier. The CONTROL
pin clamps external circuit signals to the VC voltage level. The
CONTROL pin current in excess of the supply current is
separated by the shunt regulator and becomes the feedback
current IFB for the pulse width modulator.
Time
Figure 6. Switching Frequency Jitter (Idealized VDRAIN Waveforms).
modes. Please see the following sections for the details of the
operation of each mode and the transitions between modes.
Full Frequency PWM mode: The PWM modulator enters full
frequency PWM mode when the CONTROL pin current (IC)
reaches IB. In this mode, the average switching frequency is
kept constant at fOSC (pin selectable 132 kHz or 66 kHz). Duty
cycle is reduced from DCMAX through the reduction of the on-time
when IC is increased beyond IB. This operation is identical to the
PWM control of all other TOPSwitch families. TOP264-271 only
operates in this mode if the cycle-by-cycle peak drain current
stays above kPS(UPPER) × ILIMIT(set), where kPS(UPPER) is 55% (typical)
and ILIMIT(set) is the current limit externally set via the X pin.
On-Chip Current Limit with External Programmability
The cycle-by-cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET on-state drain
to source voltage VDS(ON) with a threshold voltage. High drain
current causes VDS(ON) to exceed the threshold voltage and turns
the output MOSFET off until the start of the next clock cycle.
The current limit comparator threshold voltage is temperature
compensated to minimize the variation of the current limit due
to temperature related changes in RDS(ON) of the output MOSFET.
The default current limit of TOP264-271 is preset internally.
However, with a resistor connected between EXTERNAL
CURRENT LIMIT (X) pin and SOURCE pin, current limit can be
programmed externally to a lower level between 30% and 100%
of the default current limit. By setting current limit low, a larger
TOP264-271 than necessary for the power required can be used
to take advantage of the lower RDS(ON) for higher efficiency/
smaller heat sinking requirements. With a second resistor
connected between the EXTERNAL CURRENT LIMIT (X) pin
and the rectified DC high voltage bus, the current limit is
reduced with increasing line voltage, allowing a true power
limiting operation against line variation to be implemented. When
using an RCD clamp, this power limiting technique reduces
maximum clamp voltage at high line. This allows for higher
reflected voltage designs as well as reducing clamp dissipation.
Variable Frequency PWM mode: When peak drain current is
lowered to kPS(UPPER) × ILIMIT(set) as a result of power supply load
reduction, the PWM modulator initiates the transition to variable
frequency PWM mode, and gradually turns off frequency jitter.
In this mode, peak drain current is held constant at kPS(UPPER)
ILIMIT(set) while switching frequency drops from the initial full
frequency of fOSC (132 kHz or 66 kHz) towards the minimum
×
frequency of fMCM(MIN) (30 kHz typical). Duty cycle reduction is
accomplished by extending the off-time.
Low Frequency PWM mode: When switching frequency
reaches fMCM(MIN) (30 kHz typical), the PWM modulator starts to
transition to low frequency mode. In this mode, switching
frequency is held constant at fMCM(MIN) and duty cycle is reduced,
similar to the full frequency PWM mode, through the reduction
of the on-time. Peak drain current decreases from the initial
value of kPS(UPPER) × ILIMIT(set) towards the minimum value of
kPS(LOWER) × ILIMIT(set), where kPS(LOWER) is 25% (typical) and ILIMIT(set)
is the current limit externally set via the X pin.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that, if a
power supply is designed properly, current spikes caused by
primary-side capacitances and secondary-side rectifier reverse
recovery time should not cause premature termination of the
switching pulse. The current limit is lower for a short period
after the leading edge blanking time. This is due to dynamic
characteristics of the MOSFET. During startup and fault
conditions the controller prevents excessive drain currents by
reducing the switching frequency.
Multi-Cycle-Modulation mode: When peak drain current is
lowered to kPS(LOWER) × ILIMIT(set), the modulator transitions to
multi-cycle-modulation mode. In this mode, at each turn-on,
the modulator enables output switching for a period of TMCM(MIN)
at the switching frequency of fMCM(MIN) (4 or 5 consecutive pulses
at 30 kHz) with the peak drain current of kPS(LOWER) × ILIMIT(set),
and stays off until the CONTROL pin current falls below IC(OFF)
.
This mode of operation not only keeps peak drain current low
but also minimizes harmonic frequencies between 6 kHz and
30 kHz. By avoiding transformer resonant frequency this way,
all potential transformer audible noises are greatly suppressed.
Line Undervoltage Detection (UV)
At power up, UV keeps TOP264-271 off until the input line
voltage reaches the undervoltage threshold. At power down,
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Rev. B 03/10
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TOP264-271
VUV
VLINE
0 V
S14
S14
S15
S13 S12
S0
S15 S14
S13 S12
S0
S15
S13 S12
S0
S15
S15
5.8 V
4.8 V
VC
0 V
VDRAIN
0 V
VOUT
0 V
1
2
3
2
4
Note: S0 through S15 are the output states of the auto-restart counter
PI-4531-121206
Figure 7. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-Restart (4) Power Down.
UV prevents auto-restart attempts after the output goes out of
regulation. This eliminates power down glitches caused by slow
discharge of the large input storage capacitor present in
applications such as standby supplies. A single resistor
connected from the VOLTAGE-MONITOR pin to the rectified DC
high voltage bus sets UV threshold during power up. Once the
power supply is successfully turned on, the UV threshold is
lowered to 44% of the initial UV threshold to allow extended
input voltage operating range (UV low threshold). If the UV low
threshold is reached during operation without the power supply
losing regulation, the device will turn off and stay off until UV
(high threshold) has been reached again. If the power supply
loses regulation before reaching the UV low threshold, the
device will enter auto-restart. At the end of each auto-restart
cycle (S15), the UV comparator is enabled. If the UV high
threshold is not exceeded, the MOSFET will be disabled during
the next cycle (see Figure 7). The UV feature can be disabled
independent of the OV feature.
In order to reduce the no-load input power of TOP264-271
designs, the V pin operates at very low currents. This requires
careful layout considerations when designing the PCB to avoid
noise coupling. Traces and components connected to the V pin
should not be adjacent to any traces carrying switching currents.
These include the drain, clamp network, bias winding return or
power traces from other converters. If the line sensing features
are used, then the sense resistors must be placed within 10 mm
of the V pin to minimize the V pin node area. The DC bus
should then be routed to the line sense resistors. Note that
external capacitance must not be connected to the V pin as this
may cause misoperaton of the V pin related functions.
Hysteretic or Latching Output Overvoltage Protection (OVP)
The detection of the hysteretic or latching output overvoltage
protection (OVP) is through the trigger of the line overvoltage
threshold. The V pin voltage will drop by 0.5 V, and the
controller measures the external attached impedance immediately
after this voltage drops. If IV exceeds IOV(LS) (336 mA typical)
longer than 100 ms, TOP264-271 will latch into a permanent off
state for the latching OVP. It only can be reset if IX exceeds IX(TH)
= -27 mA (typ) or VC goes below the power-up-reset threshold
(VC(RESET)) and then back to normal. If IV does not exceed IOV(LS) or
exceeds no longer than 100 ms, TOP264-271 will initiate the line
overvoltage and the hysteretic OVP. Their behavior will be
identical to the line overvoltage shutdown (OV) that has been
described in detail in the previous section. During a fault
condition resulting from loss of feedback, output voltage will
rapidly rise above the nominal voltage. The increase in output
voltage will also result in an increase in the voltage at the output
of the bias winding. A voltage at the output of the bias winding
that exceeds of the sum of the voltage rating of the Zener diode
connected from the bias winding output to the V pin and V pin
voltage, will cause a current in excess of IV to be injected into
the V pin, which will trigger the OVP feature.
Line Overvoltage Shutdown (OV)
The same resistor used for UV also sets an overvoltage
threshold, which, once exceeded, will force TOP264-271 to
stop switching instantaneously (after completion of the current
switching cycle). If this condition lasts for at least 100 ms, the
TOP264-271 output will be forced into off state. When the line
voltage is back to normal with a small amount of hysteresis
provided on the OV threshold to prevent noise triggering, the
state machine sets to S13 and forces TOP264-271 to go
through the entire auto-restart sequence before attempting to
switch again. The ratio of OV and UV thresholds is preset at
4.5, as can be seen in Figure 8. When the MOSFET is off, the
rectified DC high voltage surge capability is increased to the
voltage rating of the MOSFET (725 V), due to the absence of the
reflected voltage and leakage spikes on the drain. The OV
feature can be disabled independent of the UV feature.
7
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Rev. B 03/10
TOP264-271
If the power supply is operating under heavy load or low input
line conditions when an open loop occurs, the output voltage
may not rise significantly. Under these conditions, a latching
shutdown will not occur until load or line conditions change.
Nevertheless, the operation provides the desired protection by
preventing significant rise in the output voltage when the line or
load conditions do change. Primary side OVP protection with
the TOP264-271 in a typical application will prevent a nominal
12 V output from rising above approximately 20 V under open
loop conditions. If greater accuracy is required, a secondary
sensed OVP circuit is recommended.
Remote ON/OFF
TOP264-271 can be turned on or off by controlling the current
into the VOLTAGE-MONITOR pin or out from the EXTERNAL
CURRENT LIMIT pin. In addition, the VOLTAGE-MONITOR pin
has a 1 V threshold comparator connected at its input. This
voltage threshold can also be used to perform remote ON/OFF
control.
When a signal is received at the VOLTAGE-MONITOR pin or the
EXTERNAL CURRENT LIMIT pin to disable the output through
any of the pin functions such as OV, UV and remote ON/OFF,
TOP264-271 always completes its current switching cycle before
the output is forced off.
Line Feed-Forward with DCMAX Reduction
The same resistor used for UV and OV also implements line voltage
feed-forward, which minimizes output line ripple and reduces
power supply output sensitivity to line transients. Note that for the
same CONTROL pin current, higher line voltage results in smaller
operating duty cycle. As an added feature, the maximum duty
cycle DCMAX is also reduced from 78% (typical) at a voltage slightly
lower than the UV threshold to 36% (typical) at the OV threshold.
DCMAX of 36% at high line was chosen to ensure that the power
capability of the TOP264-271 is not restricted by this feature under
normal operation. TOP264-271 provides a better fit to the ideal
feed-forward by using two reduction slopes: -1% per mA for all bus
voltage less than 195 V (typical for 4 MW line impedance) and
-0.25% per mA for all bus voltage more than 195 V.
As seen above, the remote ON/OFF feature can also be used as
a standby or power switch to turn off the TOP264-271 and keep
it in a very low power consumption state for indefinitely long
periods. If the TOP264-271 is held in remote off state for long
enough time to allow the CONTROL pin to discharge to the
internal supply undervoltage threshold of 4.8 V (approximately
32 ms for a 47 mF CONTROL pin capacitance), the CONTROL
pin goes into the hysteretic mode of regulation. In this mode,
the CONTROL pin goes through alternate charge and discharge
cycles between 4.8 V and 5.8 V (see CONTROL pin operation
Voltage Monitor and External Current Limit Pin Table*
Figure Number
12
13
14
15
16
17
18
19
20
21
22
23
Three Terminal Operation
Line Undervoltage (UV)
Line Overvoltage (OV)
Line Feed-Forward (DCMAX
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
)
Output Overvoltage Protection (OVP)
Overload Power Limiting (OPP)
External Current Limit
Remote ON/OFF
3
3
3
3
3
3
3
3
3
3
3
3
3
Device Reset
Fast AC Reset
3
3
AC Brownout
*This table is only a partial list of many VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Pin Configurations that are possible.
Table 2. VOLTAGE MONITOR (V) Pin and EXTERNAL CURRENT LIMIT (X) Pin Configuration Options.
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Rev. B 03/10
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TOP264-271
X Pin
V Pin
IREM(N)
IUV
IOV
IOV(LS)
(Enabled)
(Disabled)
Output
MOSFET
Switching
(Non-Latching) (Latching)
Disabled when supply
output goes out of
regulation
I
ILIMIT (Default)
Current
Limit
I
DCMAX (78%)
Maximum
Duty Cycle
I
VBG
Pin Voltage
I
-250
-200
-150
-100
-50
0
25
50
75
100
125
336
X and V Pins Current (µA)
Note: This figure provides idealized functional characteristics with typical performance values. Please refer to the parametric
table and typical performance characteristics sections of the data sheet for measured data. For a detailed description of
each functional pin operation refer to the Functional Description section of the data sheet.
PI-5528-060409
Figure 8. VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT (E and V package) Pin Characteristics.
section above) and runs entirely off the high voltage DC input,
but with very low power consumption (<100 mW typical at
230 VAC with X pin open). When the TOP264-271 is remotely
turned on after entering this mode, it will initiate a normal
start-up sequence with soft-start the next time the CONTROL
pin reaches 5.8 V. In the worst case, the delay from remote-on
to start-up can be equal to the full discharge/charge cycle time
of the CONTROL pin, which is approximately 125 ms for a
47 mF CONTROL pin capacitor. This reduced consumption
remote off mode can eliminate expensive and unreliable in-line
mechanical switches. It also allows for microprocessor
controlled turn-on and turn-off sequences that may be required
in certain applications such as inkjet and laser printers.
Soft-Start
The 17 ms soft-start sweeps the peak drain current and switching
frequency linearly from minimum to maximum value by operating
through the low frequency PWM mode and the variable
frequency mode before entering the full frequency mode. In
addition to start-up, soft-start is also activated at each restart
attempt during auto-restart and when restarting after being in
hysteretic regulation of CONTROL pin voltage (VC), due to
remote OFF or thermal shutdown conditions. This effectively
minimizes current and voltage stresses on the output MOSFET,
the clamp circuit and the output rectifier during start-up. This
feature also helps minimize output overshoot and prevents
saturation of the transformer during start-up.
9
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Rev. B 03/10
TOP264-271
Shutdown/Auto-Restart (for OCP, SCP, OPP)
Bandgap Reference
To minimize TOP264-271 power dissipation under fault
conditions such as over current (OC), short circuit (SC) or over
power (OP), the shutdown/auto-restart circuit turns the power
supply on and off at an auto-restart duty cycle of typically 2% if
an out of regulation condition persists. Loss of regulation
interrupts the external current into the CONTROL pin. VC
regulation changes from shunt mode to the hysteretic auto-
restart mode as described in CONTROL pin operation section.
When the fault condition is removed, the power supply output
becomes regulated, VC regulation returns to shunt mode, and
normal operation of the power supply resumes.
All critical TOP264-271 internal voltages are derived from a
temperature-compensated bandgap reference. This voltage
reference is used to generate all other internal current references,
which are trimmed to accurately set the switching frequency,
MOSFET gate drive current, current limit, and the line OV/UV/
OVP thresholds. TOP264-271 has improved circuitry to
maintain all of the above critical parameters within very tight
absolute and temperature tolerances.
High-Voltage Bias Current Source
This high-voltage current source biases TOP264-271 from the
DRAIN pin and charges the CONTROL pin external capacitance
during start-up or hysteretic operation. Hysteretic operation
occurs during auto-restart, remote OFF and over-temperature
shutdown. In this mode of operation, the current source is
switched on and off, with an effective duty cycle of approxi-
mately 35%. This duty cycle is determined by the ratio of
CONTROL pin charge (IC) and discharge currents (ICD1 and ICD2).
This current source is turned off during normal operation when
the output MOSFET is switching. The effect of the current
source switching will be seen on the DRAIN voltage waveform
as small disturbances and is normal.
Hysteretic Over-Temperature Protection (OTP)
Temperature protection is provided by a precision analog circuit
that turns the output MOSFET off when the junction temperature
exceeds the thermal shutdown temperature (142 °C typical).
When the junction temperature cools to below the lower
hysteretic temperature point, normal operation resumes, thus
providing automatic recovery. A large hysteresis of 75 °C
(typical) is provided to prevent overheating of the PC board due
to a continuous fault condition. VC is regulated in hysteretic
mode, and a 4.8 V to 5.8 V (typical) triangular waveform is
present on the CONTROL pin while in thermal shutdown.
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Rev. B 03/10
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TOP264-271
CONTROL (C)
200 µA
(Negative Current Sense - ON/OFF,
Current Limit Adjustment, OVP Latch Reset)
VBG + VT
EXTERNAL CURRENT LIMIT (X)
VOLTAGE MONITOR (V)
(Voltage Sense, ON/OFF)
1 V
VREF
(Positive Current Sense - Undervoltage,
Overvoltage, ON/OFF, Maximum Duty
Cycle Reduction, Output Over-
voltage Protection)
400 µA
PI-5567-030910
Figure 9. VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pin Input Simplified Schematic.
11
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Rev. B 03/10
TOP264-271
Typical Uses of FREQUENCY (F) Pin
+
+
DC
Input
DC
Input
Voltage
D
D
S
CONTROL
Voltage
CONTROL
F
C
C
S
F
-
-
PI-2655-071700
PI-2654-071700
Figure 10. Full Frequency Operation (132 kHz).
Figure 11. Half Frequency Operation (66 kHz).
12
Rev. B 03/10
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TOP264-271
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins
+
+
VUV = IUV × RLS + VV (IV = IUV
)
)
V Package
(eDIP-12)
E Package
(eSIP-7C)
V
OV = IOV × RLS + VV (IV = IOV
S 12
S 11
S 10
S 9
1 V
For RLS = 4 MΩ
2 X
VUV = 102.8 VDC
RLS 4 MΩ
3 C
4 F
VOV = 451 VDC
V X C
F
S
D
DC
Input
Voltage
DC
Input
Voltage
S 8
5 NC
DCMAX@100 VDC = 76%
DCMAX@375 VDC = 41%
S 7
6 D
S
D
S
V
D
C
C
S
D
D
S
V
CONTROL
CONTROL
C
C
X
F
-
-
PI-4717-120307
PI-5562-082809
Figure 13. Line-Sensing for Undervoltage, Overvoltage and Line Feed-Forward.
Figure 12. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL
CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to
SOURCE or CONTROL Pin.)
VUV = IUV × RLS + VV (IV = IUV
)
V
OV = IOV × RLS + VV (IV = IOV)
+
+
VUV = RLS × IUV + VV (IV = IUV
)
For RLS = 4 MΩ
4 MΩ
VUV = 102.8 VDC
For Values Shown
VUV = 103.8 VDC
VOV = 451 VDC
Sense Output Voltage
RLS
RLS
4 MΩ
ROVP
DC
Input
Voltage
DC
Input
Voltage
VROVP
40 kΩ
DCMAX @ 100 VDC = 76%
DCMAX @ 375 VDC = 41%
D
S
V
D
S
V
CONTROL
CONTROL
C
C
6.2 V
ROVP >3kΩ
-
-
PI-4720-120307
PI-4719-120307
Figure 14. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and
Hysteretic Output Overvoltage Protection.
Figure 15. Line Sensing for Undervoltage Only (Overvoltage Disabled).
+
+
For RIL = 12 kΩ
V
OV = IOV × RLS + VV (IV = IOV)
ILIMIT = 61%
4 MΩ
For Values Shown
VOV = 457.2 VDC
For RIL = 19 kΩ
ILIMIT = 37%
R
LS
DC
Input
Voltage
See Figure 35 for other
resistor values (RIL).
DC
Input
Voltage
D
S
55 kΩ
CONTROL
1N4148
C
D
V
CONTROL
C
X
RIL
S
-
-
PI-4721-120307
PI-5580-012210
Figure 16. Line-Sensing for Overvoltage Only (Undervoltage Disabled). Maximum
Duty Cycle Reduced at Low Line and Further Reduction with
Increasing Line Voltage.
Figure 17. External Set Current Limit.
13
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Rev. B 03/10
TOP264-271
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)
+
+
I
LIMIT = 100% @ 100 VDC
QR can be an optocoupler
output or can be replaced by
a manual switch.
53% @ 300 VDC
ILIMIT
=
RLS
2.5 MΩ
DC
Input
Voltage
DC
Input
Voltage
D
S
D
S
CONTROL
X
CONTROL
C
C
X
RIL
6 kΩ
ON/OFF
QR
47 KΩ
-
-
PI-5465-061009
PI-5466-061009
Figure 18. Current Limit Reduction with Line Voltage.
Figure 19. Active-on (Fail Safe) Remote ON/OFF, and Latch Reset.
VUV = IUV × RLS + VV (IV = IUV
)
+
+
QR can be an optocoupler
output or can be replaced
by a manual switch.
V
OV = IOV × RLS + VV (IV = IoV
)
DCMAX@100 VDC = 76%
DCMAX@375 VDC = 41%
4 MΩ
RLS
For RIL =12 kΩ
QR can be an optocoupler
output or can be replaced
by a manual switch.
I
LIMIT = 61%
DC
Input
Voltage
DC
Input
Voltage
D
S
D
S
V
For RIL = 19 kΩ
CONTROL
CONTROL
I
LIMIT = 37%
C
C
For RIL =12 kΩ
ILIMIT = 61%
X
X
RIL
RIL
QR
QR
ON/OFF
ON/OFF
16 kΩ
-
16 kΩ
-
PI-5531-072309
PI-5467-061009
Figure 21. Active-on Remote ON/OFF with Line Sense and External
Current Limit, and Latch Reset.
Figure 20. Active-on Remote ON/OFF with Externally Set Current Limit,
and Latch Reset
VUV = IUV x RLS + VV (IV = IUV
)
+
+
Typ. 65 VAC brownout threshold.
V
OV = IOV x RLS + VV (IV = IoV
)
<3 s AC latch reset time.
Higher gain QR allows increasing R1/
decreasing C1 for lower no-load input
power.
For RLS = 4 MΩ
4 MΩ
RLS
VUV = 102.8 VDC
VOV = 451 VDC
D
DC
Input
Voltage
DCMAX @ 100 VDC = 76%
DCMAX @ 375 VDC = 41%
DC
Input
Voltage
CONTROL
D
S
V
C
CONTROL
C
S
X
R1
4 MΩ
For RIL = 12 kΩ
ILIMIT = 61%
1N4007
RIL
X
QR
AC
Input
See Figure 35 for
other resistor values
(RIL) to select different
ILIMIT values.
RIL
12 kΩ
R2
C1
39 kΩ 47 nF
-
-
PI-5652-110609
Figure 22. Line Sensing and Externally Set Current Limit.
Figure 23. Externally Set Current Limit, Fast AC Latch Reset and Brownout.
14
Rev. B 03/10
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TOP264-271
device size often results in the same or lower efficiency due to
the larger switching losses associated with a larger MOSFET.
Application Example
Low No-load, High Efficiency, 65 W, Universal Input
Adapter Power Supply
Line Sense Resistor Values
• Increasing line sensing resistance from 4 MW to 10.2 MW to
reduce no-load input power dissipation by 16 mW
The circuit shown in Figure 24 shows a 90 VAC to 265 VAC
input, 19 V, 3.42 A output power supply, designed for operation
inside a sealed adapter case type. The goals of the design were
highest full load efficiency, highest average efficiency (average of
25%, 50%, 75% and 100% load points), and very low no-load
consumption. Additional requirements included latching output
overvoltage shutdown and compliance to safety agency limited
power source (LPS) limits. Measured efficiency and no-load
performance is summarized in the table shown in the schematic
which easily exceed current energy efficiency requirements.
Line sensing is provided by resistors R3 and R4 and sets the
line undervoltage and overvoltage thresholds. The combined
value of these resistors was increased from the standard 4 MW
to 10.2 MW. This reduced the resistor dissipation, and therefore
contribution to no-load input power, from ~26 mW to ~10 mW. To
compensate the resultant change in the UV (turn-on) threshold
resistor R20 was added between the CONTROL and VOLTAGE-
MONITOR pins. This adds a DC current equal to ~16 mA into the
V pin, requiring only 9 mA to be provided via R3 and R4 to reach
the V pin UV (turn-on) threshold current of 25 mA and setting the
UV threshold to 95 VDC.
In order to meet these design goals the following key design
decisions were made.
PI Part Selection
• One device size larger selected than required for power
delivery to increase efficiency
This technique does effectively disable the line OV feature as
the resultant OV threshold is raised from ~450 VDC to ~980 VDC.
However in this design there was no impact as the value of
input capacitance (C2) was sufficient to allow the design to
withstand differential line surges greater than 2 kV without the
peak drain voltage reaching the BVDSS rating of U1.
The current limit programming feature of TOPSwitch-JX allows
the selection of a larger device than needed for power delivery.
This gives higher full load, low line efficiency by reducing the
MOSFET conduction losses (IRMS2 × RDS(ON)) but maintains the
overload power, transformer and other components size as if a
smaller device had been used.
Specific guidelines and detailed calculations for the value of
R20 may be found in the TOPSwitch-JX Application Note (AN-47).
Clamp Configuration – RZCD vs RCD
• An RZCD (Zener bleed) was selected over an RCD clamp to
give higher light load efficiency and lower no-load consumption
For this design one device size larger than required for power
delivery (as recommended by the power table) was selected.
This typically gives the highest efficiency. Further increases in
Input Voltage (VAC)
Full Power Efficiency (%)
Average Efficiency (%)
90
115
230
C11
1 nF
250 VAC
C12
1 nF
100 V
R15
33 Ω
86.6 88.4 89.1
89.8 89.5
C13
470 µF 470 µF
25 V 25 V
C14
No-load Input Power (mW) 57.7 59.7 86.7
VR2
SMAJ250A
T1
RM10
19 V, 3.42 A
3
FL1
C4
C21
10 nF
50 V
D5
1000 pF
630 V
D1
R5
300 Ω
V30100C
GBU8J
600 V
FL2
5
R6
150 Ω
R28
RTN
R11
300 Ω
300 Ω
1
D4
C10
56 µF
35 V
R3
R7
BAV21WS-
7-F
R22
C5
5.1 MΩ 10 MΩ
R29
300 Ω
1.6 kΩ
4
2.2 nF
D2
RS1K
R16
20 kΩ
1 kV
C19
6.8 nF
50 V
L3
C15
Q1
R14
12 mH
470 pF
50 V
MMBT4403
R24
2.2 Ω
20 Ω
R4
R8
5.1 MΩ 10 MΩ
R10
100 Ω
C2
120 µF
400 V
D3
BAV19WS
R1
R2
R17
147 kΩ
1%
R27
10 kΩ
2.2 MΩ 2.2 MΩ
R12
4.7 kΩ
C9
220 nF
25 V
U3B
PS2501-
1-H-A
U3A
PS2501-
1-H-A
C1
R20
191 kΩ
1%
330 nF
275 VAC
VR1
ZMM5244B-7
Q2
MMBT3904
L4
200 µH
D
S
V
R25
20 Ω
1/8 W
C16
22 nF
50 V
CONTROL
TOPSwitch-JX
U1
TOP269EG
C
F1
4 A
R13
6.8 Ω
1/8 W
R19
20 kΩ
X
F
L
C6
100 nF
50 V
R9
11 kΩ
1%
C7
90 - 265
VAC
C22
100 nF
50 V
47 µF
16 V
U2
R18
LMV431AIMF
1%
N
10 kΩ
1%
PI-5667-030810
Figure 24. Schematic of High Efficiency 19 V, 65 W, Universal Input Flyback Supply With Low No-load.
15
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Rev. B 03/10
TOP264-271
The clamp network is formed by VR2, C4, R5, R6, R11, R28,
R29 and D2. It limits the peak drain voltage spike caused by
leakage inductance to below the BVDSS rating of the internal
TOPSwitch-JX MOSFET. This arrangement was selected over a
standard RCD clamp to improve light load efficiency and
no-load input power.
To minimize the dissipation from the bias winding under no-load
conditions the number of bias winding turns and value of C10
was adjusted to give a minimum voltage across C10 of ~9 V.
This is the minimum required to keep the optocoupler biased.
To minimize the dissipation of the secondary side feedback
circuit Q2 was added to form a Darlington connection with U3B.
This reduced the feedback current on the secondary to ~1 mA.
The increased loop gain (due to the hFE of the transistor) was
compensated by increasing the value of R16 and the addition of
R25. A standard 2.5 V TL431 voltage reference was replaced
with the 1.24 V LMV431 to reduce the supply current requirement
from 1 mA to 100 mA.
In a standard RCD clamp C4 would be discharged by a parallel
resistor rather than a resistor and series Zener. In an RCD clamp
the resistor value is selected to limit the peak drain voltage
under full load and overload conditions. However under light or
no-load conditions this resistor value now causes the capacitor
voltage to discharge significantly as both the leakage inductance
energy and switching frequency are lower. As the capacitor has
to be recharged to above the reflected output voltage each
switching cycle the lower capacitor voltage represents wasted
energy. It has the effect of making the clamp dissipation
appear as a significant load just as if it were connected to the
output of the power supply.
Output Rectifier Choice
• Higher current rating, low VF Schottky rectifier diode selected
for output rectifier
A dual 15 A, 100 V Schottky rectifier diode with a VF of 0.455 V
at 5 A was selected for D5. This is a higher current rating than
required to reduce resistive and forward voltage losses to improve
both full load and average efficiency. The use of a 100 V Schottky
was possible due to the high transformer primary to secondary
turns ratio (VOR = 110 V) which was in turn possible due to the high
voltage rating of the TOPSwitch-JX internal MOSFET.
The RZCD arrangement solves this problem by preventing the
voltage across the capacitor discharging below a minimum
value (defined by the voltage rating of VR2) and therefore
minimizing clamp dissipation under light and no-load conditions.
Increased Output Overvoltage Shutdown Sensitivity
• Transistor Q1 and VR1 added to improve the output over-
voltage shutdown sensitivity
Resistors R6 and R28 provide damping of high frequency
ringing to reduce EMI. Due to the resistance in series with VR2,
limiting the peak current, standard power Zeners vs a TVS type
may be used for lower cost (although a TVS type was selected
due to availability of a SMD version). Diode D2 was selected to
have an 800 V vs the typical 600 V rating due to its longer
reverse recovery time of 500 ns. This allows some recovery of
the clamp energy during the reverse recovery time of the diode
improving efficiency. Multiple resistors were used in parallel to
share dissipation as SMD components were used.
During an open loop condition the output and therefore bias
winding voltage will rise. When this exceeds the voltage of VR1
plus a VBE voltage drop Q1 turns on and current is fed into the
V pin. The addition of Q1 ensures that the current into the V pin
is sufficient to exceed the latching shutdown threshold even
when the output is fully loaded while the supply is operating at
low line as under this condition the output voltage overshoot is
relatively small
Feedback Configuration
• A Darlington connection formed together with optocoupler
transistor to reduce secondary side feedback current and
therefore no-load input power
• Low voltage, low current voltage reference IC used on
secondary side to reduce secondary side feedback current
and therefore no-load input power
Output overload power limitation is provided via the current limit
programming feature of the X pin and R7, R8 and R9. Resistors
R8 and R9 reduce the device current limit as a function of
increasing line voltage to provide a roughly flat overload power
characteristic, below the 100 VA limited power source (LPS)
requirement. In order to still meet this under a single fault condition
(such as open circuit of R8) the rise in the bias voltage that occurs
during an overload condition is also used to trigger a latching
shutdown.
• Bias winding voltage tuned to ~9 V at no-load, high line to
reduce no-load input power
Typically the feedback current into the CONTROL pin at high
line is ~3 mA. This current is both sourced from the bias
winding (voltage across C10) and directly from the output. Both
of these represent a load on the output of the power supply.
16
Rev. B 03/10
www.powerint.com
TOP264-271
Very Low No-load, High Efficiency, 30 W, Universal Input,
Open Frame, Power Supply
The size of the magnetic core is a function of the switching
frequency. The choice of the higher switching frequency of
132 kHz allowed for the use of a smaller core size. The higher
switching frequency does not negatively impact the efficiency in
TOPSwitch-JX designs due its small drain to source capacitance
(COSS) as compared to that of discrete MOSFETs.
The circuit shown in Figure 25 below shows an 85 VAC to
265 VAC input, 12 V, 2.5 A output power supply. The goals of
the design were highest full load efficiency, average efficiency
(average of 25%, 50%, 75% and 100% load points), very low no-
load consumption. Additional requirements included latching
output overvoltage shutdown and compliance to safety agency
limited power source (LPS) limits. Actual efficiency and no-load
performance is summarized in the table shown in the schematic
which easily exceed current energy efficiency requirements.
Line Sense Resistor Values
• Increasing line sensing resistance from 4 MW to 10.2 MW to
reduce no-load input power dissipation by 16 mW
Line sensing is provided by resistors R1 and R2 and sets the
line undervoltage and overvoltage thresholds. The combined
value of these resistors was increased from the standard 4 MW
to 10.2 MW. This reduced the resistor, and therefore contribution
to no-load input power, from ~26 mW to ~10 mW. To compensate
the resultant change in the UV threshold resistor R12 was
added between the CONTROL and VOLTAGE-MONITOR pins.
This adds a DC current equal to ~16 mA into the V pin, requiring
only 9 mA to be provided via R1 and R2 to reach the V pin UV
threshold current of 25 mA and setting the UV threshold to
approximately 95 VDC.
In order to meet these design goals the following key design
decisions were made.
PI part selection
• Ambient of 40 °C allowed one device size smaller than
indicated by the power table
The device selected for this design was based on the 85-265 VAC,
Open Frame, PCB heat sinking column of power table (Table 1).
One device size smaller was selected (TOP266V vs TOP267V)
due to the ambient specification of 40 °C (vs the 50°C assumed
in the power table) and the optimum PCB area and layout for
the device heatsink. The subsequent thermal and efficiency
data confirmed this choice. The maximum device temperature
was 107°C at full load, 40 °C, 85 VAC, 47 Hz (worst case
conditions) and average efficiency exceeded 83% ENERGY
STAR and EuP Tier 2 requirements.
This technique does effectively disable the line OV feature as
the resultant OV threshold is raised from ~450 VDC to ~980
VDC. However in this design there was no impact as the value
of input capacitance (C3) was sufficient to allow the design to
withstand differential line surges greater than 1 kV without the
peak drain voltage reaching the BVDSS rating of U1.
Specific guidelines and detailed calculations for the value of R12
may be found in the TOPSwitch-JX Application Note.
Transformer Core Selection
• 132 kHz switching frequency allowed the selection of smaller
core for lower cost
Input Voltage (VAC)
Full Load Efficiency (%)
Average Efficiency (%)
85
115
230
C11
1 nF
250 VAC
C12
1 nF
200 V
81.25 83.94 86.21
84.97 85.13
R17
22 Ω
C14
680 µF 680 µF
25 V 25 V
C15
C16
100 µF
25 V
No-load Input Power (mW) 60.8 61.98 74.74
L2
3.3 µH
VR1
P6KE180A
12 V, 2.5 A
6
7,8
D8,9
C4
SB560
4.7 nF
1 kV
11,12
1
R5
10 kΩ
RTN
C7
47 µF
25 V
1/2 W
D1
D2
1N4007 1N4007
4
R1
R3
NCNC
D5
FR107
D7
BAV21WS-
7-F
5.1 MΩ 10 MΩ
2
T1
EF25
R9
10 Ω
R18
110 Ω
R19
470 Ω
C3
82 µF
400 V
VR3
ZMM5245B-7
R2
R4
C18
47 nF
50 V
5.1 MΩ 10 MΩ
D6
BAV19WS
R21
86.6 kΩ
1%
D10
LL4148
U2B
LTV817D
L1
R12
191 kΩ
1%
14 mH
U2A
LTV817D
D3
D4
1N4007 1N4007
D
S
V
CONTROL
TOPSwitch-JX
U1
TOP266VG
C1
100 nF
275 VAC
C
F1
R16
C20
33 nF
50 V
3.15 A
6.8 Ω
X
F
C9
100 nF
50 V
L
1/8 W
R15
14.3 kΩ
1%
C10
47 µF
25 V
85 - 264
VAC
U3
LMV431A
1%
R23
10 kΩ
1%
N
PI-5775-030810
Figure 25. Schematic of High Efficiency 12 V, 30 W, Universal Input Flyback Supply With Very Low No-load.
17
www.powerint.com
Rev. B 03/10
TOP264-271
Clamp Configuration – RZCD vs RCD
1.24 V LMV431 to reduce the supply current requirement of this
• An RZCD (Zener bleed) was selected over RCD to give higher
light load efficiency and lower no-load consumption
component from 1 mA to 100 mA.
Output Rectifier Choice
• Use of high VOR allows the use of a 60 V Schottky diode for
high efficiency and lower cost
The clamp network is formed by VR1, C4, R5 and D5. It limits
the peak drain voltage spike caused by leakage inductance to
below the BVDSS rating of the internal TOPSwitch-JX MOSFET.
This arrangement was selected over a standard RCD clamp to
improve light load efficiency and no-load input power.
The higher BVDSS rating of the TOPSwitch-JX of 725 V
(compared to 600 V or 650 V rating of typical power MOSFETs)
allowed a higher transformer primary to secondary turns ratio
(reflected output voltage or VOR). This reduced the output diode
voltage stress and allowed the use of cheaper and more efficient
60 V (vs 80 V or 100 V) Schottky diodes. The efficiency
improvement occurs due the lower forward voltage drop of the
lower voltage diodes. Two parallel connected axial 5 A, 60 V
Schottky rectifier diodes were selected for both low cost and
high efficiency. This allowed PCB heat sinking of the diode for
low cost while maintaining efficiency compared to a single
higher current TO-220 packaged diode mounted on a heatsink.
For this configuration the recommendation is that each diode is
rated at twice the output current and that the diodes share a
common cathode PCB area for heat sinking so that their
temperatures track. In practice the diodes current share quite
effectively as can be demonstrated by monitoring their
individual temperatures.
In a standard RCD clamp C4 would be discharged by a parallel
resistor rather than a resistor and series Zener. In an RCD
clamp the resistor value of R5 is selected to limit the peak drain
voltage under full load and over-load conditions. However
under light or no-load conditions this resistor value now causes
the capacitor voltage to discharge significantly as both the
leakage inductance energy and switching frequency are lower.
As the capacitor has to be recharged to above the reflected
output voltage each switching cycle the lower capacitor voltage
represents wasted energy. It has the effect of making the
clamp dissipation appear as a significant load just as if it were
connected to the output of the power supply.
The RZCD arrangement solves this problem by preventing the
voltage across the capacitor discharging below a minimum
value (defined by the voltage rating of VR1) and therefore
minimizing clamp dissipation under light and no-load conditions.
Zener VR1 is shown as a high peak dissipation capable TVS
however a standard lower cost Zener may also be used due to
the low peak current that component experiences.
Output Inductor Post Filter Soft-Finish
• Inductor L2 used to provide an output soft-finish and eliminate
a capacitor
To prevent output overshoot during start-up the voltage
appearing across L2 is used to provide a soft-finish function.
When the voltage across L2 exceeds the forward drop of U2A
and D10 current flows though the optocoupler LED and
provides feedback to the primary. This arrangement acts to
limit the rate of rise of the output voltage until it reaches
regulation and eliminates the capacitor that is typically placed
across U3 to provide the same function.
In many designs a resistor value of less than 50 W may be used
in series with C4 to damp out high frequency ringing and
improve EMI but this was not necessary in this case.
Feedback Configuration
• A high CTR optocoupler was used to reduce secondary bias
currents and no-load input power
• Low voltage, low current voltage reference IC used on
secondary side to reduce secondary side feedback current
and no-load input power
• Bias winding voltage tuned to ~9 V at no-load, high line to
reduce no-load input power
Key Application Considerations
TOPSwitch-JX vs. TOPSwitch-HX
Table 4 compares the features and performance differences
between TOPSwitch-JX and TOPSwitch-HX. Many of the new
features eliminate the need for additional discrete components.
Other features increase the robustness of design, allowing cost
savings in the transformer and other power components.
Typically the feedback current into the CONTROL pin at high
line is ~3 mA. This current is both sourced from the bias
winding (voltage across C10) and directly from the output. Both
of these represent a load on the output of the power supply.
TOP264-271 Design Considerations
To minimize the dissipation from the bias winding under no-load
conditions the number of bias winding turns and value of C7
was adjusted to give a minimum voltage across C7 of ~9 V.
This is the minimum required to keep the optocoupler biased
and the output in regulation.
Power Table
The data sheet power table (Table 1) represents the maximum
practical continuous output power based on the following
conditions:
1. 12 V output.
To minimize the dissipation of the secondary side feedback
circuit a high CTR (CTR of 300 – 600%) optocoupler type was
used. This reduces the secondary side opto-led current from
~3 mA to <~1 mA and therefore the effective load on the output.
A standard 2.5 V TL431 voltage reference was replaced with the
2. Schottky or high efficiency output diode.
3. 135 V reflected voltage (VOR) and efficiency estimates.
4. A 100 VDC minimum DC bus for 85-265 VAC and 250 VDC
minimum for 230 VAC.
5. Sufficient heat sinking to keep device temperature ≤110 °C.
18
Rev. B 03/10
www.powerint.com
TOP264-271
TOPSwitch-HX vs. TOPSwitch-JX
Function
TOPSwitch-HX
TOPSwitch-JX
TOPSwitch-JX Advantages
CONTROL current IC(OFF) at
0% duty cycle
IC(OFF) = IB + 3.4 mA
(TOP256-258)
IB = External bias current
IC(OFF) = IB + 1.6 mA
(TOP266-268)
•
•
•
Reduced CONTROL current
Better no-load performance (<0.1 W)
Better standby performance
eDIP-12 package
Not available
Available
•
•
66/132 kHz frequency option for DIP style heatsink
less designs
Better thermal performance for increased power
capability over DIP-8 package
Breakdown voltage BVDSS
Fast AC reset
Min. 700 V at TJ = 25 °C
Min. 725 V at TJ = 25 °C
•
•
•
Simplifies meeting customer derating requirements
(e.g. 80%)
Extended line surge withstand
3 External transistor circuits
using the V pin
1 External transistor circuit
using the X pin
Saves 5 components
Table 4.
Comparison Between TOPSwitch-HX and TOPSwitch-JX.
Zener clamp and allows a VOR as high as 150 V. RCD clamp
dissipation can be minimized by reducing the external current
limit as a function of input line voltage (see Figure 18). The RCD
clamp is more cost effective than the Zener clamp but requires
more careful design (see Quick Design Checklist).
6. Power levels shown in the power table for the V package
device assume 6.45 cm2 of 610 g/m2 copper heat sink area
in an enclosed adapter, or 19.4 cm2 in an open frame.
The provided peak power depends on the current limit for the
respective device.
Output Diode
The output diode is selected for peak inverse voltage, output
current, and thermal conditions in the application (including heat
sinking, air circulation, etc.). The higher DCMAX of TOP264-271,
along with an appropriate transformer turns ratio, can allow the
use of a 80 V Schottky diode for higher efficiency on output
voltages as high as 15 V.
TOP264-271 Selection
Selecting the optimum TOP264-271 depends upon required
maximum output power, efficiency, heat sinking constraints,
system requirements and cost goals. With the option to
externally reduce current limit, TOP264-271 may be used for
lower power applications where higher efficiency is needed or
minimal heat sinking is available.
Bias Winding Capacitor
Due to the low frequency operation at no-load, a bias winding
capacitance of 10 mF minimum is recommended. Ensure a
minimum bias winding voltage of >9 V at zero load for correct
operation and output voltage regulation.
Input Capacitor
The input capacitor must be chosen to provide the minimum
DC voltage required for the TOP264-271 converter to maintain
regulation at the lowest specified input voltage and maximum
output power. Since TOP264-271 has a high DCMAX limit and an
optimized dual slope line feed forward for ripple rejection, it is
possible to use a smaller input capacitor. For TOP264-271, a
capacitance of 2 mF per watt is possible for universal input with
an appropriately designed transformer.
Soft-Start
Generally, a power supply experiences maximum stress at
start-up before the feedback loop achieves regulation. For a
period of 17 ms, the on-chip soft-start linearly increases the
drain peak current and switching frequency from their low
starting values to their respective maximum values. This
causes the output voltage to rise in an orderly manner, allowing
time for the feedback loop to take control of the duty cycle.
This reduces the stress on the TOP264-271 MOSFET, clamp
circuit and output diode(s), and helps prevent transformer
saturation during start-up. Also, soft-start limits the amount of
output voltage overshoot and, in many applications, eliminates
the need for a soft-finish capacitor. Note that as soon as the
loop closes the soft-start function ceases even if this is prior to
the end of the 17 ms soft-start period.
Primary Clamp and Output Reflected Voltage VOR
A primary clamp is necessary to limit the peak TOP264-271 drain
to source voltage. A Zener clamp requires few parts and takes
up little board space. For good efficiency, the clamp Zener
should be selected to be at least 1.5 times the output reflected
voltage VOR, as this keeps the leakage spike conduction time
short. When using a Zener clamp in a universal input application,
a VOR of less than 135 V is recommended to allow for the absolute
tolerances and temperature variations of the Zener. This will
ensure efficient operation of the clamp circuit and will also keep
the maximum drain voltage below the rated breakdown voltage
of the TOP264-271 MOSFET. A high VOR is required to take full
advantage of the wider DCMAX of TOP264-271. An RCD (or
RCDZ) clamp provides tighter clamp voltage tolerance than a
EMI
The frequency jitter feature modulates the switching frequency
over a narrow band as a means to reduce conducted EMI peaks
associated with the harmonics of the fundamental switching
19
www.powerint.com
Rev. B 03/10
TOP264-271
frequency. This is particularly beneficial for average detection
mode. As can be seen in Figures 26 and 27, the benefits of jitter
increase with the order of the switching harmonic due to an
increase in frequency deviation. The FREQUENCY pin offers a
switching frequency option of 132 kHz or 66 kHz. In applications
that require heavy snubber on the drain node for reducing high
frequency radiated noise (for example, video noise sensitive
applications such as VCRs, DVDs, monitors, TVs, etc.), operating
at 66 kHz will reduce snubber loss, resulting in better efficiency.
Also, in applications where transformer size is not a concern, use
of the 66 kHz option will provide lower EMI and higher efficiency.
Note that the second harmonic of 66 kHz is still below 150 kHz,
above which the conducted EMI specifications get much tighter.
For 10 W or below, it is possible to use a simple inductor in place
of a more costly AC input common mode choke to meet
worldwide conducted EMI limits.
be located closely between their respective pin and SOURCE.
Once again, the SOURCE connection trace of these components
should not be shared by the main MOSFET switching currents.
It is very critical that SOURCE pin switching currents are returned
to the input capacitor negative terminal through a separate trace
that is not shared by the components connected to CONTROL,
VOLTAGE MONITOR or EXTERNAL CURRENT LIMIT pins. This
is because the SOURCE pin is also the controller ground
reference pin. Any traces to the V, X or C pins should be kept
as short as possible and away from the DRAIN trace to prevent
noise coupling. VOLTAGE MONITOR resistors (RLS in Figures
13, 14, 18, 21, 22, 25, 29) and primary side OVP circuit
components VZOV/ROV in Figures (28, 29) should be located close
to the V pin to minimize the trace length on the V pin side.
Resistors connected to the V or X pin should be connected as
close to the bulk cap positive terminal as possible while routing
these connections away from the power switching circuitry. In
addition to the 47 mF CONTROL pin capacitor, a high frequency
bypass capacitor (CBP) in parallel should be used for better noise
immunity. The feedback optocoupler output should also be
Transformer Design
It is recommended that the transformer be designed for
maximum operating flux density of 3000 Gauss and a peak flux
density of 4200 Gauss at maximum current limit. The turns ratio
should be chosen for a reflected voltage (VOR) no greater than
135 V when using a Zener clamp or 150 V (max) when using an
RCD clamp with current limit reduction with line voltage (overload
protection). For designs where operating current is significantly
lower than the default current limit, it is recommended to use an
externally set current limit close to the operating peak current to
reduce peak flux density and peak power (see Figure 17).
80
70
60
50
40
30
Standby Consumption
Frequency reduction can significantly reduce power loss at light
or no load, especially when a Zener clamp is used. For very low
secondary power consumption, use a TL431 regulator for
feedback control. A typical TOP264-271 circuit automatically
enters MCM mode at no load and the low frequency mode at
light load, which results in extremely low losses under no-load
or standby conditions.
20
-10
0
EN55022B (QP)
EN55022B (AV)
-10
-20
0.15
1
10
30
High Power Designs
Frequency (MHz)
The TOP264-271 family contains parts that can deliver up to
162 W. High power designs need special considerations.
Guidance for high power designs can be found in the Design
Guide for TOP264-271 (AN-47).
Figure 26. Fixed Frequency Operation Without Jitter.
80
70
60
TOPSwitch-JX (with jitter)
TOP264-271 Layout Considerations
50
40
30
20
-10
0
The TOP264-271 has multiple pins and may operate at high
power levels. The following guidelines should be carefully
followed.
Primary Side Connections
Use a single point (Kelvin) connection at the negative terminal of
the input filter capacitor for the SOURCE pin and bias winding
return. This improves surge capabilities by returning surge
currents from the bias winding directly to the input filter
capacitor. The CONTROL pin bypass capacitor should be
located as close as possible to the SOURCE and CONTROL
pins, and its SOURCE connection trace should not be shared
by the main MOSFET switching currents. All SOURCE pin
referenced components connected to the VOLTAGE MONITOR
(V pin) or EXTERNAL CURRENT LIMIT (X pin) pins should also
EN55022B (QP)
EN55022B (AV)
-10
-20
0.15
1
10
30
Frequency (MHz)
Figure 27. TOPSwitch-JX Full Range EMI Scan (132 kHz With Jitter) With
Identical Circuitry and Conditions.
20
Rev. B 03/10
www.powerint.com
TOP264-271
located close to the CONTROL and SOURCE pins of TOP264-271
and away from the drain and clamp component traces. The
primary side clamp circuit should be positioned such that the loop
area from the transformer end (shared with DRAIN) and the clamp
capacitor is minimized. The bias winding return node should be
connected via a dedicated trace directly to the bulk capacitor
and not to the SOURCE pins. This ensures that surge currents
are routed away from the SOURCE pins of the TOPSwitch-JX.
of the V pin to minimize the V pin node area. The DC bus
should then be routed to the line sense resistors. Note that
external capacitance must not be connected to the V pin as this
may cause misoperaton of the V pin related functions. As with
any power supply design, all TOP264-271 designs should be
verified on the bench to make sure that components specifi-
cations are not exceeded under worst-case conditions. The
following minimum set of tests is strongly recommended:
Y Capacitor
1. Maximum drain voltage – Verify that peak VDS does not
exceed 675 V at highest input voltage and maximum
overload output power. Maximum overload output power
occurs when the output is overloaded to a level just before
the power supply goes into auto-restart (loss of regulation).
2. Maximum drain current – At maximum ambient temperature,
maximum input voltage and maximum output load, verify
drain current waveforms at start-up for any signs of trans-
former saturation and excessive leading edge current spikes.
TOP264-271 has a leading edge blanking time of 220 ns to
prevent premature termination of the ON-cycle. Verify that
the leading edge current spike is below the allowed current
limit envelope (see Figure 32) for the drain current waveform
at the end of the 220 ns blanking period.
3. Thermal check – At maximum output power, both minimum
and maximum voltage and ambient temperature; verify that
temperature specifications are not exceeded for TOP264-
271, transformer, output diodes and output capacitors.
Enough thermal margin should be allowed for the part-to-
part variation of the RDS(ON) of TOP264-271, as specified in
the data sheet. The margin required can either be calculated
from the values in the parameter table or it can be accounted
for by connecting an external resistance in series with the
DRAIN pin and attached to the same heat sink, having a
resistance value that is equal to the difference between the
measured RDS(ON) of the device under test and the worst case
maximum specification.
The Y capacitor should be connected close to the secondary
output return pin(s) and the positive primary DC input pin of the
transformer. If the Y capacitor is returned to the negative end of
the input bulk capacitor (rather than the positive end) a dedicated
trace must be used to make this connection. This is to “steer”
leakage currents away from the SOURCE pins in case of a
common-mode surge event.
Heat Sinking
The exposed pad of the E package (eSIP-7C) and the V package
(eDIP-12) is internally electrically tied to the SOURCE pin. To
avoid circulating currents, a heat sink attached to the exposed
pad should not be electrically tied to any primary ground/source
nodes on the PC board. On double sided boards, topside and
bottom side areas connected with vias can be used to increase
the effective heat sinking area. In addition, sufficient copper
area should be provided at the anode and cathode leads of the
output diode(s) for heat sinking. In Figure 28, a narrow trace is
shown between the output rectifier and output filter capacitor.
This trace acts as a thermal relief between the rectifier and filter
capacitor to prevent excessive heating of the capacitor.
Quick Design Checklist
In order to reduce the no-load input power of TOP264-271
designs, the V pin operates at very low current. This requires
careful layout considerations when designing the PCB to avoid
noise coupling. Traces and components connected to the V pin
should not be adjacent to any traces carrying switching currents.
These include the drain, clamp network, bias winding return or
power traces from other converters. If the line sensing features
are used, then the sense resistors must be placed within 10 mm
Design Tools
Up-to-date information on design tools can be found at the
Power Integrations website: www.powerint.com
21
www.powerint.com
Rev. B 03/10
TOP264-271
DC
OUT
Maximize Copper Area
for Optimum Heat Sinking
–
RLS1
RPL1
J2
CB
U2
ROV
DB
U3
T1
HF LC
Post-Filter
C16
C18
VZOV
R12
Output Filter
Capacitors
U1
RIL
R16
CBP
Transformer
L2
C10
C17
D8
Output
Rectifiers
J1
D9
D5
C3
R5
DC
IN
Y-
Capacitor
VR1
C11
C4
Clamp Circuit
Input Filter
Capacitor
PI-5752-012510
Figure 28. Layout Considerations for TOPSwitch-JX Using V-Package and Operating at 132 kHz.
Isolation Barrier
Clamp
Circuit
Y-
Input Filter
Capacitor
Capacitor
C6
R7
T1
C16
R12
R6
HS1
D5
J1
C4
+
HV
-
D8
HS2
Output
Rectifier
Transformer
Output Filter
Capacitors
VR1
U1
D
CBP
S
V
C9
R8
C17
F
X
RIL
C
L3
RLS2
HF LC
Post-Filter
RLS1
RPL1
CB
C18
DB
U4
ROV
RPL2
R10
C19
C21
R20
VZOV
R9
J2
R17
R13
U2
JP2
R15
R21
DC
OUT
-
+
PI-5793-030910
Figure 29. Layout Considerations for TOPSwitch-JX Using E-Package and Operating at 132 kHz.
22
Rev. B 03/10
www.powerint.com
TOP264-271
Absolute Maximum Ratings(2)
DRAIN Pin Peak Voltage..........................................................-0.3 V to 725 V
DRAIN Pin Peak Current: TOP264.......................................................2.08 A
DRAIN Pin Peak Current: TOP265........................................................2.72 A
DRAIN Pin Peak Current: TOP266.......................................................4.08 A
DRAIN Pin Peak Current: TOP267........................................................5.44 A
DRAIN Pin Peak Current: TOP268.......................................................6.88 A
DRAIN Pin Peak Current: TOP269........................................................ 7.73 A
DRAIN Pin Peak Current: TOP270........................................................9.00 A
DRAIN Pin Peak Current: TOP271........................................................ 11.10 A
CONTROL Pin Voltage...................................................................-0.3 V to 9 V
CONTROL Pin Current.............................................................................100 mA
VOLTAGE MONITOR Pin Voltage............................................-0.3 V to 9 V
CURRENT LIMIT Pin Voltage................................................-0.3 V to 4.5 V
FREQUENCY Pin Voltage ...........................................................-0.3 V to 9 V
Storage Temperature ...........................................................-65 °C to 150 °C
Operating Junction Temperature................................... -40 °C to 150 °C
Lead Temperature(1)......................................................................................260 °C
Notes:
1. 1/16 in. from case for 5 seconds.
2. Maximum ratings specified may be applied one at a time
without causing permanent damage to the product. Exposure
to Absolute Maximum Rating conditions for extended periods
of time may affect product reliability.
Thermal Resistance
Thermal Resistance: E Package
Notes:
(qJA) ................................................................105 °C/W(1) 1. Free standing with no heatsink.
(qJC) ....................................................................2 °C/W(2) 2. Measured at the back surface of tab.
3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
V Package
(qJA) ........................................68 °C/W(3), 58 °C/W(4)
(qJC) ....................................................................2 °C/W(2)
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter
Symbol
Min
Typ
Max
Units
See Figure 32
(Unless Otherwise Specified)
Control Functions
FREQUENCY Pin
Switching Frequency
in Full Frequency
Mode (average)
119
132
66
145
Connected to SOURCE
fOSC
TJ = 25 °C
kHz
FREQUENCY Pin
59.4
72.6
Connected to CONTROL
132 kHz Operation
66 kHz Operation
5
Frequency Jitter
Deviation
kHz
Hz
Df
2.5
Frequency Jitter
Modulation Rate
fM
250
78
IV ≤ IV(DC)
75
30
83
VV = 0 V
Maximum Duty Cycle
Soft-Start Time
DCMAX
IC = ICD1
%
IV = 95 mA
tSOFT
TJ = 25 °C
17
ms
TOP264-265
TOP266-268
TOP269-271
TOP264-265
TOP266-268
TOP269-271
-62
-54
-50
-61
-60
-57
-50
-44
-40
-51
-50
-48
-40
-34
-30
-41
-40
-38
TJ = 25 °C
IB < IC < IC01
See Note C
PWM Gain
DCreg
%/mA
TJ = 25 °C
IC ≥ IC01
See Note A
PWM Gain
Temperature Drift
See Note B
-0.01
%/mA/°C
mA
TOP264-265
TOP266-268
TOP269-271
0.8
0.9
1.0
1.4
1.5
1.6
2.0
2.1
2.2
External Bias Current
IB
66 kHz Operation
23
www.powerint.com
Rev. B 03/10
TOP264-271
Conditions
Parameter
Symbol
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
mA
Control Functions (cont.)
External Bias Current
TOP264-265
0.9
1.2
1.5
1.5
1.8
2.1
2.9
3.1
3.3
3.1
3.4
3.8
21
2.1
2.4
2.8
3.9
4.1
4.3
4.1
4.4
4.8
25
IB
132 kHz Operation
66 kHz Operation
132 kHz Operation
TOP266-268
TOP269-271
TOP264-265
TOP266-268
TOP269-271
TOP264-265
TOP266-268
TOP269-271
CONTROL Current at
0% Duty Cycle
IC(OFF)
mA
Dynamic Impedance
ZC
IC = 2.5 mA; TJ = 25 °C, See Figure 31
13
50
W
Dynamic Impedance
Temperature Drift
0.18
7
%/°C
CONTROL Pin Internal
Filter Pole
kHz
%
Upper Peak Current to
Set Current Limit Ratio
TJ = 25 °C
See Note C
kPS(UPPER)
kPS(LOWER)
55
25
60
Lower Peak Current to
Set Current Limit Ratio
TJ = 25 °C
See Note C
%
Multi-Cycle-
Modulation Switching
Frequency
fMCM(MIN)
TJ = 25 °C
TJ = 25 °C
30
kHz
Minimum Multi-Cycle-
Modulation On Period
TMCM(MIN)
135
ms
Shutdown/Auto-Restart
VC = 0 V
-5.0
-3.0
-3.5
-1.8
-1.0
-0.6
CONTROL Pin
Charging Current
IC(CH)
TJ = 25 °C
mA
VC = 5 V
Charging Current
Temperature Drift
See Note B
0.5
5.8
4.8
%/°C
Auto-Restart
Upper Threshold
Voltage
VC(AR)U
V
V
Auto-Restart Lower
Threshold Voltage
VC(AR)L
4.5
0.8
5.1
Voltage Monitor (V) and External Current Limit (X) Inputs
Auto-Restart
VC(AR)hyst
1.0
2
V
Hysteresis Voltage
Auto-Restart Duty
DC(AR)
4
%
Cycle
Auto-Restart
f(AR)
0.5
Hz
Frequency
Line Undervoltage
Threshold Current and
Hysteresis (V Pin)
Threshold
Hysteresis
Threshold
Hysteresis
22
25
14
112
4
27
mA
mA
mA
mA
IUV
TJ = 25 °C
TJ = 25 °C
Line Overvoltage
Threshold Current and
Hysteresis (V Pin)
107
117
IOV
24
Rev. B 03/10
www.powerint.com
TOP264-271
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter
Symbol
Min
Typ
Max
Units
(Unless Otherwise Specified)
Voltage Monitor (V) and External Current Limit (X) Inputs (cont.)
Output Overvoltage
Latching Shutdown
Threshold Current
IOV(LS)
TJ = 25 °C
269
336
403
mA
V Pin Remote
ON/OFF Voltage
VV(TH)
TJ = 25 °C
0.8
-35
1.0
-27
5
1.6
-20
V
X Pin Remote ON/OFF
and Latch Reset
Negative Threshold
Current and Hysteresis
Threshold
Hysteresis
VV = VC
IREM (N)
TJ = 25 °C
mA
V Pin Short Circuit
Current
IV(SC)
TJ = 25 °C
VX = 0 V
IV = IOV
300
400
500
mA
mA
Normal Mode
-260
-95
-200
-75
-140
-55
X Pin Short Circuit
Current
IX(SC)
Auto-Restart Mode
V Pin Voltage
(Positive Current)
VV
TOP264-TOP271
IV = IOV
2.83
0.2
3.0
0.5
3.25
V
V
V Pin Voltage Hysteresis
(Positive Current)
VV(hyst)
1.23
1.15
1.30
1.22
1.37
1.29
IX = -50 mA
X Pin Voltage
(Negative Current)
VX
V
IX = -150 mA
Maximum Duty Cycle
Reduction Onset
Threshold Current
IC ≥ IB, TJ = 25 °C
18.9
22.0
24.2
IV(DC)
mA
-1.0
-0.25
0.6
IV(DC) < IV <48 mA
IV ≥48 mA
Maximum Duty Cycle
Reduction Slope
TJ = 25 °C
%/mA
X or V Pin Floating
1.0
1.6
Remote-OFF DRAIN
Supply Current
ID(RMT)
VDRAIN = 150 V
mA
V Pin Shorted to
CONTROL
1.0
From Remote-ON to Drain
Turn-On
66 kHz
132 kHz
66 kHz
3.0
1.5
3.0
1.5
Remote-ON Delay
tR(ON)
ms
ms
See Note C
Minimum Time Before Drain
Turn-On to Disable Cycle
See Note C
Remote-OFF
Set-up Time
tR(OFF)
132 kHz
Frequency Input
FREQUENCY Pin
Threshold Voltage
VF
IF
See Note B
TJ = 25 °C
2.9
55
V
FREQUENCY Pin
Input Current
VF = VC
10
90
mA
25
www.powerint.com
Rev. B 03/10
TOP264-271
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter
Symbol
Min
Typ
Max
Units
(Unless Otherwise Specified)
Circuit Protection
TOP264E/V
1.209
1.581
2.371
2.800
3.023
3.236
1.30
1.70
2.55
3.01
3.25
3.48
1.391
1.819
2.728
3.222
3.478
3.723
di/dt = 270 mA/ms
TJ = 25 °C
TOP265E/V
di/dt = 350 mA/ms
TJ = 25 °C
TOP266E/V
di/dt = 530 mA/ms
TJ = 25 °C
TOP267E/V
Self Protection
Current Limit
(See Note C)
di/dt = 625 mA/ms
TJ = 25 °C
ILIMIT
A
TOP268E/V
di/dt = 675 mA/ms
TJ = 25 °C
TOP269E/V
di/dt = 720 mA/ms
TJ = 25 °C
TOP270E/V
3.906
4.808
4.20
5.17
4.494
5.532
di/dt = 870 mA/ms
TJ = 25 °C
TOP271E/V
di/dt = 1065 mA/ms
TJ = 25 °C
0.70 ×
ILIMIT(MIN)
Initial Current Limit
Power Coefficient
IINIT
See Note C
A
0.9 × I2f
0.9 × I2f
I2f
I2f
1.2 × I2f
1.2 × I2f
IX ≤ - 165 mA
TJ = 25 °C,
See Note E
PCOEFF
A2kHz
IX ≤ - 117 mA
Leading Edge
Blanking Time
tLEB
tIL(D)
TJ = 25 °C, See Figure 32
220
100
142
ns
ns
°C
Current Limit Delay
Thermal Shutdown
Temperature
135
150
Thermal Shutdown
Hysteresis
75
°C
V
Power-Up Reset
Threshold Voltage
VC(RESET)
Figure 33 (S1 Open Condition)
1.75
3.0
4.25
26
Rev. B 03/10
www.powerint.com
TOP264-271
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter
Symbol
Min
Typ
Max
Units
(Unless Otherwise Specified)
Output
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
5.4
8.35
4.1
6.25
9.70
4.70
7.30
3.20
4.75
2.30
3.60
1.95
2.90
1.70
2.60
1.40
2.10
1.20
1.80
TOP264
ID = 150 mA
TOP265
ID = 200 mA
6.3
2.8
TOP266
ID = 300 mA
4.1
2.0
TOP267
ID = 400 mA
3.1
ON-State
Resistance
RDS(ON)
W
1.7
TOP268
ID = 500 mA
2.5
1.45
2.25
1.20
1.80
1.05
1.55
TOP269
ID = 600 mA
TOP270
ID = 700 mA
TOP271
ID = 800 mA
TJ ≤ 85 °C, See Note F
18
36
DRAIN Supply Voltage
V
OFF-State Drain
Leakage Current
VV = Floating, Device Not Switching,
IDSS
470
mA
VDS = 580 V, TJ = 125 °C
Breakdown
Voltage
VV = Floating, Device Not Switching,
BVDSS
725
V
TJ = 25 °C, See Note G
Rise Time
Fall Time
tR
tF
100
50
ns
ns
Measured in a Typical Flyback
Converter Application
Supply Voltage Characteristics
TOP264-265
66 kHz
Operation
0.6
0.9
1.1
0.8
1.2
1.5
1.2
1.4
1.6
1.4
1.7
2.1
2.0
2.3
2.5
2.1
2.4
2.9
TOP266-268
TOP269-271
TOP264-265
TOP266-268
TOP269-271
Output
MOSFET
Enabled
VX, VV =
0 V
ICD1
Control Supply/
Discharge Current
mA
132 kHz
Operation
Output MOSFET Disabled
VX, VV = 0 V
ICD2
0.3
0.5
1.2
27
www.powerint.com
Rev. B 03/10
TOP264-271
NOTES:
A. Derived during test from the parameters DCMAX, IB and IC(OFF) at 132 kHz.
B. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with
increasing temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with increasing
temperature.
C. Guaranteed by characterization. Not tested in production.
D. For externally adjusted current limit values, please refer to Figures 34 and 35 (Current Limit vs. External Current Limit Resistance)
in the Typical Performance Characteristics section. The tolerance specified is only valid at full current limit.
E. I2f calculation is based on typical values of ILIMIT andfOSC, i.e. ILIMIT(TYP)2 × fOSC, where fOSC = 66 kHz or 132 kHz depending on F pin
connection. See fOSC specification for detail.
F. The device will start up at 18 VDC drain voltage. The capacitance of electrolytic capacitors drops significantly at temperatures
below 0 °C. For reliable start up at 18 V in sub zero temperatures, designers must ensure that circuit capacitors meet recom-
mended capacitance values.
G. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not
exceeding minimum BVDSS
.
28
Rev. B 03/10
www.powerint.com
TOP264-271
t
2
t
1
HV
90%
90%
t
t
DRAIN
VOLTAGE
1
2
D =
10%
0 V
PI-2039-033001
Figure 30. Duty Cycle Measurement.
t
(Blanking Time)
LEB
120
100
80
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
I
INIT(MIN)
60
40
Dynamic
Impedance
1
=
Slope
20
0
0
5
6
7
8
9
0
1
2
3
4
5
6
7
8
CONTROL Pin Voltage (V)
Time (µs)
Figure 31. CONTROL Pin I-V Characteristic.
Figure 32. Drain Current Operating Envelope.
(X and V Pins)
S1
470 Ω
5 W
0-300 kΩ
5-50 V
40 V
V
D
CONTROL
470 Ω
C
S2
F
X
S
S4
0-15 V
S3
0-60 kΩ
47 µF
0.1 µF
NOTES: 1. This test circuit is not applicable for current limit or output characteristic measurements.
Figure 33. TOPSwitch-JX General Test Circuit.
29
www.powerint.com
Rev. B 03/10
TOP264-271
Typical Performance Characteristics
PI-5581-090309
1.1
1
1.1
1
Maximum
0.9
0.8
0.7
0.6
0.5
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Typical
Minimum
0.4
t
Normalized Current Limit
0.3
Notes:
1. Maximum and Minimum levels are
based on characterization.
2. TJ = 0 OC to 125 OC.
0.2
0.1
0
-200
-150
-100
-50
0
IX (µA)
Figure 34. Normalized Current Limit vs. X Pin Current.
PI-5582-090309
1.1
1
1.1
1
Notes:
1. Maximum and Minimum levels are
based on characterization.
2. TJ = 0 OC to 125 OC.
3. Includes the variation of X pin voltage.
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
s)
Maximum
µ
Typical
N
Normalized Current Limit (A)
0.2
Minimum
15
0.1
0
0
5
10
20
25
30
35
40
45
RIL ( kΩ )
Figure 35. Normalized Current Limit vs. External Current Limit Resistance.
30
Rev. B 03/10
www.powerint.com
TOP264-271
Typical Performance Characteristics (cont.)
1.2
1.0
0.8
0.6
0.4
1.1
1.0
0.9
0.2
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Junction Temperature (°C)
Figure 37. Frequency vs. Temperature.
Junction Temperature (°C)
Figure 36. Breakdown Voltage vs. Temperature.
1.2
1.0
0.8
0.6
0.4
0.2
1.2
1.0
0.8
0.6
0.4
0.2
0
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Junction Temperature (°C)
Junction Temperature (C)
Figure 39. External Current Limit vs. Temperature with RIL = 10.5 kW.
Figure 38. Internal Current Limit vs. Temperature.
1.2
1.0
1.2
1.0
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Junction Temperature (°C)
Figure 41. Undervoltage Threshold vs. Temperature.
Junction Temperature (C)
Figure 40. Overvoltage Threshold vs. Temperature.
31
www.powerint.com
Rev. B 03/10
TOP264-271
Typical Performance Characteristics (cont.)
6
5.5
5
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
VX = 1.354 - 1147.5 × IX + 1.759 × 106 ×
(IX)2 with -180 µA < IX < -25 µA
4.5
4
3.5
3
2.5
2
0
-200
0
100
200
300
400
500
-150
-100
-50
0
VOLTAGE-MONITOR Pin Current (µA)
EXTERNAL CURRENT LIMIT Pin Current (µA)
Figure 42. VOLTAGE-MONITOR Pin vs. Current.
Figure 43. EXTERNAL CURRENT LIMIT Pin Voltage vs. Current.
1.2
1.0
0.8
0.6
0.4
0.2
1.2
1.0
0.8
0.6
0.4
0.2
0
0
-50 -25
0
25 50 75 100 125 150
-50 -25
0
25 50 75 100 125 150
Junction Temperature (°C)
Junction Temperature (°C)
Figure 45. Maximum Duty Cycle Reduction Onset Threshold
Current vs. Temperature.
Figure 44. Control Current Out at 0% Duty Cycle vs. Temperature.
5
4
1
VC = 5 V
0.5
0
3
-0.5
Scaling Factors:
TOP271 1.62
TOP270 1.42
-1
-1.5
-2
2
TOP269 1.17
TOP268 1.00
TOP267 0.85
TOP266 0.61
TOP265 0.42
TOP264 0.32
1
TCASE = 25 °C
TCASE = 100 °C
0
-2.5
0
2
4
6
8
10 12 14 16 18 20
0
20
40
60
80
100
Drain Voltage (V)
Drain Pin Voltage (V)
Figure 46. Output Characteristics.
Figure 47. IC vs. DRAIN Voltage.
32
Rev. B 03/10
www.powerint.com
TOP264-271
Typical Performance Characteristics (cont.)
500
10000
Scaling Factors:
TOP271 1.62
TOP270 1.42
TOP269 1.17
TOP268 1.00
TOP267 0.85
TOP266 0.61
TOP265 0.42
TOP264 0.32
Scaling Factors:
TOP271 1.62
TOP270 1.42
TOP269 1.17
TOP268 1.00
TOP267 0.85
TOP266 0.61
TOP265 0.42
TOP264 0.32
400
300
132 kHz
1000
100
10
200
100
0
66 kHz
0
100 200 300 400 500 600
0
100 200 300 400 500 600 700
Drain Pin Voltage (V)
Figure 48. COSS vs. DRAIN Voltage.
Drain Pin Voltage (V)
Figure 49. DRAIN Capacitance Power.
1.2
1.0
0.8
0.6
0.4
0.2
0
-50 -25
0
25 50 75 100 125 150
Junction Temperature (°C)
Figure 50. Remote OFF DRAIN Supply Current vs. Temperature.
33
www.powerint.com
Rev. B 03/10
TOP264-271
eSIP-7C (E Package)
C
2
0.403 (10.24)
0.397 (10.08)
0.264 (6.70)
Ref.
0.081 (2.06)
0.077 (1.96)
A
B
Detail A
2
0.290 (7.37)
Ref.
0.325 (8.25)
0.320 (8.13)
0.198 (5.04) Ref.
0.519 (13.18)
Ref.
0.207 (5.26)
0.187 (4.75)
Pin #1
I.D.
0.016 (0.41)
Ref.
0.140 (3.56)
0.120 (3.05)
3
4
0.047 (1.19)
0.118 (3.00)
SIDE VIEW
0.070 (1.78) Ref.
0.033 (0.84)
0.028 (0.71)
0.010 M 0.25 M C A B
6×
0.100 (2.54)
0.050 (1.27)
0.016 (0.41)
0.011 (0.28)
3
6×
0.020 M 0.51 M C
FRONT VIEW
BACK VIEW
0.100 (2.54)
10° Ref.
All Around
0.050 (1.27)
0.050 (1.27)
0.020 (0.50)
0.060 (1.52)
Ref.
0.021 (0.53)
0.019 (0.48)
PIN 1
0.048 (1.22)
0.046 (1.17)
0.019 (0.48) Ref.
0.155 (3.93)
0.059 (1.50)
0.378 (9.60)
Ref.
0.023 (0.58)
0.027 (0.70)
PIN 7
END VIEW
0.059 (1.50)
Notes:
DETAIL A
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.100 (2.54)
0.100 (2.54)
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but including
any mismatch between the top and bottom of the plastic
body. Maximum mold protrusion is 0.010 [0.25] per side.
MOUNTING HOLE PATTERN
(not to scale)
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches [mm].
PI-4917-042010
34
Rev. B 03/10
www.powerint.com
TOP264-271
eDIP-12 (V Package)
0.004 [0.10] C A
12×
2
Seating Plane
C
0.400 [10.16]
0.016 [0.41]
0.011 [0.28]
Pin #1 I.D.
(Laser Marked)
0.316 [8.03]
Ref.
A
0.010 [0.25] Ref.
0.059 [1.50]
Ref, typ.
2X
6
1
1
2
3
4
5
6
0.004 [0.10] C B
7
0.412 [10.46]
Ref.
2
0.400 [10.16]
8
0.213 [5.41]
Ref.
0.350 [8.89]
0.306 [7.77]
Ref.
0.059 [1.50]
Ref, typ.
0.436 [11.08]
0.406 [10.32]
B
12 11 10
9
8
7
7
12
3
12×
4
0.023 [0.58]
0.018 [0.46]
Detail A
°
°
4
5
TOP VIEW
0.104 [2.65] Ref.
0.010 (0.25) M C A B
END VIEW
BOTTOM VIEW
0.092 [2.34]
0.086 [2.18]
Notes:
0.356 [9.04]
Ref.
1. Dimensioning and tolerancing
per ASME Y14.5M-1994.
0.019 [0.48]
Ref.
0.049 [1.23]
0.046 [1.16]
2. Dimensions noted are determined
at the outermost extremes of the plastic
body exclusive of mold flash, tie bar
burrs, gate burrs, and interlead flash,
but including any mismatch between the
top and bottom of the plastic body.
3. Dimensions noted are inclusive of
plating thickness.
4. Does not include inter-lead flash or
protrusions.
5. Controlling dimensions in inches (mm).
6. Datums A & B to be determined at Datum H.
7. Measured with the leads constrained to be
perpendicular to Datum C.
0.022 [0.56]
Ref.
0.192 [4.87]
Ref.
H
0.031 [0.80]
0.028 [0.72]
0.020 [0.51]
Ref.
0.070 [1.78]
0.028 [0.71]
Ref.
SIDE VIEW
DETAIL A (Not drawn to scale)
8. Measured with the leads unconstrained.
9. Lead numbering per JEDEC SPP-012.
PI-5556-122109
Part Ordering Information
• TOPSwitch Product Family
• JX Series Number
• Package Identifier
E
Plastic eSIP-7C
Plastic eDIP-12
V
• Pin Finish
G
Halogen Free and RoHS Compliant
• Tape & Reel and Other Options
Blank Standard Configurations
TOP 264
E
G - TL
35
www.powerint.com
Rev. B 03/10
Revision
Notes
Date
A
B
B
Release data sheet.
Added eDIP parts.
Page 4 “latching” changed to “hysteretic”. Table 4 updated.
01/10
01/10
03/10
For the latest updates, visit our website: www.powerint.com
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Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.
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POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
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and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
©2010, Power Integrations, Inc.
Power Integrations Worldwide Sales Support Locations
World Headquarters
5245 Hellyer Avenue
Germany
Japan
Taiwan
. .
Rueckertstrasse 3
D-80336, Munich
Germany
Phone: +49-89-5527-3910
Fax: +49-89-5527-3920
e-mail: eurosales@powerint.com Phone: +81-45-471-1021
Fax: +81-45-471-3717
Kosei Dai-3 Bldg.
2-12-11, Shin-Yokomana,
Kohoku-ku
Yokohama-shi Kanagwan
222-0033 Japan
5F, No. 318, Nei Hu Rd., Sec. 1
Nei Hu Dist.
Taipei, Taiwan 114, R.O.C.
Phone: +886-2-2659-4570
Fax: +886-2-2659-4550
e-mail: taiwansales@powerint.com
San Jose, CA 95138, USA.
Main: +1-408-414-9200
Customer Service:
Phone: +1-408-414-9665
Fax: +1-408-414-9765
e-mail: usasales@powerint.com
India
e-mail: japansales@powerint.com Europe HQ
China (Shanghai)
Room 1601/1610, Tower 1
Kerry Everbright City
No. 218 Tianmu Road West
Shanghai, P.R.C. 200070
Phone: +86-21-6354-6323
Fax: +86-21-6354-6325
#1, 14th Main Road
Vasanthanagar
Bangalore-560052 India
Phone: +91-80-4113-8020
Fax: +91-80-4113-8023
e-mail: indiasales@powerint.com Seoul, 135-728, Korea
Phone: +82-2-2016-6610
1st Floor, St. James’s House
East Street, Farnham
Surrey GU9 7TJ
Korea
RM 602, 6FL
Korea City Air Terminal B/D, 159-6 United Kingdom
Samsung-Dong, Kangnam-Gu, Phone: +44 (0) 1252-730-141
Fax: +44 (0) 1252-727-689
e-mail: eurosales@powerint.com
e-mail: chinasales@powerint.com Italy
Via De Amicis 2
Fax: +82-2-2016-6630
e-mail: koreasales@powerint.com Applications Hotline
World Wide +1-408-414-9660
China (Shenzhen)
20091 Bresso MI
Italy
Phone: +39-028-928-6000
Fax: +39-028-928-6009
e-mail: eurosales@powerint.com Singapore, 308900
Phone: +65-6358-2160
Rm A, B & C 4th Floor, Block C,
Electronics Science and
Technology Bldg., 2070
Shennan Zhong Rd,
Singapore
51 Newton Road
#15-08/10 Goldhill Plaza
Applications Fax
World Wide +1-408-414-9760
Shenzhen, Guangdong,
China, 518031
Fax: +65-6358-2015
Phone: +86-755-8379-3243
Fax: +86-755-8379-5828
e-mail: chinasales@powerint.com
e-mail: singaporesales@powerint.com
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