3236-22 [PSEMI]
2200 MHz UltraCMOS-TM Integer-N PLL for Low Phase Noise Applications; 2200兆赫的UltraCMOS -TM整数N分频PLL的低相位噪声应用
| 型号： | 3236-22 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 2200 MHz UltraCMOS-TM Integer-N PLL for Low Phase Noise Applications |
| 文件： | 总15页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE3236
2200 MHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Product Description
Features
Peregrine’s PE3236 is a high performance integer-N PLL
capable of frequency synthesis up to 2.2 GHz. The
superior phase noise performance of the PE3236 is ideal
for applications such as LMDS / MMDS / WLL basestations
and demanding terrestrial systems.
• 2.2 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
The PE3236 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired. This
programming flexibility, combined with the dual latch
architecture enabling ping-pong loading of the main divide
counter, makes these PLLs well suited as the core for
fractional-N or sigma-delta implementation.
• Serial, parallel or hardwired
programmable
• Low power— 22 mA at 3 V
• Q3236 PLL replacement
• Ultra-low phase noise
• Available in 44-lead PLCC package
The PE3236 is optimized for terrestrial applications. It is
manufactured on Peregrine’s UltraCMOS™ process, a
patented variation of silicon-on-insulator (SOI) technology
on a sapphire substrate, offering the performance of GaAs
with the economy and integration of conventional CMOS.
Figure 1. Block Diagram
Fin
Fin
Prescaler
10 / 11
Main
Counter
fp
13
D(7:0)
8
Sdata
Primary
20-bit
Latch
Secon-
dary
20-bit
Latch
PD_U
Phase
Detector
PD_D
20
20
20
20
16
Pre_en
M(6:0)
A(3:0)
R(3:0)
6
6
fr
R Counter
fc
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©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
PE3236
Product Specification
Figure 2. Pin Configurations (Top View)
Figure 3. Package Type
44-lead PLCC
6
5
4
3
2
1
44 43 42 41 40
D0, M0
D1, M1
fc
7
8
39
38
37
36
35
34
33
32
31
30
29
VDD_fc
PD_U
PD_D
VDD
D2, M2
9
D3, M3
10
11
12
13
14
15
16
17
VDD
VDD
Cext
S_WR, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
VDD
Dout
VDD_fp
fp
GND
18 19 20 21 22 23 24 25 26 27 28
Table 1. Pin Descriptions
Pin No. Pin Name
Interface Mode
Type
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
1
VDD
ALL
(Note 1)
2
3
4
5
6
R0
Direct
Direct
Direct
Direct
ALL
Input
R Counter bit0 (LSB).
R Counter bit1.
R1
Input
R2
Input
R Counter bit2.
R3
Input
R Counter bit3.
GND
D0
(Note 1)
Input
Ground.
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
7
8
M0
D1
Input
Input
M1
D2
Input
9
Input
Parallel data bus bit2.
M Counter bit2.
M2
D3
Input
10
Input
Parallel data bus bit3.
M Counter bit3.
M3
VDD
VDD
Input
11
12
(Note 1)
(Note 1)
Same as pin 1.
ALL
Same as pin 1.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
Page 2 of 15
PE3236
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name
Interface Mode
Type
Description
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data are transferred to the secondary register on S_WR or Hop_WR
rising edge.
S_WR
Serial
Input
13
D4
Parallel
Direct
Input
Input
Parallel data bus bit4.
M Counter bit4.
M4
Sdata
Serial
Input
Input
Input
Input
Input
Input
Input
Input
Input
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
14
15
16
D5
Parallel
Direct
M5
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Sclk
D6
Serial
Parallel
Direct
Parallel data bus bit6.
M Counter bit6.
M6
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
FSELS
D7
Serial
Parallel
Direct
Parallel data bus bit7 (MSB).
Pre_en
GND
FSELP
A0
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Ground.
17
18
ALL
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
Parallel
Direct
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
Serial
E_WR
19
Parallel
Direct
A1
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
M2_WR
A2
Parallel
Direct
20
21
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
Smode
A3
Serial, Parallel
Direct
A Counter bit3 (MSB).
Bmode
VDD
Selects direct interface mode (Bmode=1).
Same as pin 1.
22
23
24
25
26
27
ALL
ALL
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
M1_WR
A_WR
Parallel
Parallel
Serial, Parallel
ALL
Hop_WR
Fin
Prescaler input from the VCO. 2.2 GHz max frequency.
Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
Fin
28
29
ALL
ALL
Input
GND
Ground.
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Page 3 of 15
PE3236
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name
Interface Mode
Type
Description
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
30
31
32
33
fp
ALL
Output
VDD-fp
Dout
VDD
ALL
(Note 2)
Output
VDD for fp.
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
Serial, Parallel
ALL
(Note 1)
Same as pin 1.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
34
Cext
ALL
Output
35
36
37
38
39
40
41
42
43
44
VDD
ALL
(Note 1)
Output
Same as pin 1.
PD_D
PD_U
VDD-fc
fc
PD_D is pulse down when fp leads fc.
PD_U is pulse down when fc leads fp.
VDD for fc.
ALL
ALL
ALL
(Note 2)
Output
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
ALL
GND
GND
fr
ALL
Ground.
ALL
Ground.
ALL
Input
Reference frequency input.
Output,
OD
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
LD
ALL
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Enh
Serial, Parallel
Input
Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
Note 2: VDD pins 31 and 38 are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp
and fc outputs.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
Page 4 of 15
PE3236
Product Specification
Table 2. Absolute Maximum Ratings
Table 4. ESD Ratings
Symbol
Parameter/Conditions Min Max Units
Symbol
Parameter/Conditions
Level
Units
ESD voltage (Human Body
Model)
VDD
VI
Supply voltage
-0.3
-0.3
-10
-10
-65
4.0
VDD
V
V
VESD
1000
V
+
Voltage on any input
DC into any input
0.3
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
II
+10
mA
mA
°C
Electrostatic Discharge (ESD) Precautions
IO
DC into any output
Storage temperature range
+10
150
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Tstg
Table 3. Operating Ratings
Symbol
Parameter/Conditions Min Max Units
VDD
Supply voltage
2.85
3.15
V
Latch-Up Avoidance
Operating ambient
temperature range
TA
-40
85
°C
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Operational supply current;
Prescaler enabled
IDD
VDD = 2.85 to 3.15 V
22
35
mA
Digital Inputs: All except fr, R0, Fin, Fin
VIH
VIL
IIH
High level input voltage
Low level input voltage
High level input current
Low level input current
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
0.7 x VDD
V
V
0.3 x VDD
+1
µA
µA
IIL
VIL = 0, VDD = 3.15 V
-1
Reference Divider input: fr
IIHR High level input current
IILR Low level input current
R0 Input (Pull-up Resistor): R0
IIHRO High level input current
IILRO Low level input current
Counter and phase detector outputs: fc, fp
VIH = VDD = 3.15 V
+100
+5
µA
µA
VIL = 0, VDD = 3.15 V
-100
VIH = VDD = 3.15 V
µA
µA
VIL = 0, VDD = 3.15 V
-5
VOLD
VOHD
Output voltage LOW
Output voltage HIGH
Iout = 6 mA
Iout = -3 mA
0.4
V
V
VDD - 0.4
Lock detect outputs: Cext, LD
VOLC
VOHC
VOLLD
Output voltage LOW, Cext
Iout = 0.1 mA
Iout = -0.1 mA
Iout = 1 mA
0.4
0.4
V
V
V
Output voltage HIGH, Cext
Output voltage LOW, LD
VDD - 0.4
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Page 5 of 15
PE3236
Product Specification
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see Figures 4, 5, 6)
fClk
tClkH
tClkL
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
(Note 1)
10
MHz
ns
30
30
ns
Sdata set-up time to Sclk rising edge, D[7:0] set-up time to
M1_WR, M2_WR, A_WR rising edge
tDSU
10
ns
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
tDHLD
tPW
tCWR
tCE
tWRC
tEC
10
30
30
30
30
30
ns
ns
ns
ns
ns
ns
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
E_WR transition to Sclk rising edge
Main Divider (Including Prescaler)
Fin
Operating frequency
Input level range
200
-5
2200
5
MHz
dBm
PFin
External AC coupling
External AC coupling
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
Input level range
20
-5
220
5
MHz
dBm
PFin
Reference Divider
fr
Operating frequency
(Note 3)
100
20
MHz
dBm
Pfr
Reference input power (Note 2)
Single ended input
-2
Phase Detector
fc
Comparison frequency
(Note 3)
MHz
SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C)
100 Hz Offset
1 kHz Offset
-75
-85
dBc/Hz
dBc/Hz
Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2: CMOS logic levels can be used to drive the reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Note 3: Parameter is guaranteed through characterization only and is not tested.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
Page 6 of 15
PE3236
Product Specification
Functional Description
The PE3236 consists of a prescaler, counters, a
phase detector and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired direct to the pins. There
are also various operational and test modes and
lock detect.
Figure 4. Functional Block Diagram
R Counter
fr
fc
(6-bit)
D(7:0)
R(5:0)
M(8:0)
A(3:0)
PD_U
PD_D
Phase
Control
Logic
Sdata
Detector
Control
Pins
LD
Cext
Modulus
Select
Fin
Fin
10/11
M Counter
(9-bit)
fp
Prescaler
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PE3236
Product Specification
Main Counter Chain
Register Programming
The main counter chain divides the RF input
frequency, Fin, by an integer derived from the user
defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9 bit M counter. Setting
Pre_en “low” enables the 10/11 prescaler. Setting
Pre_en “high” allows Fin to bypass the prescaler
and powers down the prescaler.
Parallel Interface Mode
Parallel Interface Mode is selected by setting the
Bmode input “low” and the Smode input “low”.
Parallel input data, D[7:0], are latched in a
parallel fashion into one of three, 8-bit primary
register sections on the rising edge of M1_WR,
M2_WR, or A_WR per the mapping shown in
Table 7 on page 9. The contents of the primary
register are transferred into a secondary register
on the rising edge of Hop_WR according to the
timing diagram shown in Figure 5. Data are
transferred to the counters as shown in Table 7
on page 9.
The output from the main counter chain, fp, is
related to the VCO frequency, Fin, by the following
equation:
fp = Fin / [10 x (M + 1) + A]
(1)
where A ≤ M + 1, 1 ≤ M ≤ 511
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This
double buffering for “ping-pong” counter control
is programmed via the FSELP input. When
FSELP is “high”, the primary register contents
set the counter inputs. When FSELP is “low”, the
secondary register contents are utilized.
When the loop is locked, Fin is related to the
reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
(2)
where A ≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of
E_WR according to the timing diagram shown in
Figure 5. This data provides control bits as
shown in Table 8 on page 9 with bit functionality
enabled by asserting the Enh input “low”.
When the prescaler is bypassed, the equation
becomes:
Fin = (M + 1) x (fr / (R+1))
(3)
Serial Interface Mode
where 1 ≤ M ≤ 511
Serial Interface Mode is selected by setting the
Bmode input “low” and the Smode input “high”.
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low.
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (Sdata input), B0
to B19, are clocked serially into the primary
register on the rising edge of Sclk, MSB (B0)
first. The contents from the primary register are
transferred into the secondary register on the
rising edge of either S_WR or Hop_WR
according to the timing diagram shown in
Figures 5-6. Data are transferred to the counters
as shown in Table 7 on page 9.
Reference Counter
The reference counter chain divides the reference
frequency, fr, down to the phase detector
comparison frequency, fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
fc = fr / (R + 1)
(4)
The double buffering provided by the primary
and secondary registers allows for “ping-pong”
counter control using the FSELS input. When
FSELS is “high”, the primary register contents
set the counter inputs. When FSELS is “low”, the
secondary register contents are utilized.
where 0 ≤ R ≤ 63
Note that programming R equal to “0” will pass the
reference frequency, fr, directly to the phase
detector.
In Direct Interface Mode, R Counter inputs R4 and
R5 are internally forced low (“0”).
While the E_WR input is “high” and the S_WR
input is “low”, serial input data (Sdata input), B0
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
Page 8 of 15
PE3236
Product Specification
to B7, are clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B0) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
6. After the falling edge of E_WR, the data provide
control bits as shown in Table 8 on with bit
functionality enabled by asserting the Enh input
“low”.
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M7 and M8, and R Counter inputs
R4 and R5 are internally forced low (“0”).
Table 7. Primary Register Programming
Interface
Mode
Smode
R5
R4
M8
M7
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Enh
Bmode
Pre_en
M2_WR rising edge load
M1_WR rising edge load
A_WR rising edge load
Parallel
1
0
0
D3
B0
0
D2
B1
0
D1
B2
0
D0
B3
0
D7
B4
D6
B5
D5
B6
D4
B7
D3
B8
D2
B9
D1
B10
M1
D0
B11
M0
D7
B12
R3
D6
B13
R2
D5
B14
R1
D4
B15
R0
D3
B16
A3
D2
B17
A2
D1
D0
Serial*
Direct
1
1
0
1
1
B18 B19
A1 A0
X
Pre_en M6
M5
M4
M3
M2
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Power
down
Counter
load
MSEL
output
Prescaler
output
Smode
Reserved
Reserved
Reserved
fc, fp OE
Enh
Bmode
E_WR rising edge load
Parallel
Serial*
0
0
X
X
0
1
D7
B0
D6
B1
D5
B2
D4
B3
D3
B4
D2
B5
D1
B6
D0
B7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
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Page 9 of 15
PE3236
Product Specification
Figure 5. Parallel Interface Mode Timing Diagram
tDSU
tDHLD
[7: 0]
D
tPW
tCWR
tWRC
M1_WR
M2_WR
A_WR
tPW
E_WR
Hop_WR
Figure 6. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
Page 10 of 15
PE3236
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved**
Reserved**
Reserved**
Power down
Counter load
MSEL output
Prescaler output
fp, fc OE
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and Smode inputs.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the raw internal prescaler output onto the Dout output.
fp, fc outputs disabled.
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_D pulses “low”. If the divided reference leads
the divided VCO in phase or frequency (fc leads
fp), PD_U pulses “low”. The width of either pulse
is directly proportional to phase offset between the
two input signals, fp and fc.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kΩ resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “AND”
function of PD_U and PD_D.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses
result in an increase in VCO frequency and PD_D
results in a decrease in VCO frequency.
Document No. 70-0026-03 │ www.psemi.com
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 15
PE3236
Product Specification
Figure 7. PE3236 Typical Phase Noise vs. Offset (VDD = 3.0 V, Temp = 25° C)
-60
-70
Frequency = 1915MHz.
Reference Frequency = 10MHz.
Loop Band Width = 40kHz.
-80
-90
Comparison Frequency = 1MHz.
-100
-110
-120
100
1000
104
105
106
Offset From Carrier (Hz.)
Figure 8. PE3236 Typical Input Sensitivity vs. Frequency (VDD = 3.0 V, Temp = 25° C)
10
0
-10
-20
-30
-40
500
1000
1500
2000
Frequency (Hz.)
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
Page 12 of 15
PE3236
Product Specification
Handling Requirements
All surface mount products which do not meet
Level 1 moisture sensitivity requirements are
processed through dry bake and pack procedure.
The necessary data is recorded on the caution
label of each shipment. The 44-lead PLCC
package is moisture sensitivity Level 3.
Level 3 Caution Label
Level and Body temperature defined by:
IPC/JEDEC-J-STD-020
The caution label should contain the following
information for Level 3 devices:
1. Calculated shelf life in sealed bag: 12 months
at <40 °C and <90% relative humidity (RH)
For Dry Bake Procedures, see:
IPC/JEDEC-J-STD-033
2. Peak package body temperature is 225 °C.
Operator must observe ESD precautions per
ESD Control Procedure and Parts Handling and
shipping Procedure.
3. After bag is opened, devices that will be
subjected to reflow solder or other high
temperature process must
a) Be mounted within 168 hours of factory
conditions <30 °C/60% RH, or
b) Be stored at <10% RH
4. Devices require bake, before mounting, if:
a) Humidity Indicator Card is > 10% when
read at 23 ± 5 °C
b) 3a or 3b are not met
5. If baking is required, devices may be baked for
48 hours at 125 +5/-0 °C
Note: If device containers cannot be subjected to
high temperature or shorter bake times are
desired, reference IPC/JEDEC-J-STD-033 for
bake procedure.
Document No. 70-0026-03 │ www.psemi.com
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 13 of 15
PE3236
Product Specification
Figure 9. Package Drawing
44-lead PLCC
0.690±0.005
0.653±0.003
0.045 X 45°
0.010 X 45°
1*
4*
0.020 MIN.
R0.025
PIN 1
SURFACE
MOUNT
POINT
0.610 ±0.020
2*
3*
A
DETAIL
BOTTOM VIEW
0.027 (WIDTH OF LEAD SLOT)
*EJECT PIN POSITION
0.070
Ø0.040
DIMENSIONS ARE IN INCHES
TOLERANCES ARE ± 0.004
50X 45°
0.180 MAX.
0.070
0.004
0.010
SEE DETAIL A
Table 10. Ordering Information
Order Code
3236-21
Part Marking
PE3236
Description
Package
Shipping Method
PE3236-44PLCC-27A
44-lead PLCC
44-lead PLCC
44-lead PLCC
27 units / Tube
500 units / T&R
1 / Box
3236-22
PE3236
PE3236-44PLCC-500C
3236-00
PE3236EK
PE3236-44PLCC-EVAL KIT
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
Page 14 of 15
PE3236
Product Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corporation
Peregrine Semiconductor K.K.
9450 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Fax: 858-731-9499
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor, Korea
#B-2402, Kolon Tripolis, #210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-480 S. Korea
Tel: +82-31-728-4300
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
Fax: +82-31-728-4305
South Asia Pacific
Space and Defense Products
Americas:
Peregrine Semiconductor, China
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Tel: 858-731-9453
Fax: +86-21-5836-7652
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence Cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
Document No. 70-0026-03 │ www.psemi.com
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 15 of 15
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